JPS63303516A - D/a converting device - Google Patents

Abstract

PURPOSE:To realize the D/A converting device of a high accuracy and a high bit with two cheap D/A converters with low accuracy and the low number of bits by adding analogly the output of high-order and low-order D/A converters after it is weighted. CONSTITUTION:Concerning respective values of a high-order D/A converter 7, the dislocation from (2<m> pieces in total) ideal values is measured, this is converted with 1 LSB unit of a low-order D/A converter 13 and written into a memory 11. The high-order (m) bit data of input data are supplied to the high-order D/A converter 7, and fed to the address of the memory 11. Since the above-mentioned error data are accumulated in the memory 11, an error value (digital quantity) corresponding to respective high-order (m) bits of the input data is obtained. The difference between the low-order (n) bit of the input data and the above-mentioned error value is calculated by a digital adder 12, supplied to the low-order D/A converter 13, synthesized with the output of the high-order D/A converter 7 with a weighting adder 9 (analog), and outputted to an output terminal 10.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a DA converter, and an object of the present invention is to realize a high-precision DA converter by combining DA converters with low precision.

[Conventional technology]

Conventionally, a configuration shown in FIG. 2 has been used as an example of a high-precision D/A converter. 1 to 6 are digital input terminals, 7 is a l)/A converter that converts the upper n bits to 1)/A, and 8 is a D/A converter for the lower n bits. 9 represents each output of the D/A converter 7 and the D/A converter 8.
This is an analog adder that performs weighting and addition using a ratio of :l.

[Problem that the invention seeks to solve]

In order to maintain the accuracy of the D/A converter with such a configuration within 1/ZLSB, K is set so that the accuracy of the D/A converter 7 is
It is necessary to suppress fn+1 to less than 1/ZLSB of , so a relative precision v of 1/2 is required. For example, m=4. Even when n=4, a relative accuracy of 1/2, ie, Q, 4% is required; when m=9, a relative accuracy of 1/2, ie, 0.0004% is required. It is difficult to achieve such precision without adjustment, and even more so on an integrated circuit.

[Means for solving problems]

The present invention measures the error of the L)/A converter 7 on the upper side in advance and stores it in a memory, gives the input data of the upper side 1)/A converter to the address of the memory, and outputs the memory. An adder for taking the difference from the input data of the L)/A converter on the lower side, and the output of the adder on the lower side 1i1.
1 D/A converter, and weights the outputs of the above and lower D/A converters and adds them in an analog manner.

〔Example〕

FIG. 1 shows a first embodiment of the present invention, and the same parts as in FIG. 2 are given the same numbers and their explanation will be omitted.

11 is a memory in which the error of the D/A converter 7 on the upper side is measured and written in advance, 12 is a digital adder, and 13 is the 1)/A converter on the lower side, as shown in FIG. l)
The /A converter 8 and υ are also L)/A converters that have a larger number of sibits than the adder 12's carry and carry portions shown in FIG.

According to the present invention, prior to use of this device, the upper D/
Measure the deviation from the ideal value for each value of the A converter 7 (total of 2 m), and measure this deviation from the IL 8 of the D/A converter 13 on the lower side.
Convert it in B units and write it in Memo IJII. When using this device, the upper m bits of input data are supplied to the upper D/A converter 7 and also to the address of the memory 11 mentioned above. Since the above-mentioned error data is stored in the memory 11, the top m of the input data
An error value (digital amount) corresponding to each bit is obtained. A digital adder 12 (or subtracter) calculates the difference between the lower n bits of the input data and the error value, and provides it to the lower D/A converter 13, and a weight adder 9 (analog) calculates the difference between the lower n bits of the input data and the error value. )/A converter 7 and output to the output terminal 1o.

In this case, it is possible to correct the error of the upper L)/A converter 7, but not the error of the lower D/A converter 13, but the accuracy of the latter is rougher because it is weighted more heavily than the former. Since it is good, there are no practical problems. Furthermore, since the error data of the upper 1ilIID/A7 is considered to be less than this L8B/2, which corresponds to the full scale of the lower D/A 13, the word structure of the memory 11 may be n bits. Since the adder 12 performs subtraction between n bits and g, the width is n+1 bits, so n+1 bits,
1)/A converter 13 is required.

[Embodiment 2] The lower L)/A converter 13 shown in the first embodiment needed to be capable of positive and negative outputs, but a constant was added in advance to prevent it from becoming negative. You can leave it there.

In this case, a second adder (not shown) may be used, but the same result can be obtained by simply writing the complement of the error and the sum of the constants in the memory in advance. Depending on the above constant, the voltage at the output terminal will deviate by the above constant, but when used for audio etc., there is no problem at all since a DC component is not required. Alternatively, level shift circuits for the above constants may be added as necessary (not shown).

By using K in this manner, there is an advantage that an inexpensive D/A converter that can operate on a single power supply can be configured with a /A converter that can only provide positive output.

FIG. 3 shows a third embodiment of the present application.

Dl-D8 is the digital data input terminal during actual use, DI
N is a digital data input terminal when writing data to a cell, and is a CLli clock input terminal. Also 28 is EP
ROM, 21 is an address counter for reading the contents of the memory, and 29 is a shift register for parallelizing the read contents of the memory. 24 is a full adder, 25 and 26 are upper and lower D/A converters, and 27 is an adder. 0
8 is an analog data output terminal.

The basic operation is the same as that of the first embodiment, and in this embodiment as well, the deviation from the ideal value is measured for each value of the upper-side D/A converter 25, and the lower-side D/A converter 26 It is necessary to convert it in units of ILSB and write it into memory.

The first feature of this example is that EFROM is used as the memory, and electrical table data can be written.

When correction data measured in advance is serially applied to the terminal DIN, it is input to the write circuit 22, and the data is stored in the memory cell 23 by the write circuit.

The second feature of this example is that data from memory cells is sequentially read out by the address counter 21 and the shift register 29
The point is that the data is converted to parallel data.

In the memory cell 23, data is stored by shifting the Vrt of each cell, but it is the sense amplifier 28 that completely determines whether T is high or low, that is, whether it is "high" data or 6-low data. If the address counter 21 sequentially reads out the 4-bit correction data as in this example, only one sense amplifier 28 is required.
The method of reading bit data in parallel requires four sense amplifiers, eliminating the need for the address counter 21 and shift register 29. LS the above two methods
Comparing the area of the I-chip, the method that requires only one sense amplifier is considerably smaller.

In other words, when the capacity of the memory cell itself is not so large as in this example (for example, in Fig. 3, 2 x 4 = 64
(2048 cells in the case of 16 bits (cell, upper 8 bits, and lower 8 bits)) Within the EFROM section, the ratio of the area of memory cells and circuits other than memory cells is large, and the area of circuits other than memory cells is large, and the sense amplifier Reducing the area by one K is effective in reducing the area of the entire LSI.

Next, the data for which the sense amplifier 28 determines that "high" is 10-" is input to the shift register 29. The shift register 29 converts the data sequentially sent from the sense amplifier 28 into parallel data and sends it to the full adder 24. The full adder 24 adds the correction data from the shift register described above and the lower data D5 to D8. The subsequent operation is similar to that of the first embodiment.

〔Effect of the invention〕

As described above, according to the present invention, two inexpensive 1)/A converters with low precision and a low number of bits are used to achieve high precision and high bit D/A converters.
A conversion device can be realized.

Note that by using a RAM as the memory of the present invention, it is possible to execute a calibration cycle when the power is turned on or as necessary, and write error data to the RAM. Or as a memory P)! , OM can be used to omit error data at the time of factory shipment.

In this case, since it is unlikely that the user will readjust it at a later date, a one-time PROM or a heasel OM can be used.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an L)/A converter according to the present invention, FIG. 2 is an example of a conventional L)/A converter, and FIG.
The figure shows a third embodiment of the present invention. 1 to 6...Input terminal, 7...Upper side L
)/A converter, 8...lower side 1)/A converter,
9... Weighting adder, lO... Output terminal, 11... Memory, 12... Adder, 13... Lower side D/A converter. Agent: Susumu Uchihara, 'Tomi゛1\(XJ)
stomach) ? '-r)N)

Claims (1)

[Claims] A first m-bit DA converter that operates according to the upper m bits of input digital data, a second DA converter that operates according to the lower n bits, and their outputs. In the DA converter, there is provided a 2^m word memory in which errors for each of the 2^m values of the first DA converter are measured and written in advance, and a memory of 2^m words for the input data. It has means for reading out the memory using the upper m bits as an address, and an adder circuit for adding or subtracting the contents of the memory and the lower n bits of the input data, and the output of the adder is added to the second DA. A DA converter connected to the input of the converter, and characterized in that the second DA converter is a DA converter that covers the maximum possible value (greater than n bits) of the addition result of the adder. .