JP4892499B2 - Digital / analog converter - Google Patents

Description

  The present invention relates to a current cell type digital-to-analog converter (hereinafter referred to as “DAC”), and more particularly to a current value adjusting function of a unit current cell through which the unit current flows.

FIG. 2 is a configuration diagram of a general current cell type DAC.
The DAC outputs analog voltage AV corresponding to the digital signal DS of 10 bits input, 31 pieces of unit current cells for outputting a unit current I, respectively _(UC) unit current having a 10 1 _{to 10 31} The cell group 10 and fractional current cells (FC) 21, 22, 23 that output a constant current weighted to 1/32, 1/16, 1/8 /, 1/4, 1/2 of the unit current I, respectively. , 24, 25, the fractional current cell group 20 is provided.

  The operations of the fractional current cells 21 to 25 of the fractional current cell group 20 are respectively controlled by the lower 5 bits b0 to b4 of the 10-bit digital signal DS, and are weighted when the corresponding bit is a logical value “1”. A constant current is output to the node N20.

On the other hand, the output currents of the unit current cells 10 ₁ to 10 ₃₁ of the unit current cell group 10 are controlled by the values of the upper 5 bits b5 to b9 of the 10-bit digital signal DS. That is, the output side of the unit current cells ₁₀ 1 _{to 10 31,} via the corresponding switches ₃₀ 1 _{to 30 31} of the switch group 30 is connected to the node N30, the switches ₃₀ 1 _{to 30 31} switch control unit 40 On / off control is performed by a selection control signal from. The switch control unit 40 outputs a selection control signal for turning on the same number of switches (= 0 to 31) as the value based on the upper 5 bits b5 to b9 of the digital signal DS.

  The current I30 of the unit current cell group 10 output from the node N30 is added to the current I20 of the fractional current cell group 20 output from the node N20, and is supplied to the current-voltage converter 50. The current-voltage converter 50 outputs an analog voltage AV corresponding to the input current (I20 + I30).

  In this DAC, the unit current I output from the same number of unit current cells is added by the switch group 30 according to the value (ie, 0 to 31) designated by the upper 5 bits of the 10-bit digital signal DS, and the node N30 is output as current I30. On the other hand, in the fractional current cell group 20, the fractional current cells 21 to 25 are controlled in accordance with the lower 5 bits of the 10-bit digital signal DS, and the values of the lower 5 bits (that is, 0 to 31/32) are controlled. A current is output from node N20 as current I20.

  The currents I20 and I30 are added and given to the current-voltage conversion unit 50, converted into a voltage corresponding to the magnitude of the current, and output as an analog voltage AV.

Here, when the accuracy of the DAC is considered, the error in the output current of each of the unit current cells 10 ₁ to 10 ₃₁ of the unit current cell group 10 is at least the resolution of the current I20 of the fractional current cell group 20 (ie, the unit current). It is meaningless unless it is 1/32) or less of I. In particular, considering that the currents of 10 or more unit current cells are added, the current error of the unit current cell needs to be 1/10 or less. is there. In general, in a semiconductor integrated circuit, it is difficult to form elements having exactly the same characteristics even in the same chip due to variations in the concentration of source gas and temperature in the manufacturing process. For this reason, a unit current cell that places importance on current accuracy is often provided with a current value adjusting function.

FIG. 3 is a configuration diagram of a conventional unit current cell having a current value adjusting function.
This unit current cell is provided as each unit current cell 10 ₁ to 10 ₃₁ in FIG. 2, and includes a fuse circuit composed of six sets of resistors 11a to 11f and fuses 12a to 12f, a decoder (DEC) 13, and a fine adjustment Constant current sources 14 _{1 to} 14 ₆₃ and a main constant current source 15.

In the fuse circuit, a resistor 11j and a fuse 12j (where j = af) are connected in series between a power supply potential VDD and a ground potential GND, and a level “ A signal of H ″ (that is, power supply potential VDD) is output. The decoder 13 outputs a control signal to the constant current sources 14 _{1 to} 14 ₆₃ for fine adjustment according to the value of the signal output according to the states of the six fuses 12a to 12f of the fuse circuit. .

Each of the constant current sources 14 _{1 to} 14 ₆₃ outputs, for example, a current of about 3/1000 of the unit current I when controlled to the output state by the control signal. On the other hand, the main constant current source 15 outputs a base current of about 9/10 of the unit current I irrespective of the control signal.

In this unit current cell, when all of the constant current sources 14 _{1 to} 14 ₆₃ are in the OFF state, a base current of about (9/10) I flows from the constant current source 15 and all of the constant current sources 14 _{1 to} 14 ₆₃ are in the ON state. In this case, a total current of (11/10) I flows from the constant current sources 14 _{1 to} 14 ₆₃ and the constant current source 15. That is, the unit current cell can adjust the output current with an error of about 0.3% between 90% and 110% of the unit current I by setting the adjustment fuses 12a to 12f.

Japanese Patent No. 2504773 Japanese Patent Laid-Open No. 11-239059

However, each unit current cell of the DAC has six fuses for adjustment. Therefore, 186 fuses are required for the entire unit current cell group 10 having ₃₁ unit current cells 10 ₁ to 10 ₃₁ .

  Since the fuse is selectively burned out by laser beam irradiation or current when adjusting the current value, it is necessary to arrange the fuse at a certain distance so that the adjacent fuse is not affected at the time of cutting. For this reason, there is a problem that a larger layout area is required compared with other circuit elements such as transistors and resistors, and the entire chip area is increased. Further, since it is necessary to set six fuses for each unit current cell, there is a problem that a test time for current adjustment or the like increases. Furthermore, there is a problem that adjustment is impossible due to defective manufacture of the fuse itself, and the yield is lowered.

  The main object of the present invention is to reduce the layout area of a chip by reducing the number of adjustment fuses used in a unit current cell group of a current cell type DAC.

  The present invention provides a current cell group having a plurality of unit current cells that generate the same constant current, and a switch that generates a selection control signal for selecting the number of unit current cells according to the value of a given digital signal. Selecting a unit current cell of the current cell group in accordance with the selection control signal, adding a constant current generated by the selected unit current cell, and outputting a current output from the switch; In a DAC including a current-voltage conversion unit that converts an analog voltage, a current cell group is configured as follows.

  That is, one specific unit current cell among the plurality of unit current cells of the current cell group is added to the first main current source that outputs the base current and the base current of the first main current source. A plurality of first adjustment current sources for outputting an adjustment current for generating the constant current, and M for generating a first control signal for current value adjustment (where M is an integer of 3 or more) ) And a first control unit for controlling the operation of the first adjustment current source in accordance with the first control signal.

  Further, among the plurality of unit current cells of the current cell group, unit current cells other than the specific unit current cell are respectively a second main current source that outputs a base current and a second main current source that outputs a base current. A plurality of second adjustment current sources for outputting an adjustment current for generating the constant current by adding to the base current, and N for generating a correction signal for current value adjustment (where N is from M A second fuse circuit having a smaller integer than 2), an adder for adding the first control signal and the correction signal to generate a second control signal, and the second control signal And a second control unit for controlling the operation of the second adjustment current source.

  In the present invention, M fuses for generating a first control signal for current value adjustment are provided in one specific unit current cell among the plurality of unit current cells of the current cell group, Each unit current cell other than the unit current cell is provided with N fuses for generating a correction signal to be added to the first control signal. Since the correction signal may have a narrower control range than the first control signal, M> N can be satisfied. Thereby, there is an effect that the total number of fuses in the current cell group can be reduced.

  The above and other objects and novel features of the present invention will become more fully apparent when the following description of the preferred embodiment is read in conjunction with the accompanying drawings. However, the drawings are for explanation only, and do not limit the scope of the present invention.

FIG. 1 is a configuration diagram of a unit current cell group showing Embodiment 1 of the present invention.
This unit current cell group is used as the unit current cell group 10 in the DAC of FIG. 2, and includes one reference unit current cell 10R serving as a reference and the other 30 unit current cells 10A1, 10A2,. It is configured.

For example, when the unit current cells are arranged in a matrix as shown in FIG. 2, the reference unit current cell 10R is a unit current cell arranged almost at the center of the matrix (in the case of FIG. 2, the unit current cell 10 ₁₅ ). It is. This is because the characteristics of the unit current cell change little by little depending on the arrangement position due to variations in the manufacturing process, but the unit current cell at the center is considered to have an average characteristic. The unit current 1 of the reference unit current cell 10R is always selected by a selection control signal from the switch control unit 40 when one or more unit current cells are selected based on the digital signal DS. .

Similarly to the conventional unit current cell shown in FIG. 3, the reference unit current cell 10R is composed of a fuse circuit including six sets of resistors 11a to 11f and fuses 12a to 12f, a decoder (DEC) 13, and a constant current for fine adjustment. It is composed of a constant current circuit including sources 14 _{1 to} 14 ₆₃ and a main constant current source 15.

  The fuse circuit of the reference unit current cell 10R is configured such that a resistor 11j and a fuse 12j (where j = af) are connected in series between the power supply potential VDD and the ground potential GND, and the fuse 12j is disconnected to disconnect its connection point. A signal of level “H” (that is, power supply potential VDD) is output. The control signals Sa to Sf output according to the states of the six fuses 12a to 12f of the fuse circuit represent a binary number with a sign in which the signal Sa is a sign bit and the signal Sf is a least significant bit. I have to. That is, values in the range of −32 to +31 are output by the control signals Sa to Sf.

The decoder 13 outputs an operation control signal to the constant current sources 14 _{1 to} 14 ₆₃ for fine adjustment according to the values of the control signals Sa to Sf output from the fuse circuit. That is, when the values of the control signals Sa to Sf are −32, an operation control signal for turning off all the constant current sources 14 _{1 to} 14 ₆₃ (turning on zero constant current sources) is output. When the values of the control signals Sa to Sf are +32, an operation control signal for turning on all the constant current sources 14 _{1 to} 14 ₆₃ (turning on the 63 constant current sources) is output. That is, when the value of the control signals Sa to Sf is K (K = −32 to +31), the decoder 13 outputs an operation control signal for simultaneously turning on (32 + K) constant current sources. ing.

Each of the constant current sources 14 _{1 to} 14 ₆₃ outputs, for example, a current of about 3/1000 of the unit current I when controlled to the output state by the operation control signal. On the other hand, the main constant current source 15 always outputs a base current of about 9/10 of the unit current I irrespective of the operation control signal.

  On the other hand, the other 30 unit current cells 10A1, 10A2,... Have the same configuration. For example, as shown as the unit current cell 10A1, a fuse circuit including three sets of resistors 11g to 11i and fuses 12g to 12i, The constant current circuit is similar to the adder (ADD) 16, the decoder 13, and the reference unit current cell 10R.

  In the fuse circuit of the unit current cell 10A1, a resistor 11k and a fuse 12k (where k = g to i) are connected in series between the power supply potential VDD and the ground potential GND, and the fuse 12k is cut to the connection point. A correction signal of level “H” (that is, power supply potential VDD) is output. The correction signals Sg to Si output in accordance with the states of the three fuses 12g to 12i of the fuse circuit represent a signed binary number having the signal Sg as a sign bit and the signal Si as a least significant bit. I have to. That is, values in the range of -4 to +3 are output by the correction signals Sg to Si.

  The adder 16 is a binary number with a sign by the correction signals Sg to Si output from the fuse circuit of the unit current cell 10A1, and a sign by the control signals Sa to Sf output from the fuse circuit of the reference unit current cell 10R. Is added to the binary number. The addition result of the adder 16 is given to the decoder 13.

The decoder 13 of the unit current cell 10A1 has the same function as the decoder of the unit current cell 10A1, and according to the addition result of the adder 16, the constant current sources 14 _{1 to} 14 ₆₃ for fine adjustment of the constant current circuit are used. An operation control signal is output. That is, when the addition result of the adder 16 is K (K = −32 to +31), the decoder 13 outputs an operation control signal for simultaneously turning on (32 + K) constant current sources. Yes.

  The other components of the DAC using the unit current cell group (the fractional current cell group 20, the switch group 30, and the current-voltage conversion unit 50) are the same as the general current cell type DAC shown in FIG. It is the same. Further, as described above, the switch control unit 40 generates a selection control signal for turning on the same number of switches as the value (= 0 to 31) based on the upper 5 bits b5 to b9 of the digital signal DS. Although output, when one or more switches are turned on, the switch corresponding to the reference unit current cell 10R is always turned on.

  Next, a method for adjusting each unit current cell of the unit current cell group in the DAC of FIG. 2 provided with the unit current cell group of FIG. 1 will be described.

  First, a binary number “0000011111” is input as a 10-bit digital signal DS, and an adjustment signal (not shown) is given. This adjustment signal is a test fractional current cell (not shown) that is provided in parallel with the fractional current cell 21 of the fractional current cell group 20 of FIG. 2 and outputs the same constant current (1/32 of the unit current I) during adjustment. ). Thereby, current is output from the fractional current cells 21 to 25 of the fractional current cell group 20 and the test fractional current cell, and the total current I20 coincides with the unit current I. On the other hand, since the unit current cell of the unit current cell group 10 is not selected, the current I30 output from the switch group 30 is zero. At this time, the value of the analog voltage AV output from the current-voltage converter 50 is recorded as a reference voltage corresponding to the unit current I.

  Next, the adjustment signal is stopped and the binary number “0000100000” is input as the digital signal DS. As a result, the current I20 output from the fractional current cell group 20 becomes zero. On the other hand, in the switch group 30, only the current output from the reference unit current cell 10R of the unit current cell group 10 is selected and supplied to the current-voltage converter 50 as the current I30. At this point, the analog voltage AV output from the voltage converter 50 is measured and compared with the previously recorded reference voltage. Based on the difference between the measured voltage and the reference voltage, a fuse to be cut is determined among the fuses 12a to 12f of the reference unit current cell 10R, and the corresponding fuse is cut. (It is assumed that which fuse is to be cut according to the difference from the reference voltage is determined in advance by a test using a test chip.)

As a result, the control signals Sa to Sf of the fuse circuit of the reference unit current cell 10R are set, and the fine adjustment constant current sources 14 _{1 to} 14 ₆₃ in the constant current circuit are supplied from the decoder 13 in accordance with the control signals Sa to Sf. An operation control signal is output. In this state, it is confirmed that the analog voltage AV output from the voltage converter 50 is within the allowable error range with respect to the previously recorded reference voltage.

  Next, the digital signal DS is changed to the binary number “0000001”. Thereby, in the switch group 30, in addition to the reference unit current cell 10R of the unit current cell group 10, the current output from the other unit current cell 10A1 is selected, and the current I30 is supplied to the current-voltage converter 50. Given. In the adder 16 of the unit current cell 10A1, the control signals Sa to Sf of the reference unit current cell 10R and the correction signals Sg to Si of the fuse circuit are added, but the fuses 12g to 12i of the fuse circuit are in an uncut state. Therefore, the values of the correction signals Sg to Si are 0. Therefore, the addition result of the adder 16 becomes the same value as the control signals Sa to Sf of the reference unit current cell 10R, and the constant current circuit of the unit current cell 10A1 is controlled to the same state as the constant current circuit of the reference unit current cell 10R. The

  At this time, since the reference unit current cell 10R and the unit current cell 10A1 of the unit current cell group 10 are formed in the same matrix by the same manufacturing process, the constant current circuit of the reference unit current cell 10R and the unit current cell 10A1. There is little difference in characteristics. At this point, the analog voltage AV output from the voltage converter 50 is measured and compared with the previously recorded reference voltage. Then, the fuse to be cut is determined among the fuses 12g to 12i of the unit current cell 10A1 so that the measured voltage becomes twice the reference voltage, and the corresponding fuse is cut.

Thereby, the correction signals Sg to Si of the fuse circuit of the unit current cell 10A1 are set, and the correction signals Sg to Si and the control signals Sa to Sf of the reference unit current cell 10R are added by the adder 16. Then, according to the addition result, an operation control signal is output from the decoder 13 to the constant current sources 14 _{1 to} 14 ₆₃ for fine adjustment in the constant current circuit. In this state, it is confirmed that the analog voltage AV output from the voltage conversion unit 50 is within an allowable error range with respect to twice the previously recorded reference voltage.

  Similarly, the digital signal DS is sequentially increased by 1 and the correction signals Sg to Si of the remaining 29 unit current cells 10A2 to 10A30 are sequentially set.

  As described above, in the unit current cell group of the first embodiment, a specific one of the plurality of unit current cells is set as the reference unit current cell 10R, and is distinguished from the remaining plurality of unit current cells 10A. The reference unit current cell 10R has six fuses for generating control signals Sa to Sf for adjusting so as to output the unit current I, and the other unit current cell 10A is composed of three fuses. The correction signals Sg to Si are generated to adjust the difference from the output current of the reference unit current cell 10R. Thereby, there is an advantage that the number of fuses in the unit current cell group can be almost halved (strictly speaking, in the case of this embodiment, the number is reduced from 186 to 96).

  Further, in the unit current cells 10A other than the reference unit current cell 10R, the correction fuses 12g to 12i may be cut according to the difference from the output current of the reference unit current cell 10R. Therefore, if there is no difference in the output current, there is no need to cut the correction fuses 12g to 12i, and there is an advantage that the test time for unit current adjustment and the like can be significantly reduced. Further, since the number of fuses decreases, there is no possibility that adjustment cannot be performed due to manufacturing defects of the fuses themselves and the yield is reduced.

  FIG. 4 is a configuration diagram of a unit current cell group showing Embodiment 2 of the present invention. Elements common to those in FIG. 1 are denoted by common reference numerals.

  In this unit current cell group, unit current cells 10B2,... Slightly different from each other are provided in place of the second and subsequent unit current cells 10A2,. That is, the adder 16 of the unit current cell 10B2 adds the control signals Sa1 to Sf1 of the addition result of the adder 16 of the adjacent unit current cell 10A1 and the correction signals Sg to Si from the fuse circuit, and controls the addition result. Signals Sa2 to Sf2 are supplied to the decoder 13 and to the adder of the adjacent unit current cell in the subsequent stage. Other configurations (reference unit current cell 10R and unit current cell 10A1) are the same as those in FIG.

Here, the reference unit current cells 10R, as described in Example 1, may be the unit current cells 10 ₁₅ arranged substantially in the center of the matrix in FIG. 2, the unit current cells located at the end of the matrix 10 _{1 is} also acceptable. The adjustment method of each unit current cell of the unit current cell group connected in this way is as described in the first embodiment.

  As described above, in the unit current cell group of the second embodiment, in the remaining plurality of unit current cells 10B other than the reference unit current cell 10R, adjacent unit current cells (in some cases, the reference unit current cell 10R may be included). The difference from the output current of the other unit current cell 10B is adjusted by the correction fuses 12g to 12i. As a result, the difference in output current between the unit current cells is expected to be very small, so that the adjustment range can be reduced. In addition to the same advantages as in the first embodiment, the correction fuse There is an advantage that the number of can be further reduced.

In addition, this invention is not limited to the said Example, A various deformation | transformation is possible. Examples of this modification include the following.
(A) The number of fuses in the fuse circuit of the reference unit current cell 10R and the other unit current cells 10A and 10B is not limited to that illustrated. That is, if the reference unit current cell uses an integer M of 3 or more and the other unit current cells use an integer N of 2 or more smaller than M, the same effect can be obtained.
(B) The constant current circuit uses 63 constant current sources that generate the same current for fine adjustment. However, if a constant current source that generates weighted current for fine adjustment is used, the constant current circuit The number of current sources can be reduced. In this case, it is necessary to change the configuration of the decoder that controls the constant current circuit.
(C) The DAC of FIG. 2 to which the unit current cell group of the first and second embodiments is applied includes the fractional current cell group 20 that outputs a current equal to or lower than the unit current I, but has the fractional current cell group 20. It is equally applicable to non-DACs. In this case, the setting of the fuse circuit of the reference unit current cell may be adjusted so that the analog voltage AV becomes a specified voltage when 1 is input as the digital signal DS.
(D) The configuration of the fuse circuit is not limited to that illustrated.
(E) The number of bits of the digital signal DS is not limited to ten. Further, the number of unit current cells and the number of fractional current cells are not limited to those illustrated.

It is a block diagram of the unit current cell group which shows Example 1 of this invention. It is a block diagram of a general current cell type DAC. It is a block diagram of the conventional unit current cell. It is a block diagram of the unit current cell group which shows Example 2 of this invention.

Explanation of symbols

10 unit current cell group 10R reference unit current cell 10A, 10B unit current cell 11 resistance 12 fuse 13 decoder 14, 15 constant current source 16 adder 20 fractional current cell group 21-25 fractional current cell 30 switch group 40 switch control unit 50 Current-voltage converter

Claims (4)

A current cell group having a plurality of unit current cells that generate the same constant current; a switch control unit that generates a selection control signal for selecting the number of unit current cells according to the value of a given digital signal; A switch that selects a unit current cell of the current cell group according to the selection control signal, adds a constant current generated by the selected unit current cell, and outputs the combined current, and converts the current output from the switch into an analog voltage In a digital-to-analog converter with a current-voltage converter
One specific unit current cell among the plurality of unit current cells of the current cell group is:
A first main current source that outputs a base current; and a plurality of first adjustment current sources that output an adjustment current for generating the constant current by adding to the base current of the first main current source; A first fuse circuit having M fuses (where M is an integer of 3 or more) for generating a first control signal for adjusting a current value, and the first adjustment according to the first control signal A first control unit that controls the operation of the current source;
Unit current cells other than the specific unit current cell among the plurality of unit current cells of the current cell group are respectively
A second main current source for outputting a base current; a plurality of second adjustment current sources for outputting an adjustment current for generating the constant current by adding to the base current of the second main current source; A second fuse circuit having N fuses (where N is an integer of 2 or more smaller than M) for generating a correction signal for current value adjustment, the first control signal, and the correction signal. An adder for adding and generating a second control signal; and a second control unit for controlling the operation of the second adjustment current source according to the second control signal.
Features a digital-to-analog converter. A current cell group having a plurality of unit current cells that generate the same constant current; a switch control unit that generates a selection control signal for selecting the number of unit current cells according to the value of a given digital signal; A switch that selects a unit current cell of the current cell group according to the selection control signal, adds a constant current generated by the selected unit current cell, and outputs the combined current, and converts the current output from the switch into an analog voltage In a digital-to-analog converter with a current-voltage converter
One specific unit current cell among the plurality of unit current cells of the current cell group is:
A first main current source that outputs a base current; and a plurality of first adjustment current sources that output an adjustment current for generating the constant current by adding to the base current of the first main current source; A first fuse circuit having M fuses (where M is an integer of 3 or more) for generating a first control signal for adjusting a current value, and the first adjustment according to the first control signal A first control unit that controls the operation of the current source;
Unit current cells other than the specific unit current cell among the plurality of unit current cells of the current cell group are respectively
A second main current source for outputting a base current; a plurality of second adjustment current sources for outputting an adjustment current for generating the constant current by adding to the base current of the second main current source; A second fuse circuit having N fuses (where N is an integer of 2 or more smaller than M) for generating a correction signal for current value adjustment; the first control signal or another unit current; An adder that generates a second control signal by adding the second control signal generated by the cell and the correction signal; and the second adjustment current source according to the second control signal generated by the adder. Having a second control unit for controlling the operation of
Features a digital-to-analog converter.   3. The digital unit according to claim 1, wherein the one specific unit current cell is a unit current cell arranged in a central portion among a plurality of unit current cells arranged in a matrix. 4. Analog converter.   The adder of the unit current cell other than the specific unit current cell includes the correction signal generated by the second fuse circuit of the unit current cell and the first or second control generated by the adjacent unit current cell. 3. The digital-to-analog converter according to claim 2, wherein the signal is added to generate a second control signal.

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