JP4639593B2 - Semiconductor integrated circuit, electro-optical device, electronic apparatus, and method of manufacturing semiconductor integrated circuit - Google Patents

Description

The present invention relates to a technique for generating a reference current having a desired magnitude in a drive circuit of an electro-optical device.

As an element for realizing a thin and low power consumption display device, a self-luminous element using organic electroluminescence (hereinafter referred to as an organic EL element) has attracted attention, and a display apparatus using the organic EL element has already been used. It has reached a practical level. Recently, it has been desired to increase the screen size of this type of display device. To that end, the number of data lines and scanning lines provided on the display panel is increased to make the display image as high-definition as possible. It is necessary to let However, a data line driving circuit or a scanning line driving circuit for driving a pixel is generally a MOSFET (Metal Oxide Semiconductor Field Effect Tr).
anfer), an increase in the number of data lines and scanning lines as described above results in an increase in the IC mounting area and a decrease in yield rate. There is a fear. Therefore, normally, the data line driving circuit and the scanning line driving circuit are each constituted by a plurality of ICs.

However, since the characteristics of each IC vary in the IC manufacturing process, for example, if the data line driving circuit is constituted by a plurality of ICs, the value of the driving current supplied to the data line for each IC. May be different. When the drive currents are different in this way, it is natural that areas with different emission luminances are generated on the display panel. Therefore, in order to solve this problem, in Patent Document 1, by using a reference current of the same value among a plurality of ICs one after another using a current mirror circuit, a driving current supplied from each IC to a data line is used. It has been proposed to align the values to approximately the same value.

However, the technique described in Patent Document 1 (hereinafter referred to as conventional technique) has the following problems. First, in the current mirror circuit used in the prior art, if the current flowing through the transistors constituting the circuit does not depend on the drain-source voltage Vds at all, A current of the same value can be supplied to the other transistor. However, in reality, there is some dependence on the drain-source voltage Vds, so that there is a possibility that the current value is slightly shifted in the current mirror circuit. Second, in the prior art, a dedicated wiring for supplying a reference current from one IC to the next must be provided between the ICs. Therefore, there is a problem that the mounting cost for this wiring increases. Third, when the reference current is repeatedly used between the ICs, noise may be mixed into the reference current due to the influence of other electronic circuits. When such noise is mixed, the value of the reference current is shifted, and the reference current having the same value cannot be reused between the ICs. Fourthly, the conventional technique has a plurality of I in the data line driving circuit.
Since it is intended only to make the reference currents substantially the same between C, no adjustment is made regarding adjusting the absolute value of the reference current to an appropriate magnitude. Therefore, when the data line driving circuit having such a configuration is actually used, first, the value of the reference current itself first applied to a plurality of IC groups constituting the data line driving circuit is strictly adjusted. It is necessary to keep. As described above, the four problems are included in the prior art, and some ingenuity is required to solve these problems.

By the way, when a manufacturer sells a display device, a method is generally adopted in which the specifications and performance of the device are disclosed and a portion advantageous to other products is advertised.
One such specification is the display panel emission luminance (cd / m ² ). However, since the characteristics of each IC vary as described above, even if the data line driving circuit is constituted by one IC, when compared between display devices of the same type manufactured at the same time, Variations in light emission luminance due to characteristic variations will occur. Of course, on the same display panel, there is no difference in light emission luminance, so it does not cause problems such as being difficult to see visually, but if the light emission luminance does not match the contents of the published specifications, The responsibility of the manufacturer guaranteeing the performance of the display device may be questioned.

JP 2001-42827 A

The present invention has been made in view of these circumstances, and an object thereof is to make it possible to make the light emission luminance uniform on the display panel even when the data line driving circuit is constituted by a plurality of ICs. Another object is to prevent a difference in light emission luminance between the display panels even when the data line driving circuit is constituted by one IC.

In order to solve this problem, the present invention provides a reference current generation circuit that generates a reference current having a predetermined value, a reference current generated by the reference current generation circuit, and a reference current specified for each of a plurality of colors. And a reference current generation circuit for each color that generates a reference current for each color based on the output level of each color, and a reference current for each color generated by the reference current generation circuit for each color And gradation data representing gradation in each color pixel,
Provided is a semiconductor integrated circuit including a D / A conversion circuit that outputs a current to be supplied to each pixel or a voltage to be applied to each pixel.

According to this semiconductor integrated circuit, based on the reference current generated by the reference current generation circuit, only the output level is indicated by the output ratio signal for each color, for example, a reference for each of a plurality of colors such as R, G, B. A current can be generated. Therefore, it is not necessary to generate the reference current independently for each of the plurality of colors. For example, even when the characteristics of a display panel to be driven by a data line driving circuit including the semiconductor integrated circuit having the above-described configuration are changed, the color tone can be easily adjusted.

In a preferred aspect of the present invention, the reference current generation circuit includes a plurality of transistors,
A plurality of fuses respectively provided on a path of current flowing through each of the transistors;
A path formed to add the current flowing through each of the transistors and output as a reference current, and any one of the plurality of fuses may output a reference current of a predetermined value. The fuse is cut or formed without being cut. According to this aspect, the magnitude of the reference current can be accurately adjusted by cutting an appropriate one of several fuses prepared in the reference current generating circuit. Of course, if the reference current has already reached a desired level with none of the fuses cut, these fuses need not be cut.

In another preferred embodiment, the reference current generating circuit includes a main transistor, 1
Or adding a plurality of adjustment transistors, one or a plurality of fuses provided on a path of current flowing through each of the adjustment transistors, and a current flowing through the main transistor and the adjustment transistor to generate the reference current And one of the one or the plurality of fuses is cut or the one or the plurality of fuses are connected so that a reference current having a predetermined value is output. All are formed without being cut. According to this aspect, the magnitude of the reference current is determined to some extent according to the driving capability of the main transistor, and the reference current is cut by cutting an appropriate one of the fuses prepared on the current path of the adjustment transistor. Can be adjusted more accurately. Of course, if the reference current has already reached a desired level with none of the fuses cut, these fuses need not be cut.

In another preferred aspect, the reference current generation circuit includes a threshold voltage compensation circuit that generates and outputs a constant current as the reference current regardless of a threshold voltage value of a transistor. According to this aspect, since the reference current that does not depend on the variation in the threshold voltage of the transistor is generated, the variation in the value of the reference current itself can be suppressed.

Further, the present invention is based on a reference current generation circuit that generates a reference current of a predetermined value, a reference current generated by the reference current generation circuit, and gradation data that represents a gradation in each pixel. A D / A conversion circuit that outputs a current to be supplied to each pixel or a voltage to be applied to each pixel, and the reference current generation circuit has a plurality of transistors and a constant value regardless of the threshold voltage value of the transistors. A threshold voltage compensation circuit that generates and outputs a current, a plurality of fuses respectively provided on a path of a current flowing through each of the transistors, and a current flowing through each of the transistors are added and output as the reference current A path formed in such a manner that any one of the plurality of fuses is cut or the plurality of fuses are output so that a reference current having a predetermined value is output. Any of the over's is to provide a semiconductor integrated circuit, characterized by being formed without being cut.

According to this semiconductor integrated circuit, a current that does not depend on variations in the threshold voltage of the transistor is generated, and the reference current is generated by adjusting this current by cutting the fuse. That is, since the variation in the reference current before the fuse is cut can be suppressed, the number of fuses prepared in advance can be reduced.

Further, the present invention is based on a reference current generation circuit that generates a reference current of a predetermined value, a reference current generated by the reference current generation circuit, and gradation data that represents a gradation in each pixel. A D / A conversion circuit that outputs a current to be supplied to each pixel or a voltage to be applied to each pixel, and the reference current generation circuit includes a main transistor, one or a plurality of adjustment transistors, and a threshold value of the transistor A threshold voltage compensation circuit that generates and outputs a constant current regardless of the voltage value; one or more fuses provided on a path of current flowing through the one or more adjustment transistors; and the main transistor And a path formed so that the current flowing through the adjustment transistor is added and output as the reference current, and a reference current having a predetermined value is output. It provides a semiconductor integrated circuit according to claim none urchin of said one or or the one or more fuses any of the plurality of fuses are cut is formed without being cut.

According to this semiconductor integrated circuit, a current that does not depend on variations in the threshold voltage of the transistor is generated, and the reference current is generated by adjusting this current by cutting the fuse. That is, since the variation in the reference current before the fuse is cut can be suppressed, the number of fuses prepared in advance can be reduced.

In a preferred aspect of the present invention, the reference current generation circuit includes at least two transistors having different drive capability ratios. When an input current input from an input terminal flows to one transistor, A current mirror circuit in which a current having a magnitude proportional to the driving capability ratio with respect to the input current flows is provided, and the generated reference current is input to an input terminal of the current mirror circuit. According to this aspect, the value of the reference current can be measured as a larger current value corresponding to the drive capability ratio, so even a slight deviation of the reference current can be measured.

In another preferred embodiment, the reference current generation circuit includes a switch that can be turned on / off provided on a current path provided with the fuse. According to this aspect, before selecting the fuse to be cut, the value of the reference current after cutting the fuse can be confirmed in advance by turning on and off the switch on the same path as the fuse.

Further, the present invention is based on a reference current generation circuit that generates a reference current of a predetermined value, a reference current generated by the reference current generation circuit, and gradation data that represents a gradation in each pixel. A D / A conversion circuit that outputs a current to be supplied to each pixel or a voltage to be applied to each pixel, and the reference current generation circuit has a plurality of transistors and a current path that flows through each of the transistors. A plurality of fuses provided respectively, a path formed to add the current flowing through each of the transistors and output as the reference current, and at least two transistors having different drive capability ratios, from the input end When the input reference current flows through one transistor, the other transistor has a magnitude proportional to the drive capability ratio with respect to the reference current. A current mirror circuit through which a current flows, and is formed by cutting any of the plurality of fuses or without cutting any of the plurality of fuses so that a reference current having a predetermined value is output. A semiconductor integrated circuit is provided.

According to these semiconductor integrated circuits, the value of the reference current can be measured as a larger current value corresponding to the drive capability ratio, and therefore even a slight deviation of the reference current can be measured. In addition, the magnitude of the reference current can be accurately adjusted by cutting an appropriate one of several fuses prepared in the reference current generating circuit.

Further, the present invention is based on a reference current generation circuit that generates a reference current of a predetermined value, a reference current generated by the reference current generation circuit, and gradation data that represents a gradation in each pixel. A D / A conversion circuit that outputs a current to be supplied to each pixel or a voltage to be applied to each pixel, and the reference current generation circuit includes a main transistor, one or a plurality of adjustment transistors, One or a plurality of fuses respectively provided on a path of a current flowing through a plurality of adjustment transistors, and a path formed to add the current flowing through the main transistor and the adjustment transistor and output as the reference current When the reference current input from the input terminal flows to one transistor, the other transistor has at least two transistors having different drive capability ratios. And a current mirror circuit in which a current having a magnitude proportional to the drive capability ratio with respect to the reference current flows in the star, and either one of the one or the plurality of fuses is output so that a reference current having a predetermined value is output. The semiconductor integrated circuit is characterized in that it is cut or is formed without cutting any one or the plurality of fuses.

According to these semiconductor integrated circuits, the value of the reference current can be measured as a larger current value corresponding to the drive capability ratio, and therefore even a slight deviation of the reference current can be measured. In addition, the magnitude of the reference current can be accurately adjusted by cutting an appropriate one of several fuses prepared in the reference current generating circuit.

Further, the present invention is based on a reference current generation circuit that generates a reference current of a predetermined value, a reference current generated by the reference current generation circuit, and gradation data that represents a gradation in each pixel. A D / A conversion circuit that outputs a current to be supplied to each pixel or a voltage to be applied to each pixel, and the reference current generation circuit has a plurality of transistors and a current path that flows through each of the transistors. A plurality of fuses and on / off switches provided respectively, and a path formed so as to output the reference current by adding the currents flowing through the transistors, and outputting a reference current of a predetermined value Thus, a semiconductor integrated circuit in which any one of the plurality of fuses is cut is provided.

According to this semiconductor integrated circuit, the magnitude of the reference current can be accurately adjusted by cutting an appropriate one of several fuses prepared in the reference current generating circuit. Further, before selecting a fuse to be cut, by turning on and off a switch on the same path as the fuse, the value of the reference current after cutting the fuse can be confirmed in advance.

Further, the present invention is based on a reference current generation circuit that generates a reference current of a predetermined value, a reference current generated by the reference current generation circuit, and gradation data that represents a gradation in each pixel. A D / A conversion circuit that outputs a current to be supplied to each pixel or a voltage to be applied to each pixel, and the reference current generation circuit includes a main transistor, one or a plurality of adjustment transistors, One or a plurality of fuses respectively provided on a path of a current flowing through a plurality of adjustment transistors, and a path formed to add the current flowing through the main transistor and the adjustment transistor and output as the reference current And either one of the one or more fuses is cut or one of the one or more fuses is output so that a reference current of a predetermined value is output. Also to provide a semiconductor integrated circuit, characterized in that it is formed without being cut.

According to this semiconductor integrated circuit, the magnitude of the reference current can be accurately adjusted by cutting an appropriate one of the fuses prepared in the reference current generating circuit. Further, before selecting a fuse to be cut, by turning on and off a switch on the same path as the fuse, the value of the reference current after cutting the fuse can be confirmed in advance.

Further, the present invention provides a plurality of pixels provided at each intersection of the data line and the scanning line, a data line driving circuit configured by the semiconductor integrated circuit as described above and supplying a data signal to the data line, An electro-optical device including a scanning line driving circuit for supplying a scanning signal to the scanning line is provided. The data line driving circuit may be constituted by one semiconductor integrated circuit, or may be constituted by a plurality of the semiconductor integrated circuits. In the former case, the light emission luminance is kept substantially the same between the electro-optical devices, and the published specifications and performance can be guaranteed. Further, in the latter case, the reference current can be accurately made to be almost the same value in the data line driving circuit including a plurality of semiconductor integrated circuits, and as a result, the emission luminance is kept almost uniform in all the pixels. be able to.

  In general, electronic devices can include the electro-optical device described above as a display device.

Further, the present invention provides a process of generating a current by a reference current generating circuit having a plurality of transistors, a process of measuring the generated current value as a current value having a magnitude proportional to the drive capability ratio of the transistor, and Any one of the plurality of fuses provided on the path of the current flowing through the plurality of transistors so that the value of the current generated by the reference current generation circuit is determined based on the measured current value. There is provided a method of manufacturing a semiconductor integrated circuit comprising a step of cutting the metal.

Further, the present invention provides a process of generating a current by a reference current generation circuit having a plurality of transistors, a process of measuring a value of the generated current, and the reference current generation circuit based on the measured current value. A process of turning on or off any of the plurality of switches respectively provided on the path of the current flowing through the plurality of transistors, and a state of turning on or off any of the switches so that the current value to be determined is a predetermined value Measuring the value of the current generated by the reference current generating circuit and cutting one of the plurality of fuses provided on the path of the current flowing through the plurality of transistors based on the measurement result. A method for manufacturing a semiconductor integrated circuit is provided.

Embodiments of the present invention will be described below.
(1) First Embodiment FIG. 1 is a diagram illustrating a configuration of an electro-optical device 10 according to a first embodiment. Display panel section 1
1, a plurality of data lines 111 extending in the Y direction in the drawing and a plurality of scanning lines 112 extending in the X direction in the drawing are provided so as to intersect each other. At each intersection, red (R), green (G)
The organic EL element 113 formed including the blue (B) light emitting layer is repeatedly formed in the X direction in a predetermined order (in this case, the order of R, G, B). Each organic EL element 113 corresponds to a sub-pixel, and a substantially square one pixel is constituted by three R, G, and B organic EL elements 113 adjacent in the X direction. In the present embodiment, one organic EL element 113 is 2
It is assumed that light emission is performed with 64 (= 2 ⁶ ) gradations according to the gradation number / 6-bit gradation data.
Accordingly, in the electro-optical device 10, when one pixel is viewed, 260,000 colors (= 2)
^{6 × 3} ) color display will be performed.

The data line driving circuit 12 and the scanning line driving circuit 13 are respectively a data line 111 and a scanning line 1.
12 is provided so as to be connected to one end. The control unit 14 converts image data representing an image to be displayed on the display panel unit 11 into gradation data representing a light emission gradation in each organic EL element 113, and scans the scanning line driving circuit 13 while performing timing control. A line signal is supplied, and gradation data for each organic EL element 113 is supplied to the data line driving circuit 12. The scanning line driving circuit 13 drives the scanning line 112 based on the supplied scanning line signal, and the data line driving circuit 12 drives the data line 111 based on the supplied gradation data.

Here, FIG. 2 is a block diagram showing a configuration of the data line driving circuit 12. The data line driving circuit 12 is composed of one IC, and includes a reference current generation circuit 121, a D / A converter 122 (hereinafter referred to as DACRGB 122), and a D / A converter 123R1,
123G1, 123B1, 123R2, 123G2, 123B2, ..., 123Rn,
123Gn, 123Bn (hereinafter referred to as DAC). Reference current generation circuit 12
1 generates and outputs a reference current Iref as a reference for driving the pixel. DACRGB1
Reference numeral 22 denotes a reference for each color used for driving the organic EL elements 113 of each color of R, G, B based on the reference current Iref and the output level of the reference current designated for each color of R, G, B. Generate and output currents Iref-R, Iref-G, and Iref-B. DAC123R1, 123
G1, 123B1 to 123Rn, 123Gn, and 123Bn are provided for each of the data lines 111, and the color-specific reference currents Iref-R, Iref-G, and Iref-B and the gradation data supplied from the control unit 14 are provided. Based on the above, the data signals (currents) IoutR1, IoutG1, IoutB1, IoutR2, IoutG2, IoutB2, IoutB2,
..., IoutRn, IoutGn, and IoutBn are generated and output. Hereinafter, these circuit configurations will be described in detail.

FIG. 3 is a circuit diagram showing a configuration of the reference current generation circuit 121. Reference current generation circuit 121
Includes six n-channel transistors 131 to 136 whose gates are connected to a reference voltage Vref via an input terminal T1. The sources of the transistors 131 to 136 are connected to a lower potential (ground potential Gnd), and the drains of the transistors 131 to 136 and the output terminal T2 are connected via fuses f1 to f6, respectively. That is, these fuses f1 to f6 are provided on a path of current flowing between the drain and source of each of the transistors 131 to 136. The fuses f1 to f6 are, for example, wirings made of aluminum or polysilicon formed in a relatively upper layer of the IC substrate, and are formed so as to be cut when irradiated with laser light.

Here, the relationship between the current I flowing between the source and drain of the transistor, the gain coefficient β of the transistor, and (in this case, the driving capability) is expressed by the equation I = (1/2) β (Vgs−Vth) ^2. . Note that Vgs means the gate voltage of the transistor, Vth means the threshold voltage of the transistor, and the gain coefficient β of the transistor is β = μCW / L
(Μ: carrier mobility, C: gate capacity, W: channel width, L: channel length). Therefore, if the β ratio changes, the current ratio also changes in proportion to it. For example, the β ratio of each transistor 131, 132, 133, 134, 135, 136 in FIG.
3: β4: β5: β6 = 1: 2: 4: 8: 16: 32 When the same reference voltage Vref is applied as a gate voltage to these transistors 131-136, the transistors 131-136 The ratio of the currents flowing through is 1: 2: 4: 8: 16: 32. And
These currents are added and output from the output terminal T2. Accordingly, by cutting any of the fuses f1 to f6, the value of the reference current Iref output from the output terminal T2 is set to 0 level to
Adjustment is possible in 64 levels of 63 levels. Since the reference current Iref is larger than 0, it is not actually adjusted to “0 level”.

A specific method for adjusting the reference current Iref is as follows.
After the IC including the reference current generation circuit 121 configured as described above is formed on the wafer, first, a reference voltage Vref is applied to the input terminal T1 using a measurement test circuit (not shown), and the transistor 131 To 136 are respectively connected to the lower potential (ground potential Gnd). Then, the current value output from the output terminal T2 is measured in a state where none of the fuses f1 to f6 is cut, and the measured current value is compared with the target reference current Iref. The fuses f1 to f6 are cut by laser light so that the measured current value becomes equal to the value of the reference current Iref. For example, all the fuses f1 to f6
The ratio of the current value measured when the current is not cut to the target reference current Iref is 6
In the case of 3:48, if the fuses f1, f2, f3, and f4 corresponding to β ratios of “1”, “2”, “4”, and “8” are cut off, Value is 48/63 before cutting
Thus, the reference current Iref having a desired value can be obtained. Note that the current value measured when the fuses f1 to f6 are not cut and the target reference current Ire
If the value of f matches, it is not necessary to cut any of the fuses f1 to f6.

Next, the configuration of the DACRGB 122 will be described with reference to the circuit diagram of FIG.
The DACRGB 122 includes a p-channel transistor 141 and three D / A conversion circuits 142 to 144 corresponding to R, G, and B colors. The source of the transistor 141 is connected to the higher potential (power supply potential VDD) and the gate and drain are short-circuited to form a diode connection. Each of the D / A conversion circuits 142 to 144 has the same configuration, and each includes three p-channel transistors having different driving capabilities. Selector 1
45 is provided to connect the input terminal T3 to either the drain of the transistor 141 or the pad 146, and the selector 145 connects the drain of the transistor 141 and the input terminal T3 as shown in FIG. Then, the reference current Iref output by the reference current generation circuit 121 is input to the DACRGB 122. The pad 146 is connected to the measurement test circuit, and it is confirmed by this measurement test circuit whether or not the reference current Iref has a desired value.

For example, in the D / A conversion circuit 142 corresponding to R, each of the transistors 143R-1,
The sources of 143R-2 and 143R-3 are connected to the high potential (power supply potential VDD), the gate is connected to the gate of the transistor 141, and the drain is the switch 144R.
-1, 144R-2 and 144R-3 are connected to the output terminal T4. The D / A conversion circuit 143 corresponding to G and the D / A conversion circuit 144 corresponding to B have the same configuration.

For example, in the D / A conversion circuit 142 corresponding to R, the switches 144R-1 to 144R-14.
4R-3 is turned on / off according to the color-specific output ratio signal DataRGB (r) supplied by the control unit 14. Even if the same current is supplied to the R, G, B organic EL elements,
Due to the characteristics of organic EL materials and human visual properties, the human eye does not appear to emit light at the same brightness, so the reference current for each color is adjusted to an appropriate value. There is a need to. The output ratio signals for each color DataRGB (r), DataRGB (g), and DataRGB (b) are R, G, and B, respectively.
Is a signal for instructing the output level of the reference currents Iref-R, Iref-G, and Iref-B defined for. Here, in order to adjust the output levels of the reference currents Iref-R, Iref-G, and Iref-B in eight stages, for example, with respect to R, transistors 144R-1 and 144R-2.144.
The β ratio of R-3 is set to 1: 2: 4, and the color-specific output ratio signal DataRGB (r) is represented by binary numbers and 3 bits. The least significant bit of the 3-bit string is the switch 14
4R-1, the middle bit corresponds to the switch 144R-2, the most significant bit corresponds to the switch 144R-3, the bit value "1" means switch on, and the bit value " “0” means switch-off. The D / A conversion circuit 143 corresponding to G and the D / A conversion circuit 144 corresponding to B have the same configuration.

As described above, the reference current generation circuit 121 generates a common reference current Iref for each color. For example, the ratio of the output levels of the R, G, and B reference currents to this reference current Iref is 7: 3: 4, the control unit 14 supplies the bit string data “111” as DataRGB (r) to the D / A conversion circuit 142 corresponding to R, so that the switch 144R−
1 to 144R-3 are all turned on. In addition, the control unit 14 sets “011” as DataRGB (g).
Is supplied to the D / A conversion circuit 143 corresponding to G, so that the switches 144G-1 and 144G-2 are turned on and the switch 144G-3 is turned off. Also,
The control unit 14 supplies the bit string data of “100” as DataRGB (b) to the D / A conversion circuit 144 corresponding to B, thereby turning on the switch 144B-3 and turning on the switch 144B−.
1, 144B-2 is turned off. Each of the transistors 143R-1 to 143R-3, 1
43G-1 to 143G-3 and 143B-1 to 143B-3 are supplied with currents corresponding to their β ratios, so the color-specific output ratio signals as described above are supplied to the D / A conversion circuits 142 to 144. R reference current Iref-R: G reference current Iref-G: B reference current Iref-B = 7:
3: 4 will be adjusted. The color-specific reference current I adjusted in this way
ref-R, Iref-G, and Iref-B are output from output terminals T4, T5, and T6, respectively, and DAC12
3R1, 123G1, 123B1 to 123Rn, 123Gn, 123Bn are input.

Next, the DACs 123R1, 123G1, 123B1 to 123Rn, 123Gn, 123
The configuration of Bn will be described using the configuration of the DAC 123R1 illustrated in FIG. 5 as an example.
The DAC 123R1 includes six n-channel transistors 151 to 156 that function as switching elements and six n-channel transistors 161 to 1 that function as drive elements.
66 and an n-channel transistor 170. The input terminal T7 has a DACRG
The reference current Iref-R output by B122 is input.

The gates of the respective transistors 151 to 156 have gradation data Data supplied from the control unit 14.
R1 is entered. The drains of the transistors 151 to 156 are connected to the output terminal T8, and the sources are connected to the drains of the transistors 161 to 166. Transistor 1
The gates 61 to 166 are connected to the input terminal T7, and the source is a low potential (ground potential Gn).
d) connected. The drain of the transistor 170 is connected to the input terminal T7, the source is connected to the lower potential (ground potential Gnd), and the gate and the source are short-circuited to form a diode connection. By adopting such a configuration, the transistor 170,
The transistors 161 to 166 form a current mirror circuit.

The gradation data DataR1 supplied from the control unit 14 to the transistors 151 to 156 is an H-level or L-level voltage signal corresponding to the gradation represented by a binary number of 6 bits. Here, the β ratio of the transistors 151 to 156 is 1: 2: 4: 8: 16: 32,
In the bit string of bit gradation data, the most significant bit corresponds to the transistor 156, the second bit from the most significant corresponds to the transistor 155, the third bit corresponds to the transistor 154, and the fourth bit is Corresponding to the transistor 153, the fifth bit corresponds to the transistor 152, and the least significant bit corresponds to the transistor 151. Also,
The bit value “1” means an H level voltage signal, and the bit value “0” means an L level voltage signal. For example, when the gradation data represents 8 gradation levels (that is, the bit string “0”).
In the case of “00100”, an H level voltage signal is input only to the transistor 153 from the control unit 14, and an L level voltage signal is input to the other transistors 151, 152, and 154 to 156. . As a result, the current IoutR1 having a value such that only the drain and the source of the transistor 153 are conductive and the organic EL element 113 emits light at eight gradation levels is output as a data signal from the output terminal T8 and supplied to the data line 111. Will be. In this way, each organic EL element 113 is driven, and as a result, an image is displayed on the display panel unit 11.

According to the first embodiment described above, a semiconductor integrated circuit (IC) including the reference current generation circuit 121 is formed by cutting an appropriate one of several fuses prepared in the reference current generation circuit 121. The value of the reference current Iref used in can be adjusted so as to approach the target value. Therefore, when the data line driving circuit 12 is constituted by one IC, the light emission luminance is kept substantially the same between the display devices, so that the manufacturer can guarantee the published specifications and performance. Note that as described above, when the reference current Iref already matches the target value in a state where none of the fuses is cut, it is not necessary to cut these fuses.
Further, based on the single reference current Iref generated as described above, the output ratio of each color is simply indicated by a group of signals called the output ratio signal for each color. Reference currents Iref-R, Iref-G, and Iref-B can be generated. Therefore, for example, even if the data line driving circuit 12 is the same and the characteristics of the display panel unit 11 to be driven are changed, it is possible to more easily perform the adjustment to obtain a desired color. it can.

(2) Second Embodiment In the second embodiment, considering that there is a variation in the threshold voltage of a transistor, the reference current Iref is generated without depending on this variation. The second embodiment is different from the first embodiment described above in that a reference current generating circuit 121 shown in FIG.
A reference current generating circuit 181 as shown in FIG. 6 is used, and the other configuration and operation are the same.

A reference current generation circuit 181 shown in FIG. 6 includes a circuit 182 for compensating a threshold voltage (hereinafter referred to as a threshold voltage compensation circuit 182) in addition to the configuration shown in FIG. The threshold voltage compensation circuit 182 includes a capacitor 183, an n-channel first transistor 184, an n-channel second transistor 185, and three switches 186, 187, and 188. One end of the capacitor 183 is connected to the gate of the first transistor 184,
The other end is connected to the input terminal T9 and is connected to the source of the first transistor 184 via the switch 187. The drain of the first transistor 184 is connected to a predetermined potential V 1, and the source is connected to the drain of the second transistor 185 via the switch 188. The source of the second transistor is connected to the lower potential (ground potential Gnd), the gate is connected to the gates of the transistors 131 to 136, and the gate and drain are short-circuited. By adopting such a configuration, the transistor 185 and the transistors 131 to 136 form a current mirror circuit.

The operation of the threshold voltage compensation circuit 182 is as follows. Note that the potential of the wiring portion from the capacitor 183 to the gate of the first transistor 184 is “Vg”.
First, in the threshold voltage compensation circuit 182, with the switches 186 and 187 turned on and the switch 188 turned off, a potential V0 that is lower than the predetermined potential V1 and lower than the threshold voltage Vth of the transistor 184. Is input to the input terminal T9. Next, switch 1
When 87 is turned off, the potential Vg = V1−Vth. Subsequently, after the switch 186 is turned off, the switch 188 is turned on, and the potential V lower than V0 at the input terminal T9.
When 0 ′ is input, a current corresponding to V0−V0 ′ = ΔV is output as the reference current Iref and output terminal T2
Is output from. The value of the reference current Iref does not depend on the threshold voltage Vth at all, but only depends on ΔV. Therefore, the value of the reference current Iref is almost constant regardless of the variation in the threshold voltage Vth.

According to the second embodiment, since the reference current Iref before cutting the fuses f1 to f6 can be prevented from varying due to the threshold voltage of the transistor, the number of fuses is reduced as compared with the first embodiment. In other words, the reference current Iref can be adjusted with high accuracy.

(3) Third Embodiment In the first embodiment, it is necessary to accurately measure the value of the reference current Iref output from the output terminal T2 when the fuses f1 to f6 are cut. Therefore, in the third embodiment, the reference current Ir
By measuring a larger current value proportional to the value of ef, it is possible to measure even a slight deviation of the reference current Iref. The third embodiment differs from the first embodiment described above in that a reference current generating circuit 19 as shown in FIG. 7 is used instead of the reference current generating circuit 121 shown in FIG.
1 is used, and other configurations and operations are the same.

A reference current generation circuit 191 shown in FIG. 7 includes a current mirror circuit 192 for generating a large current proportional to the value of the reference current Iref in addition to the configuration shown in FIG. The current mirror circuit 192 includes two p-channel transistors 193 and 194. The drain of the transistor 193 is connected to the fuses f1 to f6, the source is connected to the higher potential (power supply potential VDD), the gate is connected to the gate of the transistor 194 and short-circuited to the drain. On the other hand, the source of the transistor 194 is connected to the higher potential (power supply potential VDD), and the drain is connected to the pad 195.

The β ratio of these transistors 193 and 194 is larger in the transistor 194. For example, when the β ratio of the transistors 193 and 194 is 1: 4, a current corresponding to four times the reference current Iref input to the drain of the transistor 193 flows between the drain and source of the transistor 194. Therefore, when the fuses f1 to f6 are disconnected (that is, when the reference current Iref is measured), an external measurement test circuit is connected to the pad 195 to connect the pad 1
A potential at 95 is input, and the value of the current output from the pad 195 at that time is measured by a test circuit for measurement. Then, the fuses f1 to f6 to be cut may be selected in consideration that the value of the current corresponds to four times the reference current Iref. Since the reference current Iref is measured with a value increased four times in this way, even a slight deviation in the current value can be detected, and the reference current Iref can be adjusted more accurately. Note that the potential input to the pad 195 is preferably a potential that does not shift the operating points of the transistors 193 and 194. Further, in normal use after the fuse is cut, an open potential is used without making any electrical connection to the pad 195, or a higher potential (power supply potential VDD) is input to the pad 195. Thus, power consumption can be suppressed by preventing current from flowing through the transistor 194.

(4) Fourth Embodiment In the first embodiment, the fuses f1 to f6 are cut to adjust the reference current Iref.
When selecting the fuse to be cut, it is convenient if the value of the actual reference current Iref after cutting the fuse can be confirmed in advance. In order to meet such a demand, in the fourth embodiment, a reference current generation circuit 201 as shown in FIG. 8 is used in place of the reference current generation circuit 121 shown in FIG. Other configurations and operations are the same.

The reference current generation circuit 201 shown in FIG. 8 includes the fuses f1 to f in addition to the configuration shown in FIG.
6 and switches s1 to s6 interposed between the drains of the transistors 131 to 136. At the time of fuse cutting, driver IC from measurement test circuit (not shown)
The switches s1 to s6 are instructed to be turned on and off by a command, the value of the current generated by the reference current generation circuit 121 is measured in this state, and it is confirmed that the reference current Iref is adjusted to a desired value, and then the fuse f1 Any one of ~ f6 may be cut.

(5) Fifth Embodiment In the first to fourth embodiments described above, the case where the data line driving circuit 12 is configured by one IC has been described as an example. Needless to say, the circuit 12 may be composed of a plurality of ICs. For example, FIG. 9 shows an example in which the data line driving circuit is constituted by two ICs. In this example, one data line driving circuit 12a, 12b each constituted by one IC is used as a whole. A data line driving circuit is configured. Even in such a case, each data line driving circuit 1
A reference used in an IC (data line driving circuit) including the reference current generation circuit 121 by cutting an appropriate one of some of the fuses prepared in the reference current generation circuit 121 included in 2a and 12b. The magnitude of the current Iref can be adjusted to approach its target value. Therefore, the reference current Iref can be accurately adjusted to substantially the same value in the data line driving circuit 12a and the data line driving circuit 12b, and as a result, the light emission luminance can be kept substantially uniform over the entire surface of the display panel unit 11. it can.

(6) Application Examples The electro-optical device described above can also be applied to electronic equipment. The electronic device here is not particularly limited, but generally refers to a device that includes the electro-optical device according to the present invention as a display device. FIG. 10 is a perspective view showing a configuration of a mobile phone 300 having an electro-optical device to which the present invention is applied. As shown in FIG. 10, the mobile phone 300 is
In addition to a plurality of operation buttons 301 operated by a user, an earpiece 302 that outputs voice received from another terminal device, and a mouthpiece 303 that inputs voice transmitted to another terminal device, An electro-optical device 10 that displays an image is included. In addition to the mobile phone as described above, the electronic apparatus in which the electro-optical device according to the present invention can be used includes a notebook computer, a liquid crystal television, a viewfinder type (or monitor direct view type) video recorder, a car Examples include navigation devices, pagers, electronic notebooks, calculators, word processors, workstations, videophones, POS terminals, and devices equipped with touch panels.

(7) Modifications The first to fifth embodiments described above may be implemented by appropriately combining the embodiments, for example, by combining the contents of the second embodiment and the contents of the third embodiment. .
Moreover, the following modifications are possible in each embodiment.
In the first to fifth embodiments, the reference current Iref and the color-specific reference currents Iref-R, Iref-G, Iref
The β ratio of the transistor for adjusting -B is not limited to that illustrated in the embodiment. For example, when the reference current Iref is adjusted to the maximum 131 level with the 100 level as the lower limit, β1: β2: β3: β4: β5: β6 = 100: 1: 2: 4: 8: 16 may be set. For example, when adjusting the reference current Iref-R of R to 10 levels with the 10th level as a lower limit, the β ratio of the transistors 144R-1 and 144R-2.144R-3 may be set to 10: 1: 2. .

In the first to fifth embodiments, the DACRGB 122 and the DAC 123R1, 12
The current output type DA converter such as 3G1, 123B1 to 123Rn, 123Gn, 123Bn has been described as an example. However, the present invention is not limited to this, and the present invention is not limited to the voltage output type DA converter.
It is also possible to apply to a converter. For example, DAC123R1, 123G1, 123
When B1 to 123Rn, 123Gn, 123Bn are voltage output type DA converters,
These DA converters output a voltage to be applied to each organic EL element.
In the first to fifth embodiments, the reference voltage Vref may be a constant value, or a reference voltage Vref that varies with temperature may be used to compensate for the temperature characteristics of the IC.
Specifically, the reference voltage Vref is increased as the temperature increases, and the reference voltage Vref is increased as the temperature decreases.
Make it smaller. In the first to fifth embodiments, the current value is measured using an external measurement test circuit. For example, a current measurement circuit is provided in the IC, and the current value is measured by the IC itself. The measurement result may be A / D converted and output to an external test circuit. In the first to fifth embodiments, each DACDAC 123R1, 123G1,
123B1 to 123Rn, 123Gn, and 123Bn are configured to include the diode-connected transistor 170. However, the present invention is not limited to this, and three diode-connected transistors corresponding to R, G, and B colors are connected to the output terminal T4 of the DACRGB 122. , T5, T6, and the voltage output from these transistors is applied to each DACDAC 123R1, 123G.
1, 123B1 to 123Rn, 123Gn, 123Bn may be input as a gate voltage.

Further, the current mirror circuit described in the third embodiment is not limited to the simple current mirror circuit illustrated in FIG. 7, and does not depend on, for example, the drain-source voltage Vds of a cascode type, Wilson type, or wide amplitude type transistor. A current mirror circuit may be used.
In addition, an electro-optical device using an organic EL element that is currently widely used uses organic materials that emit light in three colors of R, G, and B. However, the present invention is not necessarily limited to such R, G, and B. It does not mean that it can be any color. In the first to fifth embodiments, the example in which the data line driving circuit is provided only on one end side of the data line has been described. However, the data line driving circuit may be provided on both end sides of the data line. Good.

In the first to fifth embodiments, the transistors 131 to 13 of the reference current generation circuit.
The fuses f1 to f6 are provided on the path of the current flowing through the transistor 6, respectively, and the magnitude of the reference current is adjusted according to the drive capability ratio of the transistors 131 to 136. However, a fuse is not provided so as to correspond to all of the transistors 131 to 136 as described above. For example, a transistor 136 (referred to as a main transistor) having the largest driving capability ratio (β ratio) among the transistors 131 to 136 is The corresponding fuse f6 is not provided, and the other transistors 131 to 135 (referred to as adjustment transistors) have a corresponding fuse f1.
~ F5 may be provided. In this way, the value of the reference current Iref can be adjusted according to the cutting / non-cutting of the fuses corresponding to the adjustment transistors 131 to 135 with the magnitude of the current flowing through the main transistor 136 as the lower limit. Even in this case, it is not necessary to cut these fuses when the reference current Iref already matches the target value in a state where none of the fuses are cut.

1 is a plan view illustrating a configuration of an electro-optical device according to a first embodiment of the invention. FIG. 3 is a block diagram illustrating a configuration of a data line driving circuit of the electro-optical device. It is a circuit diagram which shows the reference current generation circuit which comprises the data line drive circuit. It is a circuit diagram which shows DACRGB which comprises the data line drive circuit. It is a circuit diagram which shows DAC which comprises the data line drive circuit. It is a circuit diagram which shows the reference current generation circuit in 2nd Embodiment. It is a circuit diagram which shows the reference current generation circuit in 3rd Embodiment. It is a circuit diagram which shows the reference current generation circuit in 4th Embodiment. FIG. 10 is a plan view illustrating a configuration of an electro-optical device according to a fifth embodiment. It is a perspective view which shows the external appearance of the electronic device which concerns on this invention.

Explanation of symbols

10, 100... Electro-optical device, 12, 12a, 12b... Data line driving circuit, 14.
... Control unit, 121,181,191,201 ... Reference current generation circuit, 122 ... DACR
GB (reference current generation circuit for each color), 123R1, 123B1, 123G1 to 123Rn, 1
23Gn, 123Bn: DAC (D / A conversion circuit), 113: Organic EL element (pixel)
, 182... Threshold voltage compensation circuit, 192... Current mirror circuit, f1 to f6... Fuse, S1 to S6.

Claims (17)

A reference current generation circuit for generating a reference current of a predetermined value;
A color for generating a reference current for each color based on the reference current generated by the reference current generation circuit and the output level of the reference current specified for each of a plurality of colors. Another reference current generation circuit;
Based on the reference current for each color generated by the reference current generation circuit for each color and the gradation data representing the gradation in the pixel of each color, the current to be supplied to each pixel or the voltage to be applied to each pixel is determined. A D / A converter circuit for outputting ,
The reference current generation circuit includes a plurality of transistors and a current flowing through each of the transistors.
A plurality of fuses provided on the flow path, and a current flowing through each of the transistors.
And a path formed to add the current and output as the reference current.
One of the plurality of fuses is blown so that a reference current having a predetermined value is output.
Is formed without cutting any of the plurality of fuses. A reference current generation circuit for generating a reference current of a predetermined value;
The reference current generated by the reference current generation circuit is designated for each of a plurality of colors.
Based on the output level of the reference current, the reference current used as a reference when driving each color pixel is determined.
A reference current generation circuit for each color to be generated for each color;
The reference current for each color generated by the color-specific reference current generation circuit and the pixel for each color.
Current to be supplied to each pixel or to be applied to each pixel,
A D / A converter circuit that outputs a high voltage
With
The reference current generating circuit includes a main transistor, one or a plurality of adjustment transistors, one or a plurality of fuses provided on a path of a current flowing through each of the adjustment transistors, the main transistor, and the adjustment And a path formed so as to output the reference current as a sum of currents flowing through the transistors, and either one of the fuses or the plurality of fuses is output so that a reference current of a predetermined value is output. A semiconductor integrated circuit, wherein the semiconductor integrated circuit is cut or formed without cutting any one or the plurality of fuses. 3. The threshold voltage compensation circuit according to claim 1, wherein the reference current generation circuit includes a threshold voltage compensation circuit that generates and outputs a constant current as the reference current regardless of a threshold voltage value of the transistor. Semiconductor integrated circuit. A reference current generation circuit for generating a reference current of a predetermined value;
D / A conversion for outputting a current to be supplied to each pixel or a voltage to be applied to each pixel based on the reference current generated by the reference current generation circuit and the gradation data representing the gradation in each pixel. With circuit,
The reference current generation circuit is provided on each of a plurality of transistors, a threshold voltage compensation circuit that generates and outputs a constant current regardless of the threshold voltage value of the transistors, and a path of current flowing through each of the transistors. A plurality of fuses, and a path formed so as to output the reference current by adding the currents flowing through the transistors, so that the reference current of a predetermined value is output. A semiconductor integrated circuit, wherein any one of the fuses is cut or none of the plurality of fuses is cut. A reference current generation circuit for generating a reference current of a predetermined value;
D / A conversion for outputting a current to be supplied to each pixel or a voltage to be applied to each pixel based on the reference current generated by the reference current generation circuit and the gradation data representing the gradation in each pixel. With circuit,
The reference current generation circuit includes a main transistor, one or more adjustment transistors, a threshold voltage compensation circuit that generates and outputs a constant current regardless of the threshold voltage value of the transistor, and the one or more adjustments. One or a plurality of fuses provided on a path of current flowing through the transistor for use, and a path formed so as to add the current flowing through the main transistor and the adjustment transistor and output as the reference current And either one of the one or the plurality of fuses is cut or the one or the plurality of fuses are not cut so that a reference current having a predetermined value is output. A semiconductor integrated circuit. The reference current generation circuit includes:
When at least two transistors having different drive capability ratios are provided and an input current input from the input terminal flows into one transistor, a current having a magnitude proportional to the drive capability ratio with respect to the input current in the other transistor Current mirror circuit through which
The semiconductor integrated circuit according to any one of claims 1 to 5 to the input terminal, characterized in that the reference current is the generated is input of the current mirror circuit. The reference current generation circuit, on the path of current which the fuse is provided, a semiconductor integrated circuit according to any one of claims 1 to 6, characterized in that it comprises activatable switch. A reference current generation circuit for generating a reference current of a predetermined value;
D / A conversion for outputting a current to be supplied to each pixel or a voltage to be applied to each pixel based on the reference current generated by the reference current generation circuit and the gradation data representing the gradation in each pixel. With circuit,
The reference current generation circuit adds a plurality of transistors, a plurality of fuses provided on a path of current flowing through each of the transistors, and a current flowing through each of the transistors, and outputs the sum as a reference current When the reference current input from the input terminal flows into one transistor, the drive capability with respect to the reference current is detected in the other transistor. A current mirror circuit through which a current proportional to the ratio flows, and either one of the plurality of fuses is cut or all of the plurality of fuses are output so that a reference current of a predetermined value is output. Is formed without being cut, a semiconductor integrated circuit. A reference current generation circuit for generating a reference current of a predetermined value;
D / A conversion for outputting a current to be supplied to each pixel or a voltage to be applied to each pixel based on the reference current generated by the reference current generation circuit and the gradation data representing the gradation in each pixel. With circuit,
The reference current generation circuit includes a main transistor, one or more adjustment transistors, one or more fuses provided on a path of a current flowing through the one or more adjustment transistors, the main transistor, A path formed to add the current flowing through the adjustment transistor and output as the reference current, and at least two transistors having different drive capability ratios, and the reference current input from the input terminal is one of the transistors And the current mirror circuit in which the current having a magnitude proportional to the drive capability ratio with respect to the reference current flows in the other transistor, and the reference current having the predetermined value is output. Either one of the multiple fuses is cut or none of the one or more fuses is cut The semiconductor integrated circuit, characterized by being made. A reference current generation circuit for generating a reference current of a predetermined value;
D / A conversion for outputting a current to be supplied to each pixel or a voltage to be applied to each pixel based on the reference current generated by the reference current generation circuit and the gradation data representing the gradation in each pixel. With circuit,
The reference current generation circuit adds a plurality of transistors, a plurality of fuses and switches that can be turned on and off respectively on a path of a current flowing through each of the transistors, and a current flowing through each of the transistors to add the reference One of the plurality of fuses is cut or none of the plurality of fuses is cut so that a reference current having a predetermined value is output. A semiconductor integrated circuit comprising A reference current generation circuit for generating a reference current of a predetermined value;
D / A conversion for outputting a current to be supplied to each pixel or a voltage to be applied to each pixel based on the reference current generated by the reference current generation circuit and the gradation data representing the gradation in each pixel. With circuit,
The reference current generation circuit includes a main transistor, one or more adjustment transistors, one or more fuses provided on a path of a current flowing through the one or more adjustment transistors, the main transistor, A path formed to add the current flowing through the adjustment transistor and output as the reference current, and either one of the fuses or the plurality of fuses is cut so that a reference current of a predetermined value is output Or a semiconductor integrated circuit, wherein none of the one or the plurality of fuses is cut. A plurality of pixels provided at each intersection of the data line and the scanning line;
Is constituted by a semiconductor integrated circuit according to any one of claims 1 to 11, wherein the data lines through the data line driving circuit for supplying a voltage to be applied to the current or the pixels to be supplied to the pixels in each pixel When,
An electro-optical device comprising: a scanning line driving circuit that supplies a scanning line signal to the scanning line. 13. The electro-optical device according to claim 12 , wherein the data line driving circuit is constituted by one semiconductor integrated circuit. 13. The electro-optical device according to claim 12 , wherein the data line driving circuit includes a plurality of the semiconductor integrated circuits. 15. An electronic apparatus comprising the electro-optical device according to claim 12 as a display device. Generating a current by a reference current generating circuit having a plurality of transistors;
The process of measuring the value of the generated current as the value of the current proportional to the drive capability ratio of the transistor,
One of a plurality of fuses provided on a path of a current flowing through the plurality of transistors so that a value of a current generated by the reference current generation circuit becomes a predetermined value based on a measured current value A method for manufacturing a semiconductor integrated circuit, comprising: Generating a current by a reference current generating circuit having a plurality of transistors;
The process of measuring the value of the generated current;
Based on the measured current value, any one of the plurality of switches provided on the path of the current flowing through the plurality of transistors so that the value of the current generated by the reference current generation circuit becomes a predetermined value. The process of turning on or off,
A plurality of fuses provided on a path of a current flowing through the plurality of transistors based on a measurement result of a value of a current generated by the reference current generation circuit in a state where any of the switches is turned on / off A process for cutting any one of the above, and a method for manufacturing a semiconductor integrated circuit.

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