JPS6029035A - A/d converter - Google Patents

Abstract

PURPOSE:To enhance resolution and to decrease in the necessary numbers of elements of an A/D converter and power consumption by outputting in a form of more than (N+1) bits when a selecting circuit selects an analog signal. CONSTITUTION:The input signal Vi from the input terminal 1 is inputted into the differential amplifier 35, which outputs the different output Vsub of reference voltage from the input terminal 50. The signal Vi is added to the comparator 52 including the differential amplifier 36, and where Vi>Vref, output Vcom is outputted. When this Vcom is outputted, the output Vcom11 is inputted into the analog switch 40 and output arithmetic circuit 44. Where Vi>Vref, the output of the comparator 52 is not inversed and the direct signal Vi is inputted into the A/D converter. The output 114 of the device 4 is added to the circuit 44, and an output is outputted in a form of more than (N+1) bits on the output terminals P1-PN+1, thereby decreasing in the necessary numbers of elements.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides an A
The present invention relates to a /D conversion device fIt (also referred to as an A/D conversion circuit or #'inΦ converter).

FIG. 1 is a block diagram of a conventional A/D conversion device. This A/D converter includes N-bit A/D converters 4 and 5, and outputs a digital signal with N+1 bits.

This is a device devised to obtain a resolution of N+1 bits using two N-bit A/D converters. This A/D converter uses resistors 2 and 3 to divide or divide the analog signal 101 input from the input terminal 1, and converts the analog signal 101 input from the input terminal 1 into the first N-bit A/D converter [4 and the second ON pin]. A/
It is added to the D conversion device 5. 6 is an adder circuit for adding the outputs 104 and 105 of the A/D converters 4 and 5; P, . . .
PN+1 is an output terminal that outputs bit 1 to pit N+1 of the adder circuit 6.

FIG. 2 is a diagram showing the relationship between the analog quantity A and the mass quantization tQ obtained by quantizing the analog quantity A. The horizontal axis represents the analog sweetness A, and the vertical axis represents the quantization quantity Q. Analog amount A
The maximum allowable value of is Amax.

If the quantization step is ΔA, the required number of quantization steps is A a x/ΔA. Now, assuming that there is an A/D converter whose number of chill steps is 2N, 2N<Am
If aX/ΔA〈2N+1, then A/ with the number of steps 2N
By using two D conversion devices as shown in Figure 1,
The analog quantity A can be converted into a digital quantity Q. 1st
In the device shown, the adder circuit 6 has an N-bit input 104,
By adding 105 and outputting the logical interest of both inputs in N+1 bits, the resolution is twice as high as that of the German A/D converter of 4.5.

However, the conventional device shown in FIG.
Errors may occur due to the mismatch in characteristics between #4 and the second A/D converter 5, and since two A/D converters are used, the number of required elements is large, resulting in high power consumption. .

SUMMARY OF THE INVENTION An object of the present invention is to provide an A/D conversion device that has high resolution, is free from errors, and requires a small number of elements.

The A/D conversion device according to the present invention includes a subtraction circuit that generates a difference between an analog signal and a reference analog value, and selects the output of the subtraction circuit when the analog signal is larger than the reference analog value, and a circuit that selects the analog signal when is smaller than the reference analog value;
a circuit that converts the output of the selection circuit into an N-bit digital signal (N is an integer of 2 or more); and a predetermined digital value corresponding to the reference analog value when the selection circuit selects the output of the subtraction circuit; and an output of the conversion circuit, and when the selection circuit selects the l analog signal, outputs the output of the conversion circuit in the form of a bit number of N11 bits or more. Sleep.

The present invention will be described in detail below with reference to the drawings.

FIG. 3 is a block diagram showing one embodiment of the present invention. When input signal Vi is received from input terminal l, resistors 30 and 32
．． 34 and a differential amplifier 35.
The i-power Vsub is the difference between Vref input from the input terminal 50 of the reference voltage Vref and Vi. Also, the output .COm of the comparator 52 consisting of the resistors 31 and 33 and the differential amplifier 36 is output when the relationship Vi>Vref, and is input to the analog switch 40 and the output calculation circuit 44. Here, the reference voltage ref is set to a voltage obtained by multiplying the voltage value of one step of the N-bit A/D converter 4 by the number of steps, that is, the maximum allowable input value. Therefore, the maximum allowable value of the input signal Vi is the A/D
This is twice the maximum allowable input value of the conversion device 4.

When the input signal Vi is smaller than Vref (Vi(V
ref)Fi, the output of the comparator 52 is not inverted and the analog switch 40 is not activated. At this time, the input end 39 of the A/D converter 4 is connected to the terminal 38, and the input signal V
i is directly input to the A/D converter 4. Since the output of the converter 52 is not inverted, the output calculation circuit 44 outputs the output 114 of the A/D converter 4 without performing any calculation.
is output directly to the data output terminals P1 to 1)H, and the data output terminal PN41 is set to 0, so that the data is in N+1 bit format.

Vi) In the case of Vref, the output of the comparator 52 is inverted, and this output Vcom is given to the analog switch 40 and the output calculation circuit 44. analog switch 4
0 receives the output Vcom of the comparator 52, and the A/D
The converter 40 input 39 is connected to the subtractor output 37. The output calculation circuit 44 that receives maf(, Vcom,
N bit full scale (all N pits create data of %111, and this N bit full scale data and A/D
and the output 114 of the conversion device 4, and the result is sent to the output terminal P1.
~PN, and the overflow is output from the output terminal PN+IK, making it an N+1-bit output signal.

As explained in detail so far, N+1 in this embodiment
Since the bit A/D converter M is damaged by one N-bit A/D converter 4, by setting the refO value as the input value of the A/D converter 4 at full scale, There will be no bit loss. It has already been explained that in the past, two N-bit width converters were used, and each error was calculated as ξ0. ξ, due to error propagation, the error of the conventional A/D converter is ξ1
10ξ. On the other hand, in this embodiment, even for an input signal Vi larger than Vref, since there is only one N pip) A/D converter, only the error ξ of the N pip) A/1) converting device is N -1-1 This is an error of the A/D converter, and the conversion error that occurs when performing A/D conversion is significantly reduced. Not only that, but also N pin) A, /
The fact that only one D converter is sufficient has the effect of reducing the chip area or mounting area by about half, reducing the weight consumption, and significantly lowering manufacturing costs. As described above, according to the present invention, it is possible to provide an A/D conversion device that has high resolution, is less prone to errors, and requires a small number of elements.

[Brief explanation of the drawing]

Figure 1 is a block diagram of a conventional A/D converter (N+1 bits), Figure 2 is a diagram showing the relationship between an analog quantity and a quantized quantity obtained by tightening and chilling this analog quantity, and Figure 3 is a diagram of the present invention. FIG. 2 is a block diagram of one embodiment. ■--Input terminal, 35.36--Differential amplifier, 44--Output calculation circuit, 50...
・・Reference voltage input terminal, P, ~PN+ 1・・
...output terminal.

Claims (1)

[Claims] a subtraction circuit that generates a difference between an analog signal and a reference analog value; when the analog signal is thicker than the reference analog value, the output of the subtraction circuit is selected; and when the analog signal is smaller than the reference analog nM, the output of the subtraction circuit is selected; a circuit for selecting the analog signal; a circuit for converting the output of the selection circuit into a digital signal of N pits (N is an integer of 2 or more); is a predetermined digital value (
and a circuit that outputs the sum of the analog signal and the output of the conversion circuit, and outputs the output of the conversion circuit in a bit format of N+1 bits or more when the previous one selection circuit selects the analog °' signal. An A/D conversion device.