JPH0797747B2 - Pulse width modulator - Google Patents

Description

TECHNICAL FIELD The present invention relates to pulse width modulation (hereinafter referred to as PWM) used for digital-analog conversion of audio signals and the like.
Abbreviated. ) Regarding the device.

Conventional technology In recent years, 16-bit ...
A method of performing digital-analog conversion after converting to a 1-bit digital signal using a clock having a frequency higher than the sampling frequency of a digital audio signal has been widely used. This method has the advantage that the order of the analog low-pass filter inserted after the digital-analog conversion can be lowered and a high S / N can be obtained with a small circuit scale. This 1-bit digital
PWM is used as an example of an analog conversion method.
Therefore, the PWM will be explained first with reference to the drawings. Fourth
The figure is a waveform diagram showing an example of a PWM signal. As shown in Fig. 4, the PWM signal is a signal in which pulses of varying time width appear periodically (cycle T), and it is a type of 1-bit digital signal that has a "H" state and a "L" state. is there. The PWM signal can be converted into an analog signal by passing through a low pass filter. When passing the PWM signal through the low pass filter, the output signal waveform of the low pass filter increases when the PWM signal is "H", and the output signal of the low pass filter when the PWM signal is "L" The waveform decreases. That is, the increase / decrease of the output signal waveform of the low pass filter converted into analog is determined by the time ratio of the “H” state and the “L” state of the PWM signal. Therefore, when the time ratio of the "H" state and the "L" state is the same (50%: 50%), the increase and decrease of the output signal waveform of the low pass filter are canceled out, and one cycle T
There is no increase or decrease in.

Next, a conventional technique for a PWM device that converts a PCM signal into a PWM signal will be described with reference to the drawings.

FIG. 3 is a block diagram showing an example of a conventional PWM device. A PCM signal 107 having a sampling frequency F _s1 or 48 kHz and quantized m bits or 16 bits input to the input terminal 101 is input to a digital filter 102 as a sampling frequency F _s2 or 768 kHz and a quantized n bit or 4 bit PCM signal 109. Is converted to. Here, the digital filter 102 is for performing 16 times oversampling of the input PCM signal, and outputs data that determines the pulse width of the PWM. That is, 4-bit pulse width information is output for each 1/768 kHz cycle. This digital filter 10
2 is specifically realized by the 11R filter in FIG.
In this digital filter 102, the higher 4 bits of the signal of the calculation result are output as a 4 bit PCM signal 109, and the lower bits are fed back as an error signal. Due to the 11R configuration, an overflow may occur in the digital filter 102 depending on the input signal. On the other hand, the overflow detector 103 detects the overflow generated in the digital filter 102 and outputs the overflow detection signal 110 to the limiter 104. The sampling frequency F _s2 output from the digital filter 102, that is, 76
The PCM signal 109 limiter 104 of 8 kHz, quantized n bits, that is, 4 bits is controlled by the overflow detection signal 110, and when an overflow does not occur, a 4-bit PC
When the M signal 109 is output as it is, if the overflow occurs, the maximum value of the 4-bit code, that is, 1111 (binary number) is output if the overflow is the + side, and if the overflow is the minus side, the minimum value of the 4-bit code, that is, 0000 (binary number) To do.
The output signal 111 of the limiter 104 is the same as the digital filter output signal 109 at the sampling frequency F _s2, that is, 768 kHz,
It is a quantized n-bit or 4-bit PCM signal. The output signal 111 of the limiter 104 is input to the modulator 105,
It is processed with a clock of 2.288MHz. One pulse period T = 1 /
During 768 kHz, it is converted into a PWM signal 112 whose time width changes with T / 2 ⁿ = 1 / 12.288 MHz accuracy and is output to the output terminal 106.

Problems to be Solved by the Invention However, during the period T = 1/768 kHz, T / 2 ⁿ = 1 / 12.288
Varying the pulse time width in MHz precision, total 17 kinds from 0 units to 16 units, i.e. despite the possible pulse width representation of ways 2 ⁿ +1, P is a conventional PWM apparatus described above
Since the input of the modulator 105 which outputs the WM signal is a 4-bit PCM signal, there is a problem that only 16 kinds of pulse width expressions, that is, 2 ⁿ kinds, can be expressed.

FIG. 5 is an example of a waveform diagram showing one cycle of the PWM signal. As can be seen from FIG. 5, the time period of the "H" state of the PWM signal is an integral multiple of T / ^{2n when} the period is T. Therefore, from the time when there is no "H" state (zero time width of T / 2 ⁿ ) to the time when all are in the "H" state (time width of 2 ⁿ times T / 2 ⁿ ), 2 ⁿ +
One pulse width representation is possible during T.

However, in the PWM device described in the conventional example, since the input of the modulator 105 outputting the PWM signal is an n-bit PCM signal, only 2 ⁿ kinds of pulse width can be expressed, and when there is no "H" state, Alternatively, either one of the cases where all of them are in the “H” state is not expressed. For this reason, when the PWM device described in the conventional example is used for digital-analog conversion and the PWM signal is input to the low-pass filter, the maximum value of the increase amount and the maximum value of the decrease amount that can be expressed during one cycle T. However, when the analog signal amplitude of the low-pass filter output fluctuates greatly (when the absolute value of the slope is large), distortion occurs and overload noise occurs. Had.

The present invention solves the above-mentioned conventional problems,
⁽ EN) A high-performance PWM device capable of expressing a pulse width of 2 ⁿ +1 ways by changing the time width with a precision of T / 2 ⁿ during a period T.

In order to solve the above-mentioned problems, the PWM device of the present invention controls a quantized n-bit PCM signal, which is a digital filter output, by an overflow detection signal of an overflow detector output, and when an overflow occurs, Converts to a value that represents the upper or lower limit, outputs a + 1-bit PCM signal, and outputs 2 ⁿ +1
It uses a limiter that enables exact numerical representation.

Action The present invention produces the following action by using the limiter described above.

By outputting n + 1 bit PCM signal to the limiter and enabling 2 ⁿ +1 ways of numerical expression, the PCM signal is PWM
The output of the modulator converting into a signal, T / 2 ⁿ during the period T
It is possible to express 2 ⁿ +1 pulse widths whose time width changes with accuracy and become a high-performance PWM device.

Embodiment Hereinafter, a PWM device according to an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a PWM device according to an embodiment of the present invention. Since the apparatus of this embodiment shown in FIG. 1 has basically the same configuration as the conventional apparatus shown in FIG. 3, the same components are designated by the same reference numerals and detailed description thereof is omitted. To do.

Sampling frequency F that is the output of digital filter 102
_s2 or 768 kHz, quantized n bits or 4 bits
The PCM signal 109 is input to the +1 bit limiter 204. +
The 1-bit limiter 204 is controlled by the overflow detection signal 110 which is the output of the overflow detector 103,
Quantization of input when overflow does not occur 4
When the overflow occurs, the 5-bit PCM signal is output by adding the upper 1 bit with the content of zero to the bit PCM signal, and if the overflow occurs, the 5-bit PCM signal becomes 10000 (binary number), and if the overflow occurs, 00000.
Output a 5-bit PCM signal (binary). A concrete block diagram of the +1 bit limiter 204 is shown in FIG.
In FIG. 2, reference numeral 306 denotes a quantizing bit extender that adds 1 bit of 0 to the higher order to a 4-bit PCM signal which is an input signal to generate 5 bits, and 304 is an upper limit that outputs a value of 10000 in binary. Value PCM data, 305 is the lower limit PCM data for outputting a value of 00000 in binary. The + 1-bit limiter 204 normally selects and outputs the quantized bit extender, but when the + side overflow detection signal of the digital filter 102 output is 1, the upper limit value PCM data 304 is selected and output. When the minus overflow detection signal of the digital filter 102 output is 1, the lower limit value PCM data 305 is selected and output. PCM with sampling frequency 768kHz and quantized 5 bits output from +1 bit limiter 204
The signal 211 is input to the modulator 205. Input P on modulator 205
The CM signal 211 is converted into the PWM signal 212 and output to the output terminal 106.

Here, since the input signal of the modulator 205 is a quantized 5-bit PCM and has 17 different numerical expressions, the PWM signal output from the modulator 205 also has 17 different time widths during one pulse period T. I could have it. This makes it possible to reduce the occurrence of distortion when the amplitude fluctuation of the input digital audio signal is large, and to reduce overload noise as a PWM device. In addition, P that increased the PCM signal by 1 bit
Converting to a CM signal is easy and is a very effective means in terms of device configuration.

In this embodiment, the + 1-bit limiter 204 outputs +
When a side overflow occurs, a 5-bit PCM signal of 10000 (binary number) is output, but if the modulator 205 is operable, a 5-bit PCM signal of 11111 may be output, or an intermediate value between them. You may output the signal which shows. When + side overflow occurs, quantized n-bit PC
A quantized n + 1-bit PCM signal indicating the maximum value of the M signal may be output, and the output PCM signal may be expanded when the-side overflow occurs.

As described above, the PWM device of the present invention can maximize the time width change of the PWM signal by increasing the PCM signal of the limiter output by 1 bit, and reduce the overload noise during PWM demodulation. It is possible to reduce the occurrence of distortion as digital-analog conversion.

[Brief description of drawings]

FIG. 1 is a block diagram of a PWM device in one embodiment of the present invention, FIG. 2 is a block diagram showing an example of the internal configuration of the + 1-bit limiter, and FIG. 3 is a block diagram of a PWM device in a conventional example. FIG. 4 is a waveform diagram showing an example of a PWM signal, FIG. 5 is a waveform diagram showing an example of one cycle of a PWM signal, FIG.
FIG. 1 is a block diagram showing the structure of a digital filter according to an embodiment of the present invention. 101 …… input terminal, 102 …… digital filter, 103 ……
Overflow detector, 104 ... Limiter, 204 ... + 1
Bit limiter, 105/205 …… Modulator, 106 …… Output terminal, 107 …… Sampling frequency F _s1 , m-bit PCM signal, 109 …… Sampling frequency F _s2 , n-bit PCM signal, 110 …… Overflow detection Signal, 111 …… Sampling frequency F _s2 , n-bit PCM signal, 211 …… Sampling frequency F _s2 , n + 1-bit PCM signal, 112 ・ 212 …… PWM
Signal, T ... PWM signal pulse period, 301 ... Quantized n-bit PCM signal input terminal, 302 ... Overflow detection signal input terminal, 303 ... Quantized n + 1-bit PCM signal output terminal, 304 ... Upper limit value PCM Data, 305 ... Lower limit PCM data, 306 ... Quantization bit extender, 401 ... 16-bit PCM
Signal input terminal, 402/403 ... Adder, 404/405 ... Multiplier, 406/407 ... Delay element, 408 ... Inversion element, 409.
410 …… AND element, 411 …… + side overflow detection signal output terminal, 412 …… − side overflow detection signal output terminal, 413 …… PWM signal output terminal.

Claims (1)

[Claims] 1. A PCM signal having a sampling frequency F _s1 and a quantization m bits (m is a natural number) input from an input terminal is a sampling frequency F _s2 and a quantization n bits (n a natural number).
A digital filter for converting into a signal, an overflow detector for detecting an overflow when the digital filter processes and outputting an overflow detection signal, a limiter for limiting the numerical value of the digital filter output, and a pulse width modulation for the limiter output. The limiter is controlled by the overflow detection signal, and when the overflow does not occur in the digital filter, the value indicated by the n-bit PCM signal is not changed.
When the PCM signal is output by expanding the bit to +1 bit and the overflow occurs on the + side, a predetermined n + 1-bit PCM signal larger than the maximum value of the n-bit PCM signal is output and the overflow occurs on the-side. N-bit PC if
A pulse width characterized in that by outputting an n + 1-bit PCM signal corresponding to the minimum value of the M signal, 2 ⁿ +1 ways of numerical expression are performed and the modulator outputs 2 ⁿ +1 ways of pulse width. Modulator