JPH0191515A - Pulse width modulator - Google Patents

Abstract

PURPOSE:To attain high performance by increasing a PCM signal being an output of a limiter by one bit so as to maximize the time width change in the pulse width modulation (PWM) signal. CONSTITUTION:A quantized n-bit PCM signal 109 being an output of a digital filter 102 is controlled by an overflow detection signal 110 being an output of an overflow detector 103. Then an (n+1)-bit PCM signal 211 converted into a value representing the upper or lower limit at the occurrence of overflow is outputted so as to attain the numerical expression in 2<n>+1 ways by a limiter 204 employed in the titled modulator. Thus, the pulse width expression in (2<n>+1) ways whose time width is changed in a period T with accuracy of T/2<n> is attained to attain high performance from the output of the modulator 205 converting the PCM signal into the PWM signal.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to pulse width modulation used in digital-to-analog conversion.
:Hereinafter abbreviated as PWM. ) device.

BACKGROUND OF THE INVENTION In recent years, PWM using pulse time width control has come into use for digital-to-analog conversion.

First, PWM will be explained with reference to the drawings. FIG. 4 is a waveform diagram showing an example of a PWM signal. As shown in Figure 4, the PWM signal is a signal in which pulses with varying time widths appear periodically (period T), and is a type of 1-bit digital signal that has an 'H' state and an L' state. .

The PWM signal can be converted to an analog signal by passing it through a low pass filter. When passing a PWM signal through a low-pass filter, when the PWM signal is in the "H" state, the output signal waveform of the low-pass filter increases, and when the PWM signal is in the "L" state, the output signal waveform of the low-pass filter increases. decreases. In other words, the PWM signal's H" state and "
The increase or decrease of the output signal waveform of the low-pass filter converted to analog is determined by the time ratio of the "L" state. Therefore, the time ratio of the "H" state and the "L" state are the same (s
ob:sob), the increase and decrease in the output signal waveform of the low-pass filter cancel each other out, and the increase and decrease in the -period T disappear.

Next, a conventional technique for a PWM device that converts a PCM signal into a PWM signal will be explained with reference to the drawings.

FIG. 3 is a block diagram showing an example of a conventional PWM device. A quantized m-bit PCM signal 107 with a sampling frequency of 1's+ inputted to the input terminal 101 is inputted to the digital filter 102 and has a sampling frequency of FB.
The signal is converted into a PCM signal 109 of n bits with 21 quantization.

On the other hand, the overflow detector 103 detects the overflow generated in the digital filter 102 and outputs an overflow detection signal 110 to the limiter 104.

A PCM signal 109 of sampling frequency 1's21 and quantized n bits outputted from the digital filter 102 is inputted to the limiter 104. The limiter 104 is controlled by an overflow detection signal 110, and when no overflow occurs, it outputs the input as is, and when an overflow occurs, it outputs the maximum value (upper limit) if it is a positive overflow, or the minimum value (if it is a negative overflow). (lower limit value) is output. The output signal 111 of the limiter 104, like the digital filter output signal 109, is a PCM signal of sampling frequency Fs2 and quantization of n bits. The output signal 111 of this limiter 104 is transmitted to the modulator 105.
is input to the output terminal 10 and is converted into a PWM signal 112 whose time width changes with an accuracy of T/2" during the -pulse period T.
6 is output.

Problems to be Solved by the Invention However, although a pulse whose time width changes with T/2" accuracy during a period can be expressed in 2n+1 pulse widths, the conventional PWM device described above cannot perform PWM. The input of the modulator 105 outputting the signal is n ps) PCM
Since it is a signal, it has the problem that only 2n pulse width expressions are possible.

FIG. 6 is an example of a waveform diagram representing one period of the PWM signal. As can be seen from Figure 6, the period of the PWM signal's "H" state is an integer multiple of T/2". Therefore, if there is no "H" state at all (the time of zero times T/2") Width) to “H” state (2 of T/2
2n+1 pulse width expressions are possible up to 2 times the time width).

However, in the PWM device described in the conventional example, since the input of the modulator 105 that outputs the PWM signal is an n-bit PCM signal, it is possible to express the pulse width in only two ways. If all of them are in the H" state, one of them will not be expressed. Therefore, if the PWM device described in the conventional example is used for digital-to-analog conversion and the PWM signal is input to a low-pass filter, one cycle When the maximum value of the increase and the maximum value of the decrease that can be expressed during T do not match, and the analog signal amplitude of the low-pass filter output fluctuates greatly (when the absolute value of the slope is large), distortion occurs. There was a problem in that this would occur.

The present invention solves the above-mentioned conventional problems,
The time width changes with T/2n precision during period T, and 2n+1
The present invention provides a high-performance PWM device that can express a standard pulse width.

Means for Solving the Problems In order to solve the above-mentioned problems, the PWM device of the present invention controls the quantized n-bit PCM signal, which is the output of the digital filter, by the overflow detection signal of the output of the overflow detector, and detects an overflow. A limiter is used which converts the value into a value representing the upper or lower limit at the time of occurrence and outputs an n-)-1 bit PCM signal, allowing 2n+1 numerical expressions.

Effects The present invention provides the following effects by using the limiter described above.

Let the limiter output the PCM signal of n-1-1 pits 2
It is possible to express numerical values in n+1 ways. Therefore, the PC
The output of the modulator that converts the M signal into a PWM signal enables 2n+1 pulse width expressions in which the time width changes with T/2'' accuracy during the period T, resulting in a high-performance PWM device.

Embodiment Hereinafter, a PWM device according to an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a PWM device in one embodiment of the present invention. The device of this embodiment shown in FIG. 1 basically has the same configuration as the conventional device shown in FIG. 3, so the same components are given the same numbers and detailed explanations will be omitted. do.

The sampling frequency 's2 y quantized n-bit PCM signal 109 which is the output of the digital filter 102 is +1
The signal is input to the pittori ε ivy 204.

+1 bit limiter 204 is overflow detector 10
When no overflow occurs, the input quantized n-bit PCM signal is converted to a quantized n-J-1 bit) PCM signal and output. When an overflow occurs on the + side, a quantized n-1-1 bit PCM signal is output that indicates a value that is 1 larger than the maximum value of the n-bit PCM signal, and when an overflow occurs on the - side, the quantized n-bit PCM signal is output. quantization n corresponding to the value
-4-Output a 1-bit PCM signal. A block diagram is shown in FIG. 2 as an example of a specific internal configuration of the +1 bit limiter 204. +1 Bit limiter 204 outputs sampling frequency f's2+n+1 bit PC
M signal 211 is input to modulator 205. Modulator 20
6 converts the input PCM signal 211 into a PWM signal 212 and outputs it to the output terminal 106.

Here, since the input signal to the modulator 206 is quantized (n-1-1) PCM and has 2n+1 numerical expressions, the PWM signal output from the modulator 205 is also 2n+1 during one pulse period T. I was able to have the same amount of time. Furthermore, it is easy to convert a PCM signal to a PCM signal with one bit added, and is a very effective means for device configuration.

In this embodiment, when an overflow on the + side occurs in the +1 bit riser 204, the quantization n bit) PC
Quantization n-4 indicating a value 1 greater than the maximum value of the M signal
- Although a 1-bit PCM signal was output, the modulator 205
If it is operable, a signal indicating the maximum value of the quantized n+1-bit PGM signal may be output, or a signal indicating an intermediate value thereof may be output. Further, when a + side overflow occurs, a quantized n+1 pcm) PCM signal indicating the maximum value of the quantized n pcm) PCM signal is output, and a - side overflow a- occurs. Sometimes the output PCM signal may be expanded.

Effects of the Invention As described above, the PWM device of the present invention has a limiter output PC.
By increasing the M signal by 1 bit, the time width change of the PWM signal can be maximized, and performance can be improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a PWM device according to an embodiment of the present invention, FIG. 2 is a block diagram showing an example of the internal configuration of the +1 bit limiter, and FIG. 3 is a block diagram of a PWM device in a conventional example. FIG. 4 is a waveform diagram showing an example of a PWM signal, and FIG. 5 is a waveform diagram showing an example of one cycle of the PWM signal. 1o1... Input terminal, 102... Digital filter, 1o3... Overflow detector, 1o4... Sui ivy, 204...
+1 pit limiter, 106/206...Modulator, 106...Output terminal, 107...
Sampling frequency f51. m-pit PCM signal, 1
09... Sampling frequency fs2. n-bit PCM signal, 110... Overflow detection signal, 111... Sampling frequency fs2. n-bit PCM signal, 211...sampling frequency f52. n-1-1 bit PCM signal, 11
2・212...PWM signal, T...P
WM signal pulse period, 301... Quantization n p) PCM signal input terminal, 302... Overflow detection signal input terminal, 303... Quantization n
-1-1 pin) PCM signal output terminal, 304...
・Upper limit value PCM data, 306... Lower limit value PO
M data, 306...Quantization bit extender. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure I / ] '7 Figure 4 = -Cho 11 Row 1111 -, L-7---T-A
Figure 5 J@L

Claims (1)

[Claims] Sampling frequency F_S_1 input from the input terminal
, quantized m-bit PCN signal at sampling frequency F
_S_2, a digital filter that converts the quantized n-bit PCM signal, an overflow detector that detects an overflow of the digital filter output and outputs an overflow detection signal, and an overflow detection signal that converts the digital filter output into the overflow detector output. When an overflow occurs, the sampling frequency F_S_2 and quantization n are controlled by converting to a value representing the upper or lower limit.
A pulse width modulation device comprising a limiter that outputs a +1-bit PCM signal and can express numerical values in 2^n+1 ways, and a modulator that converts the limiter output into a pulse width modulation signal and outputs it to an output terminal.