JPS61287328A - Ad converting circuit - Google Patents

Abstract

PURPOSE:To obtain an inexpensive AD conversion circuit by fluctuating periodicall the entire reference voltage, allowing an output buffer to hold a preceding output signal of a signal conversion circuit and adding an output signal of the signal conversion circuit and the preceding output signal by an adder circuit. CONSTITUTION:The AD conversion circuit 100 has the signal conversion circuit 20, a reference voltage fluctuation circuit 30, a buffer 40 and the adder circuit 50. The signal conversion circuit 20 converts an analog input signal into a digital signal of the number prescribed bits based on the reference voltage. The refrence voltage fluctuation circuit 30 fulctuates the entire reference voltage of the signal conversion circuit 20 at each sampling. The buffer 40 fetches the preceding output signal in the signal conversion circuit 20. The adder circuit 50 adds the output signal of the signal conversion circuit 20 and the output signal of the buffer 40 and outputs a signal having bits more than the number of output bits of the signal conversion circuit 20 by one bit.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is directed to an AD converter that converts an analog signal into a digital signal.
Regarding conversion circuits.

[Prior Art] An AD conversion circuit converts an analog signal into a digital signal, and there have been various types of circuit configurations.

Furthermore, there are various methods of capturing AD-converted image information into a display memory and modifying the captured digital data to create an image. In this case, a low-cost AD conversion circuit is required from the viewpoint of versatility.

By the way, when taking in image information, an AD conversion circuit that outputs 5 bits is desirable in view of actual requirements such as resolution. However, an AD conversion circuit with a 5-bit output is inferior to one with a 4-bit output. There are reports that it is very expensive. The reason why it is expensive is as follows.

FIG. 4 is a circuit diagram showing an example of a conventional AD conversion circuit with 2-bit output. This 2-bit output AD conversion circuit 10 has three analog comparison circuits ACPI.
~ACP3 and four dividing resistors R1 to R4. Then, the output signal of the analog comparison circuit ACPI~3 is encoded by the encoder 11, and this encoded data is latched in the latch lla. 1 FIG. 5 is a chart showing the relationship between input and output of the encoder 11.

Further, the 4-bit output AD conversion circuit is composed of 15 analog comparison circuits and 16 dividing resistors. However, an AD conversion circuit with a 5-bit output requires 31 analog comparison circuits and 32 dividing resistors.

In this way, in the case of an AD conversion circuit with 5-bit output, the number of dividing resistors and analog comparison circuits increases rapidly, and the accuracy of the dividing resistors and the sensitivity of the analog comparison circuit are
Very high demands are required. If the sensitivity becomes high, the mixing and generation of noise will no longer be tolerated, and appropriate countermeasures will need to be taken. Furthermore, since the number of inputs to the encoder becomes 31, the number of gates of the encoder increases. Due to these circumstances, an AD converter with a 5-bit output becomes extremely expensive.

[Object of the Invention] The present invention has been made focusing on the above-mentioned conventional monitoring points, and an object of the present invention is to provide an inexpensive AD conversion circuit.

[J of invention! [Summary] In order to reduce the cost of an AD conversion circuit, the present invention provides a signal conversion circuit that converts an analog signal into a digital signal based on a reference voltage, periodically fluctuates the entire reference voltage, and converts the signal. An output buffer holds the previous output signal of the circuit, and an adder circuit adds the output signal of the signal conversion circuit and the previous output signal.

[Embodiments of the invention] FIG. 1 is a block diagram showing one embodiment of the present invention.

The AD conversion circuit lOO includes a signal conversion circuit 20, a reference 1 pressure variation circuit 30, a buffer 40, and an addition circuit 50.

The signal conversion circuit 20 is a circuit that converts an analog input signal into a digital signal with a predetermined number of bits based on a reference voltage. Details of this signal conversion circuit 20 are shown in FIG.

The reference voltage variation circuit 30 is a circuit that varies the entire reference voltage of the signal conversion circuit 20 every time it is sampled.

The buffer 40 is a buffer that takes in the previous output signal from the signal conversion circuit 20.

The adder circuit 50 is a circuit that adds the output signal of the signal conversion circuit 20 and the output signal of the buffer 40 and outputs a signal with one bit more than the output bit number of the signal conversion circuit 20.

FIG. 2 is a circuit diagram showing the AD conversion circuit 100 more specifically.

The signal conversion circuit 20 converts four signals based on the analog input signal.
It outputs bit digital data, and is similar to a conventional AD conversion circuit with a 4-bit output. Further, in the signal conversion circuit 20, resistors R1 to R16 (resistors each having the same resistance value r) are connected in series in order to obtain 16 voltages with equal intervals based on the reference voltage. Analog comparison circuits ACPI to ACP15 are provided to compare voltages obtained by dividing the reference voltage and analog input signals, and each of these analog comparison circuits ACFI to ACP
Based on the output signal of L5, 4-bit output Do-03
An encoder 21 is provided to generate the . Furthermore, the output data of the encoder 21 is racked by a latch 21a.

Note that the symbol VRI is a variable resistor that adjusts the voltage.

) & quasi-voltage fluctuation circuit 30 includes a resistor RO connected in series with a series circuit of resistors R1 to R16, a variable resistor VR2,
It has a station frequency divider 21. The resistor RO has a value that is approximately half the resistance value r, and the frequency divider 31 roughly divides the frequency of the strobe pulse sent from the image capture device 1 to generate a signal with a pulse width of approximately 50%. This outputs the following.

Note that an image data capture device l is provided to capture image data that is an output signal of the AD conversion circuit 100, and a signal from the image data capture device i is sent to the display memory 2 and the display device 3.

Next, the operation of the above embodiment will be explained.

FIG. 3 shows an example of the operation of the AD conversion circuit 100, and is a chart showing the correspondence between analog input and digital output.

In the above embodiment, it is assumed that the analog input signal shown in FIG. 3 is sent to the AD conversion circuit .

In this case, first, at time L1, a signal of "1" is sent from the suburban frequency divider 31, and therefore, the resistance R
A voltage is generated across O.

Therefore, the signal conversion circuit 2o outputs according to the "scale after converting the reference voltage" shown in FIG. That is, in the above example, "6" is output at time t1. The output of this signal conversion circuit 20 is output from the buffer 40.
be taken into account.

At the next timing (time t2), the rOJ signal is sent from the 1% frequency divider 31, and therefore no voltage is generated across the resistor RO. In this case, the output of the signal conversion circuit 20 becomes "6".

Here, the output value of the signal conversion circuit 2o at time t2 is "
6” and the output value “6” of the buffer 4o are added to the adder circuit 5.
Added by 0. As a result, the output value of the adder circuit 50 becomes "12", and the output of the adder circuit 50 becomes the output of the AD converter circuit 100. Further, after this addition is completed, a strobe pulse is applied from the image data capture device 1 to the buffer 40, and the signal conversion circuit 20 at that time
The output data of is taken into the buffer 4o.

At the next time t3, a signal rlJ is sent from the frequency divider 31, so that a voltage is generated across the resistor RO. Then, the analog input signal at that time is converted using the "scale after converting the reference voltage". Therefore, at this time, the signal conversion circuit 20 outputs "5". Then, the output value "5" of the signal conversion circuit 20 and the output value "6" of the buffer 40 are added by the adding circuit 50, and "11" is output. Then, in response to the strobe pulse, the buffer γ4o takes in the output value "5" of the signal conversion circuit 20 at that time.

In this way, the reference voltage in the signal conversion circuit 2o is changed at each sampling, and the signal conversion circuit 20 converts it into a digital value, and each time the output of the signal conversion circuit 20 and the output of the buffer 40 are The adding circuit 50 adds the signals, and immediately after that, the buffer 40 takes in the output value of the signal converting circuit 20. This series of operations is sequentially repeated.

As a result, as shown in FIG. 3, the output value of the adder circuit 50 becomes data with one bit more than the output value of the signal conversion circuit 20.

Further, the period of reference voltage fluctuation in the reference voltage fluctuation circuit 30 is twice the sample acquisition period in the signal conversion circuit 20.

Note that the signal conversion circuit 20 may have a bit number other than 4-bit output, and in the above embodiment, the AD conversion circuit 100 is connected to the image data importing device 211. However, it can be used for purposes other than capturing image data.

[Effects of the Invention] According to the present invention, an inexpensive AD conversion circuit can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention. FIG. 2 is a blow diagram showing the main parts of the above embodiment more specifically. FIG. 3 is a chart showing the correspondence between analog input and data output in the AD conversion circuit used in the above embodiment. FIG. 4 is a circuit diagram showing an example of a conventional AD conversion circuit. FIG. 5 is a chart showing the relationship between the input and output of the AD conversion circuit in the conventional example. 20... Signal conversion circuit, 30... Reference voltage fluctuation circuit, 40... Buffer. 50...Addition circuit, 100...AD conversion circuit. Figure 3 Figure 4 Figure 5 Procedural amendment 1, Indication of the case 1985 Patent Application No. 128.057 2) Name of the invention AD conversion circuit 3 Name of the person making the amendment Name ASCII Co., Ltd. Representative Gunji Clear section 4, Attorney 5, Date of amendment order, Voluntary amendment 6, Number of inventions increased by amendment 7, Claims column of the specification subject to amendment and Detailed description of invention column 8, Contents of amendment (1) The following sentence is added between lines 15 and 16 of page 10 of the specification. "The present invention also provides a signal conversion means for converting an analog input signal into a digital signal of a predetermined number of bits based on a reference voltage, and a reference voltage for varying the reference voltage of the signal conversion means for each sampling. In this case, the means for adding two successive pieces of output data from the signal converting means may be executed with a delay, or may be executed separately. It may be carried out in a device such as the above. Note that when the 1/2 frequency divider 31 outputs "1", a voltage equal to 1/2 of the voltage across the resistor R1 is generated across the resistor RO. , the value of the resistor VR2 is set. (2) The scope of claims will be amended as shown in the attached sheet. 2) Claims (1) Signal converting means for converting an analog input signal into a digital signal of a predetermined number of bits based on a reference voltage: The reference voltage of the signal converting means is varied every time it is sampled. a reference voltage varying means; a buffer means for capturing and holding the output signal of the signal converting means every time it is sampled; and an adding circuit for adding two consecutive pieces of output data of the signal converting means; An AD conversion circuit characterized in that it outputs a digital signal with one bit more than a predetermined number of bits. (2) The AD conversion circuit according to claim 1, wherein the amount of variation by the reference voltage variation means is approximately half of the minimum detection voltage in the signal conversion means. (3) The AD conversion circuit according to claim 1, wherein the reference voltage variation period in the reference voltage variation means is twice the sample acquisition period in the signal conversion means. There is a special AD circuit.

Claims (3)

[Claims] (1) signal converting means for converting an analog input signal into a digital signal of a predetermined number of bits based on a reference voltage; reference voltage varying means for varying the reference voltage of the signal converting means for each sampling; a buffer means for capturing and holding the output signal of the signal converting means every time it is sampled; and an adding circuit for adding two consecutive pieces of output data of the signal converting means; An AD conversion circuit characterized by outputting a digital signal with many bits. (2) The AD conversion circuit according to claim 1, wherein the amount of variation by the reference voltage variation means is approximately half of the minimum detection voltage in the signal conversion means. (3) In claim 1, the period of reference voltage variation in the reference voltage variation means is:
An AD conversion circuit characterized in that the sampling period is twice as long as the sample acquisition period in the signal conversion means.