JPH01175417A - Traveling wave type ad converter - Google Patents

Abstract

PURPOSE:To eliminate signal attenuation and to obtain delay data with an accurate value by cascading delay lines made of a superconducting material, using comparators which input delay line outputs and data of DA converters, and setting trailing-stage DA converters with output signals of the DA converters. CONSTITUTION:An analog signal inputted from a terminal 6 is compared by a comparator 21 with the reference voltage of the MSB first. When the signal is larger than a reference voltage, 1 is written in a register 41 in synchronism with the signal of a clock generator 5. This data is sent to a trailing-stage DA converter 31, the reference voltage of the MSB is added to the reference voltage of a 2nd bit, and the output is set. The input analog signal, in the other hand, is delayed by a delay line 1 by the clock timing of the clock generator 5. Said operation is repeated to decide the LSB in order. Therefore, there is no signal attenuation on delay lines 11-17 and the output gains of the respective DA converters need not be adjusted, so the constitution of the DA converter 3 may be exactly the same and the accuracy is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a traveling waveform AD converter, and more particularly to a high-speed, high-precision AD converter using a superconducting material for a signal delay line.

Conventional technology A parallel type is excellent as a high-speed AD converter.

In this method, if it is an n-bit AD converter, 2n to 1 comparators are prepared, 1 is applied with the voltage to be compared, and this reference voltage and input voltage are equalized and input to comparison 2. It detects the voltage level. Although this method is fast, it requires a large number of comparators, which increases the number of elements and also increases the power consumption. On the other hand, there is a traveling waveform AD converter that reduces the number of elements and reduces the power consumption.

(For example, Nikkei Elec L-Ronikunu 1977-3-7
pp68).

The AD converter is constructed by cascading comparators in a number corresponding to the number of pins. A DA converter is connected to one input terminal of each stage of comparators. The input analog voltages of each stage are delayed and added by a delay line for the time required for voltage comparison at the previous stage. The first stage comparator compares the reference voltage corresponding to the MSB with the input voltage, and the result is input to the next stage DA converter. Similarly, 2
The comparator in the second stage compares the 2nd pin to the 1st, and the final stage determines the LSB.

Problems to be Solved by the Invention This progressive waveform AD converter can continuously convert input signals into 3 and It does not require a sample/hold circuit, which is difficult to speed up, like the cascade type AD converter.However, the signal attenuation of the delay line is large and error correction is required.This correction requires the DA conversion input to the comparator. It is necessary to adjust the output of the device, but
Accurate adjustment is difficult.

Means for Solving the Problems According to the present invention, a plurality of delay lines made of superconducting material are connected in cascade, and the output of the delay line and data from a plurality of ODA converters are input. This is a traveling waveform converter that is composed of a plurality of comparators and has means for setting the next stage DA converter using the output signal of the two-note DA converter.

According to the present invention, since the delay line of the traveling wave AD converter is made of a superconducting material with no resistance component, there is no signal attenuation caused by the input signal passing through the delay line, and accurate It is possible to obtain delay data of a certain value. This eliminates the need for gain adjustment of the DA converter. Since the timing of the clock can be set digitally, the delay time can be easily set, and a highly accurate and high speed AD converter can be realized.

Embodiment FIG. 1 shows a block diagram of a traveling waveform AD converter of the present invention. 11 to 17 are signal delay lines using superconducting materials, 2
1 to 28 are comparators, 31 to 37 are DA converters, 41
, 48 is a register for converted data, 5 is a clock generator, 6 is an analog voltage input terminal, γ is an 8-bit digital signal output terminal, 8 is a clock input terminal, and 9 is an MSB reference voltage.

Next, the operation will be explained. The analog signal input from the terminal 6 is first compared with the reference voltage of the MSH by the comparator 21. If the voltage is higher than the reference voltage, 1" is written to the register 41 in synchronization with the signal from the clock generator 5. This data is sent to the DA converter 31 in the next stage, and 2bi) 1st reference voltage. The MSB reference voltage is added to the MSB reference voltage to set its output.Meanwhile, the input analog signal is delayed by the delay line 11 by the clock timing of the clock generator 5. The signals are compared by the comparator 22 and a decision is made on the second bit.The result is read into the register 42 in synchronization with the clock.At the same time, the output of the register 41 is also read with a delay of one clock.The output of this register is further It is input to the next stage ODA converter and the reference voltage of the 3rd bit is set.On the other hand, the output of the delay line 11 is input to the comparator 33 for determining the 3rd bit, which is delayed by one clock in the delay line 12. By repeating the above operations, the LSH discrimination is performed sequentially.LSB DA
The converter requires 8 bits. MS in register-48
Digital data with consistent timing from B to LSB-i
Data is obtained.

According to the present invention, there is no signal attenuation in the delay lines 11 to 17, and there is no need to adjust the output gain of each DA converter.
The configuration of the DA converter 3 can be exactly the same, and the accuracy is improved.
Two I can do it. The precision of the DA converter used here is 8 bits, but the resolution is 2 bits for the 1st pin 1st to 12th bits for the MSB, and 8 bits for the LSB. It can be lowered as it becomes Hino 1-.

Furthermore, errors due to differences in delay times can be corrected by adjusting the timing of the clock pulses of the registers. The timing of the clock pulses can be adjusted digitally and can be precisely programmed later.

The delay line of the present invention can also be applied to a type of cascade AD converter that uses double amplifiers instead of comparators and inputs each output to the next stage amplifier. This method uses a two-sample hold between each amplifier stage to increase speed, but instead uses a delay line made of superconducting material. In this case as well, there is no gain attenuation due to the delay line, and a highly accurate cascaded AD converter can be realized.

As can be seen from the effects of the invention, according to the traveling waveform AD converter of the present invention, by using a superconducting element in the delay line, it is possible to easily obtain a high-speed AD converter with a high degree of 11 degrees. This allows the structure to be suitable for semiconductor integrated circuits.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the traveling waveform AD converter of the present invention. 11-17 Delay line, 21-28...Comparator, 31
~37...DA converter, 41~48...Register.

Claims (1)

[Claims] Multiple delay lines made of superconducting materials are connected in cascade,
A process characterized by comprising a plurality of comparators to which the output of the delay line and the output data of the plurality of DA converters are input, and the next stage DA converter is set by the output signal of the DA converter. Waveform AD converter.