JPH04346520A - A/d converter - Google Patents

Abstract

PURPOSE:To obtain an A/D converter where the number of voltage comparators is halved compared with a conventional parallel A/D converter. CONSTITUTION:The polarity of the input voltage is decided by a differential voltage comparator 1, and an input signal converted into only a positive or negative side by a polarity inverted amplifier 2 is converted into the digital data by an A/D converter 3. The polarity of the digital data is controlled by a logic inverting circuit 4 so as to be coincident with the inverted polarity of input secured by the amplifier 2. Under such conditions, the output of the comparator 1 is outputted as the most significant bit. Meanwhile the output of the circuit 4 is outputted as a bit except the most significant one.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an A/D converter for converting analog signals into digital signals.

0002

2. Description of the Related Art FIG. 4 shows the configuration of a conventional parallel A/D converter. In FIG. 4, reference numeral 11 denotes a voltage comparator array, the positive input of which is connected to an input terminal 12, and the negative input connected to a reference resistor array 14 connected to a reference voltage 13. The output of each voltage comparator 11 is an exclusive OR gate (
EXOR) 15, and the output of EXOR 15 is connected to encoder 16.

Next, the operation of the above conventional example will be explained. In FIG. 4, the signal applied to the input terminal 12 is simultaneously input to all the positive inputs of the voltage comparator array 11, and is compared with the comparison voltage generated by the reference resistor array 14. If it is lower than the comparison voltage, the signal is applied to the logic voltage. “0”, if higher, logic voltage “1”
The EXOR 15 calculates the outputs of two adjacent voltage comparators in the voltage comparator array 11 and outputs the exclusive OR to the encoder 16.The encoder 16 outputs E
Binary digital data corresponding to the output of the XOR 15 is output.

[0004] As described above, even in the conventional parallel type A/D converter described above, analog signals can be converted into digital data at high speed by operating the voltage comparators in parallel.

[0005]

However, in the conventional parallel type A/D converter described above, (2N-1) voltage comparators 11 are required, assuming that the desired resolution is N bits. There was a problem in that a large number of voltage comparators and EXORs had to be used to increase the voltage.

The present invention solves these conventional problems, and aims to provide an excellent A/D converter that can halve the number of voltage comparators and EXORs used.

[0007]

[Means for Solving the Problems] In order to achieve the above object, the present invention uses an analog input as a differential input, and a differential voltage comparator and a polarity inverting amplifier are installed in front of a conventional parallel type A/D converter. By providing a logic inversion gate after the A/D converter, the resolution can be increased by 1 bit without doubling the number of voltage comparator arrays as in conventional parallel A/D converters. It is something.

[0008]

[Operation] Therefore, according to the present invention, the most significant bit (MSB) data of digital data to be output after A/D conversion can be obtained from an analog differential input signal by a differential voltage comparator, and other bit data can be obtained by using a differential voltage comparator. can be obtained by controlling the polarity inversion amplifier placed before and the logic inversion gate placed after the parallel type A/D converter for obtaining the lower data using the MSB data, and the same resolution can be obtained. This has the effect that the number of voltage comparators required can be halved compared to a conventional fully parallel A/D converter.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows the structure of an embodiment of the present invention. In FIG. 1, reference numeral 1 denotes a differential voltage comparator that determines the polarity of a differential input signal, and its output is connected to a control terminal of a polarity inverting amplifier 2 and a delay circuit 5. 2 is a polarity inverting amplifier, and the output polarity of the differential input signal is set by the differential voltage comparator 1 to non-inverting operation when the control signal is "H";
It is controlled to perform an inverting operation when the signal is "L", and the output is unbalanced and connected to the A/D converter 3. In this embodiment, a 5-bit A/D converter 3 is used.4 is a logic inverting circuit that can control logic inversion by a control signal, and is connected to the digital output of the A/D converter 3. In this embodiment, when the control signal is "H", it operates non-inverting; ”, a delay circuit 5 is inserted between the differential voltage comparator 1 and the logic inversion circuit 4 in order to synchronize the polarity inversion circuit 2 and the logic inversion circuit 4. It is.

Next, the operation of the above embodiment will be explained with reference to the signal waveform diagram shown in FIG. In the above embodiment, the voltage +V of the differential input signal a as in section A in FIG.
When IN is higher than -VIN, the output b of the differential voltage comparator 1 is "H", and the polarity inverting amplifier 2 becomes a non-inverting state and transmits a non-inverting signal c to the A/D converter 3. . A/
The conversion range of the D converter 3 is set to 1/2 of the full scale, and this non-inverted signal is A/D converted into 5-bit data e using the conversion clock signal d. The obtained data e passes through the logic inversion circuit 4, but since the output f of the differential voltage comparator 1 that has passed through the delay circuit 5 is "H", it is output as is without being inverted, and the output f of the delay circuit 5 are set as MSB and are combined into 6-bit conversion data.

On the other hand, as in section B of FIG. 2, the differential input signal a
When the voltage +VIN is lower than -VIN, the output b of the differential voltage comparator 1 is "L", and the polarity inversion amplifier 2 is in an inversion state and transmits the inversion signal c to the A/D converter 3. do. The A/D converter 3 converts this inverted signal c into a converted clock signal d.
A/D conversion is performed to 5-bit data e. The obtained data passes through the logic inversion circuit 4, but since the output f of the differential voltage comparator 1 that has passed through the delay circuit 5 is "L", it is inverted and output as g, and the delay circuit 5 is inverted. The output f of the differential voltage comparator 1 which has been passed through the differential voltage comparator 1 is taken as the MSB and combined into 6-bit conversion data. Note that the delay circuit 5 is for synchronizing the signal input to the A/D converter 3 and the signal output after conversion.

As described above, according to the above embodiment, since the MSB is generated by one differential voltage comparator 1, the A
The resolution of the /D converter 3 may be 5 bits, and if the A/D converter 3 is configured with parallel A/D converters, the number of voltage comparators will be 32, and 6 bits can be converted into parallel type A/D converters. This has the advantage that the circuit scale can be approximately halved compared to the case where it is configured with D converters. Furthermore, since the input dynamic range of the A/D converter 3 is only equivalent to 5 bits, it is possible to obtain the effect that the input voltage width of the A/D converter 3 can be reduced.

Note that, as shown in FIG. 3, latch circuits 6 may be provided for all output bits to align the timing.

[0014]

Effects of the Invention As is clear from the above embodiments, the present invention is such that the MSB of A/D conversion data can be obtained by one differential voltage comparator, and the lower bits are lower converted by the MSB. This is achieved by appropriately inverting and non-inverting the analog input and digital output of the A/D converter used for the A/D converter, which has the effect of reducing the circuit scale to about half that of the conventional one.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an A/D converter in an embodiment of the present invention.

[Figure 2] Signal waveform diagram of each part in the device

FIG. 3 is a block diagram of an A/D converter in another embodiment of the present invention.

[Figure 4] Block diagram of a conventional parallel A/D converter

[Explanation of symbols]

1 Differential voltage comparator 2 Polarity inversion amplifier 3 A/D converter 4 Logic inversion circuit 5 Delay circuit 6 Latch circuit a Differential input signal b Output of differential voltage comparator 1 c Output of polarity inversion amplifier 2 d Conversion clock signal e Output of A/D converter 3 f Output of delay circuit 5 g Output of logic inversion circuit 4

Claims (1)

[Claims] 1. A differential voltage comparator to which a differential input signal is input; a polarity inversion amplifier to which the differential input signal is input and whose polarity is switched by the output of the voltage comparator; and the polarity inversion amplifier. A to A/D convert the output of
a /D converter, and a logic inversion circuit capable of controlling polarity inversion of the output data of the A/D converter using the output of the differential voltage comparator, and converts the output of the differential voltage comparator into the most significant bit. An A/D converter that outputs data and the output of the logic inversion circuit as data below the most significant bit.