JPH0744105Y2 - AD conversion circuit - Google Patents

Description

[Detailed description of the device]

[Industrial application] This device is an AD that converts an analog signal into a digital signal.
The present invention relates to a converter, and more particularly, to a serial-parallel AD converter circuit that converts an analog signal into a digital signal in two steps of upper and lower levels. [Summary of the Invention] The AD conversion circuit of the present invention first digitizes an analog signal by coarse quantization to obtain a higher conversion code and then digitizes the quantization error of the higher conversion code. The serial-parallel type that obtains the lower conversion code by
In the AD converter, by outputting the logical product of the specific conversion bits of the upper comparator and the lower comparator, it is configured to obtain the overflow signal or the underflow signal. It is a simplification. [Prior Art] An AD converter that converts an analog signal into a digital signal,
Various conversion methods have been proposed, but in general, the amplitude of an analog signal is quantized to be equal to the conversion bit number, and the quantized signal is input to multiple comparators and converted into a digital code. Flash-type (parallel type) AD conversion circuits are often used. In principle, such a parallel AD converter can operate at high speed, but if the number of conversion bits is n, then at least 2 ⁿ
-1 comparator is required, for example 255 comparators are needed to obtain an 8-bit conversion code.
Therefore, in order to obtain a high-resolution digital code, it is required to form tens of thousands of active elements by forming an IC. Therefore, when converting an analog signal into an n-bit digital signal, first, the analog signal is digitized by coarse quantization to obtain an upper a-bit conversion code including MSB, and an error of the upper conversion code, That is, in order to reduce the quantization noise, an AD conversion circuit has been proposed in which the upper quantization range is further subdivided and digitized to obtain a lower b (na) bit conversion code including the LSB. There is. FIG. 6 is a block diagram showing an outline of such a new serial-parallel AD conversion circuit (hereinafter simply referred to as serial-parallel AD conversion circuit), which shows a circuit configuration for converting an analog signal into a 4-bit digital code. Shows. In this figure, R _{1 to} R ₁₆ are reference resistors connected in series to the terminals of the reference potential V _RT −V _RB (0 to 2 V). Also 1,2,3
Indicates an upper comparator, and the comparators C _{U1 to} C _U3 in the upper comparators 1, 2 and 3 are supplied with an analog signal V _in to be converted at one input terminal and the reference resistor R at the other input terminal.
Reference voltage of coarse quantization level divided by _{1 to} R ₁₆ (V ₁ ,
V ₂ and V ₃ ) are input. Also, 4, 5 and 6 are lower comparators, and comparators C _{D1 to} C _D3 in this lower comparator
Similarly, the analog signal V _in is supplied to one input terminal, and the reference voltage finely divided by the reference resistors R _{1 to} R ₁₆ is supplied to the other input terminal via the switches S _{1 to} S _12. There is. Then, the upper and lower comparators 1 to 1
Reference numeral ₆ outputs signals from the outputs of the comparators C _U and C _D through complementary output amplifiers CA and AND gates A _{1 to} A ₄ and A _{5 to} A ₈ , respectively. The part of E ₁ surrounded by the one-dot chain line is the upper comparator (1,
2,3) encode the binary signal output from, for example, 2-bit binary code (or 2's complement code)
E ₂ is a second encoder for converting the binary signal output from the lower comparators C _{D1 to} C _D2 into a 2-bit binary code. When the "1" level signal is output from the high-order comparator 1, that is, when the "1" level signal is output from the AND gate A ₁ , the switches S _{1 to} S ₃ are controlled to be ON, and the AND gate from a ₂ "1" when the level of the signal is the output switch S ₄ to S ₆ are turned on, or less, the switch S ₇ to S ₉ and S ₁₀ by similarly aND gates a _3, and the output of the a ₄
~ S ₁₂ is controlled to be turned on. In such a serial-parallel AD conversion circuit, as shown in FIG. 7, for example, the analog signal V _in is sampled at the rising point of the sampling pulse P _S , and the sampling voltage
When V _S is supplied, the first encoder E ₁
It operates at the falling time T _{H of} CLK (point delayed by τ _A ), converts the binary signal output of the upper comparators 1 to 3 into the upper 2 bit code signals D ₁ and D ₂ , and outputs the same sampling signal. The value of the voltage V _S is set to the rising point T _L (τ _{B of the} clock signal CLK
It is driven so as to be converted into lower order code signals D ₃ and D ₄ by a second encoder E ₂ which operates at a delayed point). That is, first, the reference voltage obtained by dividing the reference voltage V _{RT to} V _RB.
V ₁ , V ₂ , V ₃ and the sampling voltage V _S are compared by the comparators C _{U1 to} C _U3 in the upper comparator, for example, V ₃ <V _S <
If it is V ₂ , the output of the comparator C _U3 becomes high potential (H), and C
_U1 and C _U2 are at low potential (L) level. Then, only the output of the AND gate A ₃ becomes “1”, and the other AND gates A ₁ , A ₂ and A ₄ show “0” value. As a result, the first encoder E ₁ outputs [01] as the conversion code of the upper 2 bits. Next, a control signal is output from the AND gate A ₃ while the conversion code of the upper 2 bits is latched, and the switches S _{7 to} S ₉ are turned on. Then, the sampled analog signal at the level of V ₃ <V _S <V ₂ is further divided into reference signals V _23-1 , V _23-2 , V _23-3 by the resistors R _{9 to} R ₁₂ . And the comparators C _{D1 to} C _D3 in the lower comparator, for example, V _23-1
When> V _S > V _23-2 , the second encoder E ₂ outputs the conversion code [10] of the lower 2 bits. As a result, the 4-bit conversion code [0110] of the analog signal V _IN is output from the first and second encoders E ₁ and E ₂ . Also, in this AD conversion circuit, a signal indicating overflow or underflow when the level of the analog signal V _in , which is the input signal to be converted, is outside the dynamic range of the AD conversion circuit (outside the code conversion possible level region). _Are provided, an AND gate A _OV to which all outputs of the data signals D ₁ , D ₂ , D ₃ , and D ₄ are input and an AND gate A _{UN of} negative logic are provided. That is, by passing the outputs of D _{1 to} D ₄ through AND gates of positive logic and negative logic, when the converted data signal is [1111], that is, when the sampling signal is V _S , V _S > V _RT When the overflow signal is output and the converted data signal becomes [0000], that is, V _S <
When V _RB, an underflow signal is output. Strictly speaking, the output of the overflow signal or the underflow signal at [1111] or [0000] means that the analog signal V _in may be within the dynamic range (V _RT > V _S > V _R1 and V _RB
<V _S <V _R15 , that is, when the code obtained by converting the analog signal V _IN is at a level that actually becomes [1111] or [0000]) In practice, this level of error may be ignored. Many. [Problems to be Solved by the Invention] This serial-parallel AD conversion circuit outputs a conversion code by dividing it into upper 2 bits and lower 2 bits and outputs the converted code. Can be reduced to 6, for example, when performing 8-bit AD conversion,
The parallel type AD converter requires 255 comparators, but this method has the advantage that (2 ⁴ -1) × 2 = 30 can be obtained by setting the upper and lower bits to 4 bits each. . However, since the conversion code is performed in two steps, the problem described below occurs especially when the sampling frequency is increased. When an analog signal is sampled at a fast cycle, a constant sampling voltage V _S is generally obtained immediately from the sampling time t _{0 due} to the responsivity of the sampling circuit, as shown in FIGS. 8 (a) and 8 (b). In some cases, overshoot may occur or the settling time may become long in the initial stage. Further, the influence (kickback) of the clock signal that drives the AD conversion circuit also causes the variation of the sampling voltage V _S. Then, the sampling voltage at the time T _{H at} which the higher conversion code is output is different from the sampling voltage at the time T _L at which the lower conversion code is output. In this case, as described in the 4-bit AD conversion circuit described above, even when the analog signal V _IN is in the middle of the quantization level of the upper 2 bits, the vicinity of this quantization level, for example, the reference voltage V There is a problem if the levels are very close to ₁ , V ₂ , and V ₃ . For example, when the true value of the conversion code of the analog signal is [0111], if an error of 1 LSB occurs at the higher conversion time T _H , the upper 2 bits become [10], and the conversion code of [10] By selecting the lower comparator, [10
00]. Therefore, as described above, when the settling characteristic of the sampling circuit is bad, in the case of the above code, the conversion code of the upper 2 bits converted at a relatively early timing is likely to change from [01] to [10]. There is a problem that the conversion linearity near the upper quantization level is poor. Further, in such an AD conversion circuit, there is a problem that the circuit for generating the overflow signal and the underflow signal becomes complicated. That is, since the overflow signal and the underflow signal generate signals by all the logical products of the code-converted bit data, the AND gate A
_OV and A _UN require AND gates with the same number of inputs as the number of conversion bits. For example, the circuit shown in FIG. 6 described above has a 4-bit output, and thus requires a 4-input AND gate, and a circuit having a large number of conversion bits requires a multi-input AND gate. (10 bits → 10 inputs AND gate, n bits → n inputs AND gate) Therefore, as the number of conversion bits increases, AND gate
A _OV and A _UN have to be complicated, which is very unfavorable in terms of circuit configuration. [Means for Solving Problems] The present invention has been made for the purpose of solving such problems, and it includes switching blocks arranged in a matrix and arranged in the row direction of the switching blocks. The analog signal is first digitized by the upper conversion bits by the upper comparator and the first encoder, and then the switching blocks arranged in the matrix and the lower comparators arranged in the column direction of the switching block. , And a second encoder to form a serial-parallel AD conversion circuit that digitizes the lower conversion bits, and in the present invention, the overflow signal (or underflow signal) is further converted to a specific bit 1 ( Or 0) and the upper comparator output Specific code converted in the lower encoder 1 (or 0)
Is obtained by taking the logical product of the outputs of the lower comparator. [Operation] By generating the overflow signal and the underflow signal by the logical product of the signals taken out from the specific bit outputs of the upper and lower comparators, the overflow signal and the underflow can be generated with a simple circuit configuration regardless of the conversion bit number. You can get a signal. [Embodiment] FIG. 1 is a circuit diagram showing an embodiment of a serial-parallel AD conversion circuit of the present invention, showing a circuit configuration for converting an analog signal V _in into a 4-bit digital code. In this figure, 11 to 17, 21 to 27, 31 to 37, and 41 to 47 show switching blocks arranged in a matrix, and in this embodiment, each switching block is 4 rows-7.
It is referred to as the row matrix circuit 10. Each switching block is equipped with transistors Q ₁ , Q ₂ and Q ₃ that are configured as a differential amplifier. Except for a part, one transistor Q ₁ has a reference voltage V _RT −V _RB
Is supplied with a reference voltage divided by reference resistors R _{1 to} R ₁₆ , and an analog signal V _in to be converted into a digital code is supplied to the other transistor Q ₂ side. And
The common emitters are commonly connected to each current source I via a transistor Q ₃ which is switched by a control signal described later. Further, the power source V _DD is supplied to the collectors of the transistors Q ₁ and Q ₂ via the resistor r, and the output terminals thereof are input to the comparators C _{D1 to} C _D7 of the seven lower comparators 51 to 57, respectively. Also serves as the first-stage amplifier for comparators 51-57. Transistors Q ₁ and Q ₂ in each switching block are set so that their emitter regions are wider than those of other transistor elements on the IC substrate so that the variations in the respective base-emitter voltage V _BE are extremely small. V _BE
Is set to be even smaller than the quantization level width of at least the LSB of the conversion bit. Therefore, the area of the switching blocks arranged in a matrix occupies the largest area when integrated into an IC. Switching block with shaded lines 11,12,16,17,21,22,
26,27,31,32,36,37,41,42,46,47 output a 2 LSB redundant bit for a 2-bit lower conversion code. , 46, 47 are provided with fixed input signals so that a constant binary signal "H" or "L" is always output when activated by a control signal. In particular, the collectors of the transistors Q ₁ and Q ₂ in the second and fourth rows of the switching block are the lines opposite to the collector outputs of the transistors Q ₁ and Q _{2 in} the _first and third rows of the switching block. It is devised so that the lines of the series reference resistors R _{1 to} R ₁₆ which are connected to each other and to which the reference potential V _RT −V _RB is applied can be folded. Reference numerals 61, 62 and 63 denote three high-order comparators, each of which includes comparators C _{U1 to} C _U3 , complementary output amplifiers CA, and AND gates A _{U1 to} A _U4 . An analog signal V _in is supplied to one input of each comparator C _U of the upper comparators 61 to 63, and a reference obtained by dividing the reference potential V _RT −V _RB by coarse quantization as described above to the other input. Voltages V ₁ , V ₂ and V ₃ are supplied. And the upper comparator
The output of each comparator C _U of 61, 62, 63 becomes “H” or “L” level corresponding to the level of the sampled analog signal, and only one of the AND gates A _U has “1”. "It is configured to output levels. The output signal of each AND gate A _U is wired-OR connected and converted into a binary code through the first encoder 80, and the higher-order 2-bit codes D ₁ and D ₂ are modified in the selection gate 93 described later. . The lower comparators 51 to 57 are also configured in the same manner as the upper comparator, and in particular, the lower comparators 53, 54, 55 further digitize the quantization level selected by the upper comparator into a lower 2-bit code D ₃ , D ₄ are output via the second encoder 70. However, in this AD conversion circuit, comparators 51, 52 and 56, 57 that generate a redundant code of 2 LSB are provided on the left and right sides of the lower comparator, and the code conversion operation is performed even for the analog signal V _in outside the conversion range of the upper comparator. Is being done. Also, as the output circuit of the overflow signal, the output of the AND gate A _D3 of the lower comparator and the output of the AND gate A _U1 of the upper comparator are input to the AND gate A _ov , and the output circuit of the lower comparator is used as the output circuit of the underflow signal. The output of the AND gate A _{D3 and} the output of the AND gate A _U4 of the upper comparator are input to the AND gate A _un . The operation of the above-described embodiment will be described below in the case where the sampling voltage of the analog signal V _in is V _S. For example, if the sampling voltage V _S of the sampled analog signal is V _RB <V _S <V ₃ , the upper comparator 61,
The outputs of the comparators C _U of 62 and 63 all become “L”, and the AND gate A _U outputs the binary signal of [0001] from above. When this signal [0001] is input to the first encoder 80, the wired OR circuit causes [00] on the first two lines [I] and the next two lines [II] [0].
0], [01] is output to the next two lines [III]. When the sampling voltage V _S is V ₃ <V _S <V ₂ , the AND gates A _U1 , A _U2 , A _U3 and A _U4 of the upper comparator similarly output a signal [0010], which is the first signal. When input to the encoder 80, lines [I] to [00], lines [II] to [01], and lines [III] to [10] are output. Hereinafter, the relationship between the input and the output of the first encoder 80 is shown in FIG. 2 including the cases of V ₂ <V _S <V ₁ and V ₁ <V _S <V _RT . Then, in each AND gate A _{U (1,2,3,4)} , the control line (x ₁ , x ₂ , x ₃ ,
The transistor Q ₃ of each switching block connected to x ₄ ) is controlled to be turned on, and the quantization level is further quantified. For example, when only the AND gate A _U3 becomes the “H” level, the transistor Q ₃ of the switching blocks 31 to 37 is turned on, and the reference voltage divided by the reference resistors R _{7 to} R ₁₃ and the sampling voltage V _S become the switching block 31. ~ 37 differentially amplified and compared by the lower comparators 51 ~ 57. Similarly, the switching blocks 21 to 27 are activated when the AND gate A _U2 is at the H level. In this way, the lower conversion code compares the sampled voltage V _S with the reference voltage divided by the reference resistance of that row for each row of the switching block, and the AND gates A _D1 ~ of the lower comparators 51 to 57. A binary signal is output from A _D8 as shown in FIG. 3, and by encoding this binary signal, the lower two-bit conversion codes D ₃ and D ₄ are output from the lower code line [IV]. It At the same time, the output levels of the correction lines V, VI, VII also change as shown in FIG. Then, as shown by
When a 1-level signal is output to any one of V, VI, and VII, the higher-order 2-bit codes D ₁ and D ₂ from the lines I, II, and III of the first encoder 80 are OR gates OR ₁ , It will be selectively output via OR ₂ . The conversion code in which 1 is generated in the correction line VI (0 line), that is, the conversion codes D ₃ and D _{4 of the} lower 2 bits become [00] [01] [10] [11] corresponding to the higher conversion code. And the AND gates A ₁ and A ₂ that form the prohibition gate 92.
The output of the AND gates A ₁ , A ₃ , A ₄ , A _{6 in} the select gate 93 becomes 0, and the upper D of the line [II] output from the first encoder 80 becomes 0. Codes ₁ and D ₂ are AND gates A ₂ and A ₅ and OR gate OR of the selection gate 93.
It is directly output via ₁ and OR ₂ . This case shows the case where the level of the analog signal for outputting the conversion code of the upper 2 bits does not change from the analog signal when outputting the conversion code of the lower 2 bits, and no correction is performed. In the case of a conversion code in which 1 is generated in the correction line V (-1 line), the output of the AND gate A ₁ forming the prohibition gate 92 becomes 1 and the AND gates A ₁ and A _{4 of the} selection gate 93 are opened. As a result, the higher-order 2-bit codes D ₁ and D _{2 of the} line I input to the AND gates A ₁ and A ₄ are output via the OR gates OR ₁ and OR ₂ . In this case, the correction is performed when the level of the analog signal when the upper 2 bits D ₁ and D ₂ are digitized is higher than the analog signal when the lower 2 bits D ₃ and D ₄ are digitized. For example, as shown in FIG. 4, when the true value of the sampling value V _S of the analog signal is V _A , the conversion code of the higher 2 bits erroneously outputs [11] and the lower comparator is correct. When the 2-bit conversion code [11] is output, the higher 2-bit conversion code [11] is subtracted by 1 to correct it to [10] to obtain the correct code output [1011]. That is, in this case, the control line mistakenly selects the line of the switching block, but since the lower comparator 57 on the right side which detects the redundant bit outputs [11], the conversion code of the upper 2 bits is corrected. Will be done. In the case of a conversion code in which 1 is generated in the correction line VII (+1 line), the AND gate A ₂ forming the prohibition gate 92
Becomes 1 and the AND gates A ₃ and A _{6 of the} selection gate 93
Is opened. As a result, the high-order 2 bit codes D ₁ and D _{2 of the} line III input to the AND gates A ₃ and A ₆ are output via the OR gates OR ₁ and OR ₂ , and the high-order 2 bit code is incremented by +1. Will be added. That is, in this case, the correction is made when the sample level of the analog signal when the higher-order 2 bits D ₁ and D ₂ are digitized is lower than the quantization level range at that time. The true value of the signal is
When the upper 2 bits become [00] at the V _B point and the lower 2 bits are digitized to output [00], +1 is added to the upper 2 bits [00] to make [01], [0100] corresponding to the correct analog signal sample voltage V _B is output. As described above, this AD conversion circuit adds a comparator for detecting redundant bits to the lower comparator, and when a lower conversion code outside the range of the upper conversion code is output (hatched area in FIG. 4), correction is made. Since the H-level signal is output to line V or VII and the upper conversion code is corrected, even if the settling characteristic of the sampling circuit is bad due to high-speed sampling, an accurate conversion code detected at the lower time can be obtained. You can Next, the operation for obtaining the overflow signal and the underflow signal in this embodiment will be described. As described above, in practice, it is determined that the converted data is [1111] as an overflow, and the converted data is [0000] as an underflow. Therefore, the converted data is [1111] or [1111]. 0000], the circuit may be configured to output an overflow signal or an underflow signal. According to the code conversion operation described above in the embodiment of FIG. 1, when the output data of the AD conversion circuit is [1111], the upper data is [11] and the lower data is [11]. At the same time, only when the output of the correction line VI becomes “H” (that is, when the upper code is uncorrected). That is, when the output of the AND gate A _U1 of the upper comparator and the output of the AND gate A _{D3 of the} lower comparator become “H”, D _{1 to} D ₄ all become [1]. Therefore, the output of AND gates A _U1 and A _D3 is AND gated.
By taking the logical product via A _ov , it is possible to obtain the overflow signal of “H” output when the output data becomes [1111]. Also, when obtaining the underflow signal, D ₁
~ D ₄ is everything

The case where the value is [0] may be detected. That is, the output data becomes [0000] because the output of the AND gate A _U4 of the upper comparator becomes “H”, and at this time, the AND gate A _{D3 of the} lower comparator that obtains the output {00} inverted by the inverter 100. Detects when "H". Therefore, by taking the logical product of the outputs of the AND gates A _U4 and A _D3 with the AND gate A _un , the output data becomes
0], an underflow signal of “H” output can be obtained. As described above, the predetermined outputs of the upper and lower comparators are directly input to the AND gates A _ov and A _un so that the overflow signal and the underflow signal are obtained, and the AND gates A _ov and A _un are obtained. It is not necessary to use a multi-input circuit with three or more inputs, and even if the number of output bits of the AD conversion circuit is large, it is only necessary to always take the logical product of the binary values of the upper and lower comparator outputs. It can be greatly simplified. In the embodiment of FIG. 1, in the second and fourth rows of the switching block, the application direction of the reference voltage is opposite to that of the first and third rows due to the restriction of the circuit configuration. Therefore, when the second row and the fourth row are selected by the control signal, a signal of "1" level is supplied from the inverter 100 to the inverting gate 91 and ex-OR (1,2), and the correction line It should be noted that the V and VII signals are inverted and the conversion codes D ₃ and D ₄ of the lower 2 bits are inverted. Next, another embodiment of the present invention will be described. FIG. 5 shows a circuit which incorporates a circuit for generating an overflow signal and an underflow signal according to the present invention in the embodiment of the AD conversion circuit previously filed by the present applicant. Indicates the same part. In this circuit, the circuit portion that performs the AD conversion operation, that is, the matrix circuit portion, the upper and lower comparator portions, and the first and second encoder portions are realized by improving the circuit shown in FIG. However, here, detailed description of the operation in each improved part is omitted, but as a serial-parallel AD conversion circuit that makes it possible to correct the upper conversion code by providing redundancy in the lower code conversion, Compared with the circuit configuration of FIG. 1, significant simplification and efficiency improvement have been achieved. Even in such an improved AD conversion circuit, the overflow signal and the underflow signal can be obtained by the same means as in the embodiment of FIG. To get the overflow signal, as mentioned above,
The conversion data D _{1 to} D ₄ may be obtained by ANDing the upper comparator output and the lower comparator output, which are all [1], that is, in this embodiment, the AND gate A _U1 in the upper comparator and When the output of the AND gate A _D6 in the lower comparator becomes “H”, the conversion data becomes [1111], so the AND gates A _U1 and A _D6
It is possible to obtain the overflow signal by taking the logical product of the outputs of the AND gates A _ov . In addition, all the conversion data D _{1 to} D ₄ are underflow signals.

It should be obtained when it becomes [0]. Then, when the output of the AND gate A _U4 in the upper comparator and the output of the AND gate A _D4 in the lower comparator become “H”, the conversion data becomes [0000].
An underflow signal can be obtained by logically ANDing the outputs of A _U4 and A _D4 with an AND gate A _un . With this configuration, similarly to the embodiment of FIG. 1, it becomes possible to obtain the overflow signal and the underflow signal with a simple circuit configuration without requiring a multi-input AND gate. It is a thing.
Also, even if the number of output bits increases, the circuit does not become complicated as in the embodiment of FIG. [Advantages of the Invention] As described above, the AD conversion circuit of the present invention allows the overflow signal or the underflow signal to be output by directly inputting the predetermined output signal of the upper comparator and the predetermined output signal of the lower comparator to the gate circuit. Since the output circuit of the overflow signal or the underflow signal does not have to detect all the conversion data, the multi-input gate circuit is unnecessary, and the conversion bit number However, since the same circuit configuration can be used, there is an effect that the circuit configuration can be greatly simplified.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing one embodiment of the AD conversion circuit of the present invention,
2 and 3 are pattern diagrams showing upper and lower conversion codes, FIG. 4 is a diagram showing the relationship between the quantization level and the conversion code, and FIG. 5 is a circuit showing another embodiment of the present invention. FIG. 6 is a block diagram of a conventional serial-parallel type AD conversion circuit, FIG. 7 is a sampling timing waveform diagram, FIG. 8 (a),
(B) is a sampling waveform diagram. In the figure, 11 to 17, 21 to 27, 31 to 37, 41 to 47 are switching blocks, 51 to 57 are lower comparators, 61 to 63 are upper comparators, 70 is a second encoder, 80 is a first encoder, A _ov and A _un are AND gates.

Claims (1)

[Scope of utility model registration request] 1. A plurality of switching blocks capable of comparing and outputting each reference voltage obtained by folding back and dividing a plurality of resistance groups consisting of n resistances connected in series with a reference potential and outputting the converted input signal. From the output of the switching block comparing the converted input signal with the reference voltage applied to a specific position of the matrix circuit, The output of the matrix circuit in the column direction is commonly input, and the output of the switching block selected by the output of the upper comparator and the data at the folding point are inverted. The lower comparator and the second comparator for obtaining the lower conversion code of the lower b bits by the output inverter. An encoder, and outputs an overflow signal when the logical product of the output of the higher-order bit side of the higher-order comparator and the output of the higher-order bit side of the lower-order comparator reaches a predetermined value, and the lower-order bit side of the comparator. Is output and an underflow signal is output when the logical product of the output of the above and the output of the upper side of the lower comparator reaches a predetermined value.
AD conversion circuit.