JP3221135B2 - Analog / digital conversion circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an analog / digital (hereinafter, A / D) converter for converting an analog signal into a digital signal.
More specifically, the present invention relates to a serial / parallel A / D conversion circuit that converts an analog signal into a digital signal in two stages, upper and lower.

[0002]

2. Description of the Related Art FIG. 5 is a circuit diagram showing a configuration example of a conventional A / D conversion circuit, and shows a circuit configuration for converting an analog signal V _IN into a 4-bit digital code. 5, 10 is a matrix circuit, 21 to 23 are upper comparators, 30 is an upper encoder, 41 to 47 are lower comparators, 50 is a lower encoder, 60 is an inverting gate, 70 is a prohibition gate, 70 is a selection gate, and 90 is a selection gate. Each inverter is shown.

The matrix circuit 10 has 28 switches.
Block S₁₁~ S₁₇, S_{twenty one}~ S ₂₇, S₃₁~ S₃₇And
And S₄₁~ S₄₇Are arranged in a matrix of 4 rows and 7 columns.
Has been established. Each switching block S₁₁~ S₁₇, S
_{twenty one}~ S₂₇, S₃₁~ S₃₇And S₄₁~ S ₄₇Is an npn-type
Transistor Q₁, Q_TwoAnd Q_ThreeOf differential type
It is composed of Excluding some, so-called differential
One transistor Q forming a pair₁Base on the basis of
Voltage V_RT-V_RBIs the reference resistance element R₁~ R₁₆Group divided by
A reference voltage is supplied, and the other transistor Q_TwoAt the base of
Is the analog signal V to be converted to a digital code_INBut
Supplied respectively. Also, the transistor Q₁And Q
_TwoAre connected to each other, and the connection midpoint is described later.
Transients switched by control signals
Star Q_ThreeAre respectively connected to the current source I.
Also, the transistor Q₁And Q_TwoThe collector has no resistance
power supply voltage V _DDAnd its output terminal is 7
C of the lower-order comparators 41 to 47_D1~ C_D7To
Input to the first stage of the lower comparators 41 to 47
Also serves as an amplifier.

[0004] In the figure, the switching block shaded
S₁₁, S₁₂, S₁₆, S₁₇, S_{twenty one}, S _{twenty two}, S₂₆, S₂₇, S
₃₁, S₃₂, S₃₆, S₃₇, S₄₁, S₄₂, S₄₆, S₄₇Is 2
2 LSB redundancy for lower conversion code of bits
And outputs a bit.₁₁, S
₁₂, S₄₁, S₄₂Is activated by a control signal
The constant binary signal "H" or "L"
A fixed input signal is provided to be output.
Also, in particular, the second and fourth rows of the switching block
Transistor Q_1,Q_TwoThe collector of the switching block
Transistors Q in the first and third rows of_1,Q_TwoCollection of
Connected to the line in the direction opposite to the_RT−
V_RBIs applied to the series reference resistance element R.₁~ R₁₆Line of
Is designed so that it can be folded.

[0005] The three upper comparators 21, 22, 23
_Are comparators C _{U1 to} C _U3 , respectively, and complementary output amplifier C
A and AND gates A _{U1 to} A _U4 . An analog signal V _IN is supplied to one input of each of comparators C _{U1 to} C _U3 of upper comparators 21 to 23, and a reference voltage obtained by dividing reference potentials V _{RT to} V _RB by coarse quantization is applied to the other input. V ₁ , V ₂ and V ₃ are supplied. Upper comparator 21
The output of each comparator C _U1 -C _U3 of to 23, corresponding to the level of the sampled analog signal becomes a level of "H" or "L", any one of the respective AND gates A _U1 to A _U4 Only one is configured to output a “1” level.

The output signals of the AND gates A _{U1 to} A _U4 are wired and converted into a binary code via the upper encoder 30, and are converted into upper two-bit codes D ₁ and D ₂ by a selection gate 80 described later. Modifications are made.

The lower comparators 41 to 47 have the same configuration as the upper comparators 21 to 23. In particular, the lower comparators 43, 44, and 45 further quantify the quantum level selected by the upper comparator to obtain a lower 2nd digit. bit code D _3, D ₄ and the lower encoder 50
Output via.

Further, in this A / D conversion circuit, comparators 41, 42 and 46, 47 for generating a redundant code of 2 LSB are provided on the left and right of the lower comparator.
The code conversion operation is also performed on the analog signal V _IN outside the conversion range of the lower comparator specified by the upper comparators 21 to 23.

In such a configuration, for example, if the sampling voltage V _s of the sampled analog signal is V _RB <V _S <V ₃ , the upper comparators 21 and
The outputs of 2, 23 comparators C _{U1 to} C _U3 are all “L”, and binary signals of “0” are output from AND gates A _{U1 to} A _U3 , and “1” is output from A _U4 . as a result,
[0001] is input to the upper encoder 30, and the first binary signal is input by a so-called wired OR circuit.
In the line [LN ₃₁ ]

[00], the next two lines [LN ₃₂ ]

[00], [01] is output to the next two lines [LN ₃₃ ].

Further, if the sampling voltage V _S is V ₃ <V _S
<When the V _2, similarly the upper AND gate A _U1,
A _U2 and A _U4 output binary signals of “0”, and A _U3 output a binary signal of “1”. As a result, [0010] 2
The value signal is input to the upper encoder 30 and the line [LN
₃₁ ]

[00], line [LN₃₂] To [0
1], line [LN ₃₃] Is output as [10].
Hereinafter, V_Two<V_S<V₁, V₁<V_S<V_RTIncluding
First, the relationship between the input and output of the upper encoder 30 is shown in FIG.
Is shown.

In parallel with this, each AND gate A
Transistors of each switching block connected to the _{U (1, 2, 3, 4)} control line binary output signal in is "1" _{(x 1, x 2, x} 3, x 4) Q ₃ is controlled to be on, finer digitizing of quantization levels is performed.

For example, AND gate A_U3Only the output of
When the "1" level is reached, the switching block S₃₁~ S
₃₇Transistor Q_ThreeTurns on and the reference resistance element R₇
~ R ₁₃Reference voltage and sampling voltage V divided by_SBut
Switching block S₃₁~ S₃₇Differentially amplified by
The comparison is performed by the lower comparators 41 to 47. As well
And AND gate A_U2When the output of the
Switching block S_{twenty one}~ S₂₇Is activated_,Differential
The amplification operation is performed, and the lower comparators 41 to 47 perform the amplification.
Comparison is performed.

As described above, the lower conversion code is obtained by sampling the voltage V _S on a row-by-row basis in the switching block.
Is compared with the reference voltage divided by the reference resistance element in the row, and the AND gate A _{D1 of the} lower comparators 41 to 47 is compared.
From to A _D7 and A _D8 is output binary signal as shown in FIG. 7, these by the binary signal is encoded at a lower encoder 50, converts the code D of the lower 2 bits from the lower cord line [LN _{51] 3} and D ₄ are output. Similarly, the output level of the selected lines LN _52, LN _53, LN ₅₄ also changes as shown in FIG.

[0014] Then, as shown below,
Selection line LN₅₂, LN₅₃, LN ₅₄One of
When a “1” level signal is output,
Line LN in DA 30₃₁, LN₃₂, LN₃₃From above
2 bits conversion code D₁, D _TwoIs OR gate O
R₁, OR_TwoSelectively output via

A conversion code in which “1” occurs in the selection line LN ₅₃ (0 line), that is, conversion codes D ₃ and D _{4 of} lower 2 bits correspond to upper conversion codes

When [00], [10], and [11], the prohibition gate 7
AND gate A constituting 0₁, A _TwoOutput to "0"
Therefore, the AND gate A in the selection gate 80₁,
A_Three, A_FourAnd A₆Is "0". The result
As a result, the line [L
N₃₂] Top D₁, D_TwoCode of select gate 80
Gate A_Two, A_FiveAnd OR gate OR ₁, OR_Two
Is output as is. In this case,
The level of the analog signal when converting two bits is
It changes with the analog signal when converting the lower 2 bits.
No corrections are made.

Selection line LN₅₂Is “1” andge
A_U1Or A_U3Is "1" and the selection line
LN₅₄Is "1" and AND gate A_U4Or A_U2Is "1"
In the case of &quot; A &quot;
₁And A_FourOpens. As a result, AND gate A₁, A
_FourLine LN input to₃₁Upper 2 bits of
Do D₁, D_TwoIs OR gate OR_1,OR_TwoOutput via
It is. In this case, the upper two bits D₁, D_TwoThe number
The level of the analog signal when digitized is the lower 2 bits
D_Three, D_FourHigher than the analog signal when
In such a case, the correction is performed. For example, as shown in FIG.
The analog signal sampling value V_SIs the true value of V _Aso
At some point, the conversion code of the upper 2 bits is incorrectly [1
0] and the lower 2 comparators
When the conversion code [11] is output,
Subtract "1" from the conversion code [10] to [01]
To get the correct code output [0111]
is there. That is, in this case, the control line is wrong.
Means that the line of the switching block has been selected.
The lower-order comparator 4 on the right side that detects a redundant bit.
6

In order to output [00], the conversion code of the upper two bits is modified.

[0017]; if the selected line LN ₅₄ is "1" in the AND gate A _U1 or A _U3 is "1", and selects the line LN ₅₂ is "1" in the AND gate A _U4 or A _U2 is "1"
In the case of &quot; A &quot;
The output of the ₂ "1", the AND gates A ₃ and A ₆ of the select gate 80 is opened. As a result, the upper two lines LN ₃₃ input to the AND gates A ₃ and A ₆
Bit code D ₁ , D ₂ are OR gates OR ₁ , OR ₂
, And “+1” is added to the upper two bits of the code. That is, in this case, correction is performed when the sample level of the analog signal when the upper two bits D ₁ and D ₂ are digitized is lower than the quantum level range at that time. For example, the analog signal V
When the true value of _IN is at the V _B point in FIG. 8, the upper 2 bits

When it becomes [00], the numerical value of the lower 2 bits is

[00]
Output, the upper 2 bits

Adding "+1" to [00] and [01], in which to output a corresponding sample voltage V _B of the correct analog signal [0100].

This A / D conversion circuit adds a comparator for detecting a redundant bit to the lower comparator as described above, and outputs a lower conversion code outside the range of the upper conversion code (shown by hatching in FIG. 8). regions shown), outputs "1" level signal to the select line LN ₅₂ or LN _54, since the correction of the upper transformation code, even when settling characteristics of the sampling circuit by the fast sampling is poor, detected at lower point There is an advantage that an accurate converted code can be obtained.

[0019]

As described above, in the conventional circuit, correction is performed based on the concept of adding "1" and subtracting "1" in order to correct the upper code. Therefore, the normal data, the lower redundant data (data obtained by subtracting 1 from the normal data) and the upper redundant data (data obtained by adding 1 to the normal data) are grouped into the upper data, and selected from the lower encoder. It is configured so that one of three groups is selected by a signal. However, a column in which the right portion of the resistor column becomes lower redundant and a column in which the upper portion becomes redundant alternately exist. Therefore, there is a case where the lower encoder connected to the right part of the resistor row selects the lower redundant data or a case where the lower redundant data selects the upper redundant data. Therefore, which data is to be selected differs for each column, so that an inversion gate 60 and a prohibition gate 70 are required to control this.

However, the selection signals (LN ₅₂ , LN ₅₃ , LN ₅₄ in the figure) from the lower encoder 50 are transmitted to the selection gate 80 after passing through the inversion gate 60 and the inhibition gate 70, so that the selection signal Is input to the selection gate 80 later than the upper data output from the upper encoder 30. For this reason, there is a problem that the output of the conversion code is delayed due to the presence of the inversion gate 60 and the inhibition gate 70, and the conversion time of the A / D conversion circuit increases. Further, in addition to the necessity of extra inversion gates and prohibition gates, three selection signals are required, and the upper code to be selected is also three.
Since the number of pairs is required and the number of input gates in the selection gates is increased, there is a problem that the chip area and power consumption are increased. Further, in order to obtain the upper a bits, (2 ^a -1) upper comparators are required, and 2 ^a rows of switching blocks are required. This is one of the factors that increase the chip area and power consumption. Has become.

The present invention has been made in view of such circumstances, and an object of the present invention is to provide an A / D conversion circuit capable of increasing the speed of conversion processing, reducing the chip area, and reducing power consumption. .

[0022]

In order to achieve the above object, according to the present invention, a plurality of reference resistance elements connected in series between two reference potentials are arranged in a matrix and have a higher conversion output. is activated for each row by the signal, comparing the respective reference voltage and the converter input signal by dividing by the reference resistance element, a plurality of detecting the presence or absence of the lower bit data and the redundant bit data switching blocks Kudea
Therefore, to determine the upper bits with 1/2 offset
A plurality of derived reference voltage points and a high reference voltage point (VR
T) and the low reference voltage point (VRB).
Divided voltage sandwiched between two adjacent points and extended to both sides
Received in a single row with the divided voltage for redundancy, arranged in adjacent order
And the number of upper bits generated between adjacent rows, excluding at least the top row or bottom row of the switching block matrix.
A reference voltage, which is a voltage step corresponding to the resolution of the input signal, is compared with the input signal to be converted, and at least one data change point detection circuit for detecting a data change point is provided, according to the detection result of the data change point detection circuit. A higher-order encoder for obtaining a conversion code of adjacent higher-order bits according to two modes set in advance; and a column-based output of each switching block is divided into two groups corresponding to the two modes. A predetermined lower-order conversion code is obtained in accordance with the presence or absence of lower-order bit data and redundant bit data .
The input analog voltage is converted into two upper bit conversion codes
Which of the two corresponding reference voltage ranges belongs
And a lower encoder for generating a selection signal for selecting a conversion code to which the higher-order encoder belongs from the two upper-bit conversion codes, and two upper-order encoders output from the upper encoder. A selection gate for selectively outputting one of the bit conversion codes based on the selection signal output from the lower encoder is provided.

In the present invention, the reference resistance elements are arranged so as to be folded over a predetermined number of rows so as to correspond to the matrix arrangement of the switching blocks, and generate the highest reference voltage. A row of resistance elements and a row of resistance elements that generate the lowest reference voltage are
It is arranged to be shifted by a predetermined period with respect to the rows of other resistance elements,
The output conversion code value of the upper encoder is set according to the transition direction of the reference voltage level for each row.

In the present invention, the predetermined period is a half period.

In the present invention, the switching block columns arranged in a matrix are divided into two column groups based on a predetermined column, and these column group outputs correspond to the two groups of the lower encoder. The output conversion code value of the upper encoder is set so as to have a difference in magnitude in the order of one mode and the other mode.

In the present invention, the two groups are divided based on the switching point of the upper bit in the output conversion code.

In the present invention, the lower encoder is configured to generate two selection signals corresponding to two divided groups.

According to the present invention, the lower encoder is configured to generate one selection signal corresponding to one of the two divided groups.

[0029]

According to the present invention, when an analog signal is input, in the data change point detection circuit, the input signal and the reference voltage generated between adjacent rows except for at least the uppermost row or the lowermost row of the switching block matrix. Are compared with each other to detect a data change point, and the detection result is output to the upper encoder. At this time, when the top row of the matrix is removed, the data change point detection circuit corresponding to the top row is also used as the data change point detection circuit corresponding to the next lower row, and when the bottom row of the matrix is removed, The data change point detection circuit corresponding to the lower row is also used as one data change point detection circuit corresponding to the upper row. In the high-order encoder, a conversion code of high-order bits corresponding to a mode set in advance is selected according to the detection result, and is output to the selection gate. In parallel with the conversion operation of the higher-order bits, the input analog signal is supplied to the reference resistance element in each of the switching blocks activated by the higher-order conversion output signal among the switching blocks arranged in a matrix. Is compared with each reference voltage. The comparison result of these switching blocks is output to the lower encoder as lower bit data or redundant bit data. In the lower encoder, division into two groups according to the two modes is performed based on the output data of each activated switching block, and depending on the presence or absence of lower bit data and redundant bit data for each divided group. A predetermined lower conversion code is obtained and output. In parallel with this, a selection signal for selecting one of the two upper bit conversion codes of the upper encoder is generated, and this selection signal is output to the selection gate. In the selection gate, one of the two upper-bit conversion codes output from the upper encoder is selected based on the selection signal output from the lower encoder, and is output as an upper conversion code.

According to the present invention, the output conversion code value of the upper encoder is determined and set according to the transition direction of the reference voltage level for each row, for example, the direction of transition from low potential to high potential, Further, for example, the output conversion code value of the upper encoder is set so as to have a difference in magnitude in the order of one mode and the other mode. Further, the reference resistance element is folded back and arranged in a predetermined number over a plurality of rows so as to correspond to, for example, a matrix arrangement of the switching blocks, and a row of the resistance element generating the reference voltage of the highest value and a lower row of the resistance element. A row of resistance elements generating a reference voltage having a value is shifted by a predetermined cycle, for example, a half cycle, with respect to rows of other resistance elements.

Further, according to the present invention, the two groups to be divided are the switching point of the upper bit in the output conversion code, for example, the point where the upper bit “00” switches to “01”,
Division is performed based on the point at which “01” switches to “10”.

Further, according to the present invention, the lower encoder generates two selection signals corresponding to the two divided groups.

According to the present invention, the lower encoder generates one selection signal corresponding to one of the two divided groups.

[0034]

1 shows a first embodiment of an A / D conversion circuit according to the present invention.
FIG. 3 is a circuit diagram showing an example of the embodiment. 1, 100 is a matrix circuit, 111 and 112 are upper comparators as data change point detection circuits, 120 is an upper encoder, 131 to 137 are lower comparators, 140 is a lower encoder, 150 is a selection gate, 160 is an inverter, and R _{1 to} R ₁₆ are reference resistance elements, B _{U1 to} B _U3 , B _{D1 to} B
_D8 is multi-output pin buffers, OR _1, OR ₂ is an OR gate, EXO _1, EXO ₂ indicates an exclusive OR gate, respectively.

The matrix circuit 100 includes 21 switching blocks S _{11 to} S ₁₇ , S _{21 to} S ₂₇ and S _{31 to} S _27.
37 are arranged in a matrix of 3 rows and 7 columns. Each switching block _{S 11 ~S 17, S 21 ~S} 27 and S ₃₁ to S ₃₇ is constituted by a differential amplifier consisting of npn-type transistors Q _1, Q ₂ and Q _3. The base of _one transistor Q1 forming a so-called differential pair of each switching block has a reference voltage V _RT −
A reference voltage obtained by dividing V _RB by reference resistance elements R _{1 to} R ₁₆ is supplied, and an analog signal V _IN to be converted into a digital code is supplied to the base of the other transistor Q ₂ . The emitters of the transistors Q ₁ and Q ₂ are connected to each other, and the midpoint of the connection is a control signal x.
₁ ~ x ₃ Transistor Q ₃ switched by
Are respectively connected to the current source I. The power supply voltage V _DD is supplied to the collectors of the transistors Q ₁ and Q ₂ via the resistance element r.
Comparators C _D1 to C _D of the lower comparators 131 to 137
_D7 are input to the lower comparators 131 to 13 respectively.
7 also used as the first stage amplifier. In addition, the second from the bottom in the figure
The collector of the transistor Q _1, Q ₂ of the row of switching blocks are connected in the opposite direction of the line and the transistor Q _1, the collector Q ₂ 'outputs of the first row and the third row of the switching block, the reference potential V It is designed so that the lines of the series reference resistance elements R _{1 to} R ₁₆ to which _RT- V _RB is applied can be formed by folding back.

The reference resistance elements R _{1 to} R ₁₆ are connected in series between two reference potentials V _RT and V _RB, and are arranged in predetermined numbers so as to correspond to a matrix arrangement of switching blocks in the matrix circuit 100. It is folded back over a plurality of rows, in this embodiment five rows. Specifically, the first and fifth rows from the bottom in the figure each have 2
One of the resistance element R _16, R ₁₅ and R _2, R ₁ are connected in series, the second row - fourth row each of the resistive elements R ₁₄ -
R _11, R ₁₀ ~R ₇ and R ₆ to R ₃ are connected in series.

The folded arrangement of the resistor element rows is such that when viewed from the reference potential V _RB terminal located at the left end and the lower end side of the matrix circuit 100, the wiring pattern extending rightward in the figure is the fourth row from the left in the figure. Is folded between the fifth switching block row and the fifth switching block row,
Two resistance elements R ₁₆ and R ₁₅ are connected in series to
A resistance column in the row is configured.

The resistance row of the first row is turned back between the third switching block row and the second switching block row, and is connected between the first row and the second switching block row. and, second row of resistor string corresponding to the arrangement positions of four resistance elements R ₁₄ to R ₁₁ are connected in series in the first line of the switching block S ₃₃ to S ₃₆ are configured .

The resistance row in the second row is turned back between the fifth switching block row and the sixth switching block row, and is connected between the first row and the second switching block row. and third row of resistors column four resistive elements R ₁₀ to R ₇ corresponding to the arrangement position of the second row of the switching block S ₂₆ to S ₂₃ are connected in series is constituted .

The resistance row in the third row is turned back between the third switching block row and the second switching block row, and the third row of switching blocks S
Four resistance elements R _{6 to} R ₆ corresponding to the arrangement positions of _{13 to} S _16
3 are connected in series to form a fourth row of resistance columns.

The resistance row of the fourth row is turned back between the fifth switching block row and the sixth switching block row, and the third row of switching blocks S
Two resistance elements R _{2 to} R 2 corresponding to the arrangement positions of _{16 to} S _15
1 are connected in series, one end of the resistance element R ₁ is the reference potential V
The fifth row of resistance columns is connected to the terminal of _RT .

That is, the position of the lowest reference voltage (the connection point between the reference potential V _RB terminal and the resistor R ₁₆ ) and the position of the highest value (the connection point between the reference potential V _RT terminal and the resistor R ₁₎ ) Are located at intermediate points in the row direction of the switching blocks arranged in a matrix, so that the resistance columns in the first and fifth rows are different from the resistance columns in the second to fourth rows. They are staggered by half a cycle. As described later, the arrangement configuration of the resistor rows includes a switching block row composed of seven rows at upper and lower switching points, and a group of switching block rows from the first row to the fourth row and a switching block row from the fifth row. This is for the purpose of dividing into two groups with the switching block row of the seventh row.

The voltage V generated between the fourth and third rows of the resistance column and the third and second rows of the resistance column.
₁ and V ₂ are supplied to the upper comparators 111 and 112 as reference voltages obtained by dividing the reference potentials V _{RT to} V _RB by coarse quantization. In the configuration of FIG. 1, the reference potential V _RT
Assuming that the voltage between V _{RB and} V _RB is V _REF , the reference voltages V ₁ , V
₂ has the following values, respectively. V ₁ = (10/16) · V _REF V ₂ = (6/16) · V _REF

Further, the reference voltages e _{1 to} e ₁₅ divided by the reference resistance elements R _{1 to} R ₁₆ are wired so as to be supplied to the base of the transistor Q ₁ of a predetermined switching block. Specifically, a reference voltage e ₁ [= (15/16) · V _REF ] generated at a connection point between the resistance elements R ₁ and R _2.
Is supplied to the base of the transistor to Q ₁ switching block S _17. Resistive element reference voltage e ₂ generated at the connection point between R ₂ and R ₃ [= (14/16) · V _{RE F]} is supplied to the base of the transistor to Q ₁ switching block S _16. Resistance element R ₃ and the reference voltage e ₃ that generated at the connection point between R ₄ [= (13/16) · V _{RE F]} is supplied to the base of the transistor to Q ₁ switching block S _15. Reference voltage e generated at the midpoint of connection between resistance elements R ₄ and R _5
4 [= (12/16) · V _{RE F]} is the switching block S ₁₄
It is supplied to the base of the transistor Q _1. Resistance element R
Reference voltage e ₅ generated at the midpoint of connection between ₅ and R ₆ [= (11 /
16) · V _{RE F]} is supplied to the base of the transistor to Q ₁ switching block S _13, S _21. A reference voltage e ₆ generated at the midpoint of connection between the resistance elements R ₆ and R ₇ [= V ₁ = (1
0/16) · V _REF] is supplied to the base of the transistor to Q ₁ switching block S _12, S _22. Resistance element R ₇
Reference voltage e ₇ generated at the midpoint of connection between R ₈ and R ₈ [= (9/16)
· V _REF] is supplied to the base of the transistor to Q ₁ switching block S _11, S _23. Resistors R ₈ and R ₉
Reference voltage e ₈ [= (8/16) · V
_REF] The transistor to Q ₁ switching block S ₂₄
Supplied to the base. The reference voltage e ₉ [= (7/16) · V _REF ] generated at the midpoint of the connection between the resistance elements R ₉ and R ₁₀ is supplied to the base of the transistor Q ₁ of the switching blocks S ₂₅ and S ₃₇ . The reference voltage e ₁₀ [= V ₂ = (6/16) · V _REF ] generated at the midpoint of the connection between the resistance elements R ₁₀ and R ₁₁ is supplied to the base of the transistor Q ₁ of the switching blocks S ₂₆ and S _36. You. The reference voltage e ₁₁ [= (5/16) · V _REF ] generated at the midpoint of the connection between the resistance elements R ₁₁ and R ₁₂ is supplied to the base of the transistor Q ₁ of the switching blocks S ₂₇ and S ₃₅ . The reference voltage e ₁₂ [= (4/16) · V _REF ] generated at the midpoint of the connection between the resistance elements R ₁₂ and R ₁₃ is supplied to the base of the transistor Q ₁ of the switching block S ₃₄ . Reference voltage e ₁₃ generated at the midpoint of connection between resistance elements R ₁₃ and R ₁₄
[= (3/16) · V _REF] is supplied to the base of the transistor to Q ₁ switching block S _33. Reference voltage e ₁₄ generated at the midpoint of connection between resistance elements R ₁₄ and R ₁₅ [= (2/16) ·
V _REF] The transistor Q of the switching block S ₃₂
Supplied to ₁ base. The reference voltage e ₁₅ [= (1/16) · V _REF ] generated at the connection point between the resistance elements R ₁₅ and R ₁₆ is supplied to the base of the transistor Q ₁ of the switching block S ₃₁ .

The upper comparators 111 and 112
Each comparator C_U1, C_U2, The complementary output amplifiers CA and
AND gate A_U1, A_U2It has. It will be described later
For the reason, the upper comparator 111
The upper comparator 112 also serves as the
Also serves as the upper comparator for the lower row. Top Con
Comparator C of parator 111_U1Analog input to one input
Signal V_INIs supplied, and the other input is supplied with the reference potential V._RT~ V
_RBReference voltage V obtained by dividing voltage by coarse quantization ₁[= (10/16) ・
V_REFIs supplied. Comparison of upper comparator 112
Container C_U2Analog signal V_INIs supplied,
The reference potential V is applied to the other input._RT~ V_RBIs divided by coarse quantization
Reference voltage V _Two[= (6/16) ・ V_REFIs supplied.

The output of the comparator C _U1 of the upper comparator 111 is connected to the input of the output amplifier CA, its positive output is connected to both inputs of the two-input AND gate A _U1 , and its negative output is the output of the upper comparator 112. It is connected to one input of input AND gate A _U2 . Upper comparator 112
The output of the comparator C _U2 is connected to the input of the output amplifier CA, the positive side output is connected to the other input of the two-input AND gate A _U2 , and the negative side output is connected to both inputs of the two-input AND gate A _U3. It is connected.

The upper comparator 1 configured as described above
The outputs of the comparators C _U1 and C _U2 of the comparators 11 and 112 are set to “H” in accordance with the level of the sampled analog signal V _IN.
Or, the level becomes “L”, and each AND gate A _{U1 to} A
Only one of _U3 outputs "1" level. The output of the AND gate A _U1 upper comparator 111 is connected to the upper encoder 120 via a buffer B _U1, is connected to the base of the transistor Q ₃ of the switching block S ₁₁ to S _17. Upper comparator 11
The output of the second AND gate A _U2 is is connected to the upper encoder 120 via a buffer B _U2, are connected to the base of the transistor Q ₃ of the switching block S ₂₁ to S _27, the input of the inverter 160 via a buffer It is connected. The output of AND gate A _U3 is buffer B _U3
Connected to the upper encoder 120 via
Is connected to the base of the transistor Q ₃ of the switching block S ₃₁ to S _37.

The upper encoder 120 includes an encoder line LN ₁₂₁ for generating L (left) mode data,
(Right) Encoder line LN that generates mode data
₁₂₂ . That is, the upper encoder 120 includes the switching blocks S _{11 to} S ₁₇ , S _{21 to} S ₂₇ and S ₃₁ to S ₃₁ arranged in the matrix circuit 100.
Among the S _37, the second group from the fifth column of the seventh row arranged from the first row to the first group and the right side of the fourth row arranged central than the left side of the matrix circuit 100 in correspondence, each encoder line LN ₁₂₁ and LN ₁₂₂ is set.

FIG. 2 shows the upper comparators 111 and 112.
Of the AND gates A _U1 , A _U2 and A _U3 and the encoder lines LN ₁₂₁ and L N of the upper encoder 120
Shows the correspondence between the N _{12 2} Configuration Output data code pattern. The data is set from the first row to the fifth row (in the present embodiment, the second row to the fourth row in this embodiment) of the series-connected reference resistance element group that is folded and arranged to have five rows.
(L) in accordance with the transition direction of the reference voltage level by each reference resistance element in each row (specifically, the directivity in which the reference voltage transitions from the low potential side to the high potential side).
(Mode data) <(R mode data), (L mode data)> (R mode data).

In the configuration of FIG. 1, the resistance elements R ₁₆ , R
Has from the bottom of ₁₅ to the first row, the third row including a resistor element R ₁₀ to R _7, the same directivity and the fifth row including a resistor element R _2, R _1, resistor a second line consisting of elements R ₁₄ to R _11, and the fourth row comprising a resistive element R ₆ to R ₃ have the same directivity. Therefore, the data setting level when the AND gate A _U2 corresponding to the third row is at “1” level is set so that (L mode data)> (R mode data). In contrast, the second
AND gates A _U3 and A _U1 corresponding to the rows and the fourth row
Is set to be "1" level, the data setting level is set so that (L mode data) <(R mode data).

The lower comparators 131 to 137 include comparators C _{D1 to} C _D7 , a complementary output amplifier CA and AND gates A _{D1 to} A _D7 , respectively. Comparator one of the collector output of the transistor Q ₂ in the first column of transistors to Q ₁ collector output and the switching block S ₁₁ of the switching block S _21, S ₃₁ of the matrix circuit 100 to the input of C _D1 of the low-order comparator 131 is supplied, the other input collector output of the transistor Q ₂ of the switching block S _11, the transistor to Q ₁ collector output and switching block S ₂₁ of S ₃₁ is supplied.

[0052] The comparator C collector output and the switching block S ₁₂ of the transistor to Q ₁ switching block S ₂₂ of the second column of the matrix circuit 100 to the input of one of the _D2, S ₃₂ of the low-order comparator 132 of the transistor Q ₂ collector output is supplied to the other input collector output of the transistor Q ₂ of the switching block S _12, S ₃₂ of the transistor to Q ₁ collector output and switching block S ₂₂ is supplied.

[0053] to one input of a comparator C _D3 of the lower comparator 133 of the transistor Q ₂ in the third column of the switching block transistor to Q ₁ collector output and switching block S ₁₃ of S _23, S ₃₃ of the matrix circuit 100 collector output is supplied to the other input collector output of the transistor Q ₂ switching block S _13, the collector of the transistor to Q ₁ S ₃₃ output and the switching block S ₂₃ is supplied.

[0054] The comparator C collector output and the switching transistor to Q ₁ switching block S ₂₄ in the fourth column of the matrix circuit 100 to the input of one of the _D4 block S _14, S ₃₄ of the low-order comparator 134 of the transistor Q ₂ collector output is supplied to the other input collector output of the transistor Q ₂ collector output and switching block S ₂₄ of the transistor to Q ₁ switching block S _14, S ₃₄ are supplied.

[0055] The comparator C collector output and switching block S ₁₅ of the transistor to Q ₁ switching block S ₂₅ in the fifth column of the matrix circuit 100 to the input of one of the _D5, S ₃₅ of the low-order comparator 135 of the transistor Q ₂ collector output is supplied to the other input collector output of the transistor Q ₂ switching block S _15, the collector of the transistor to Q ₁ S ₁₅ output and the switching block S ₂₅ is supplied.

[0056] The comparator sixth column of transistors to Q ₁ collector output and switching block S ₁₆ of the switching block S ₂₆ for the matrix circuit 100 to one input of C _D6, S ₃₆ of the low-order comparator 136 of the transistor Q ₂ collector output is supplied to the other input collector output of the transistor Q ₂ switching block S _16, the transistor to Q ₁ collector output and switching block S ₂₆ of S ₃₆ is supplied.

[0057] The comparator one collector output input transistor to Q ₁ seventh column of the switching block S ₂₇ for the matrix circuit 100 in the and the switching block S _17, S ₃₇ of the C _D7 lower comparator 137 of the transistor Q ₂ It is supplied collector output, the other input collector output of the transistor Q ₂ switching block S _17, S ₃₇ of the transistor to Q ₁ collector output and switching block S ₂₇ is supplied.

The output of the comparator C _D1 of the lower comparator 131 is connected to the input of the output amplifier CA, its positive output is connected to both inputs of the two-input AND gate A _D1 , and its negative output is the output of the lower comparator 132. It is connected to one input of input AND gate A _D2 . Lower comparator 132
The output of the comparator C _D2 of being connected to an input of the output amplifier CA, its positive output is connected to the other input of the 2-input AND gates A _D2, the negative side output 2 of the low-order comparator 133
It is connected to one input of input AND gate A _D3 .
The output of the comparator C _D3 of the lower comparator 133 is connected to the input of the output amplifier CA, the positive output is connected to the other input of the two-input AND gate A _D3 , and the negative output is the two-input AND of the lower comparator 134. It is connected to one input of gate _AD4 . The output of the comparator _CD4 of the lower comparator 134 is connected to the input of the output amplifier CA, its positive output is connected to the other input of the two-input AND gate A _D4 , and its negative output is the two-input AND of the lower comparator 135. It is connected to one input of gate A _D5 . The output of the comparator C _D5 of the lower comparator 135 is connected to the input of the output amplifier CA, its positive output two-input AND gates A _D5
, And the negative output is connected to one input of a two-input AND gate A _D6 of the lower comparator 136. The output of the comparator C _D6 lower comparator 136 is connected to the input of the output amplifier CA, its positive output 2
The negative output is connected to the other input of the input AND gate A _D6 , and the two-input AND gate A _D7 of the lower comparator 137
Is connected to one input. Lower comparator 13
7, the output of the comparator C _D7 is connected to the input of the output amplifier CA, the positive side output is connected to the other input of the two-input AND gate A _D7 , and the negative side output is both inputs of the two-input AND gate A _D8 . It is connected to the.

The lower comparator 1 configured as described above
The outputs of the comparators C _{D1 to} C _D7 of 31 to 137 become “H” or “L” in correspondence with the levels of the two inputs.
Only one of each AND gate A _{D1 to} A _D8 is “1”
Output level. The outputs of AND gates A _{D1 to} A _D7 and A _D8 of lower comparators 131 to 137 are buffer B
It is connected to the lower encoder 140 via the _D1 .about.B _D8.

The lower encoder 140 has a lower data BD
_Three, BD_FourData line LN that generates₁₄₁And the lower
AND gate A of comparators 131-134_D1~ A_D4of
A selection signal S indicating that one of the outputs has become "1"
EL₁Select line LN that generates₁₄₂And the lower compare
Data 135 to 137 AND gate A_D5~ A_D7And A _D8
Selection signal indicating that one of the outputs has become "1"
SEL_TwoSelect line LN that generates₁₄₃Is composed of
ing.

FIG. 3 shows the upper AND gates A _{U1 to} A _U3.
3 shows the correspondence between the outputs of the lower AND gates A _{D1 to} A _D8 and the output conversion code data. As described above, the matrix circuit 100 in this embodiment divides each switching block into two in the row direction. The division point C is, as can be seen from FIG.
Focusing on the upper two bits of ₁ to D _4, it is divided at the point where the value of the upper 2 bits are switched.

Also, originally, the number of upper-side AND gates (the number of upper comparators) is adjusted according to the number of rows of the resistor column, "5".
In this embodiment, the two AND gates _AL and _L corresponding to the resistance columns in the first row (bottom row) and the fifth row (top row) are required. _AH is omitted, and as a result, the switching blocks to be arranged at the lowermost stage and the uppermost stage are omitted for two rows. Hereinafter, the reason why the AND gate and the switching block can be omitted will be described with reference to FIG.

Here, first, a configuration is imagined in which a switching block is provided at the uppermost stage and a high-order comparator having an AND gate A _H and a drive buffer for the high-order encoder 120 are provided correspondingly. In such a configuration, consider a case where the input analog signal V _IN is larger than the reference voltage e ₂ (V _IN > e ₂ ), the comparator output becomes “H”, and the output of the AND gate A _H becomes “1” level. Then, the output in this case is one of four types of [1111] to [1100] as shown in FIG. Focusing on these four types of data, these data are stored in the upper comparator 11 in the lower stage.
This is the same as data obtained when the output of one AND gate A _U1 is at the “1” level and any of the outputs of the lower AND gates A _{D5 to} A _D8 is at the “1” level. Therefore,
When the top of the AND gate A _H becomes "1" level, instead of activating the drive buffer of the uppermost switching block and the upper encoder 120, and one lower switching block S ₁₁ to S ₁₇ means that the buffer B _U1 it is sufficient to activate. This means that the output of AND gate A _H and AND gate A _U1
Sum switching block S ₁₁ to S ₁₇ and drive buffer of the uppermost corresponding switching block and the upper encoder be given to the buffer B _U1 and output means that the unnecessary. That is, V _IN > V ₁ (= e
In the case of ₆₎ may be activated the switching block S ₁₁ to S ₁₇ and the buffer B _U1 as in this embodiment,
Since there is no need to compare the input analog signal V _IN with the reference voltage e ₂ , there is no need for an upper comparator corresponding to the uppermost stage.

Similarly, one row of switching blocks is provided at the lowest stage, and correspondingly, the AND gates A _L
A configuration provided with a higher-order comparator having In such a configuration, the input analog signal V _IN is smaller than the reference voltage _{e 14 (V IN <e 14} ), consider the case where the output comparator output is "L" AND gate A _L becomes "1" level Then, the output in this case is, as shown in FIG.

[0000] is one of the four types. Focusing on these four types of data, the data is such that the output of the AND gate A _U3 of the upper comparator is “1” level and the lower-side AND gate A _D1
This is the same as the data obtained when any one of .about.A _D4 is at the “1” level. Therefore, when the bottom of the AND gate A _L becomes "1" level, instead of activating the drive buffer of the lowermost switching block and the upper encoder 120, one upper switching block S ₃₁ to S ₃₇ and buffer _BU3 may be activated. This drive buffer of the AND gate A _L and the output of the AND gate A _U3 switching block and the upper encoder sums the lowermost corresponding be given to the switching block S ₃₁ to S ₃₇ and the buffer B _U3 and the output of the required It means that it is gone. That is, when V _IN <V ₂ (= e ₁₀ ), the switching blocks S _{31 to} S ₃₇ and the buffer _{BU 3} may be activated as in the present embodiment, and the input analog signal V
Since it is not necessary to compare the _IN and the reference voltage e _14, it becomes unnecessary even lowermost corresponding upper comparator.

The selection gate 150 is an AND gate A₁~
A_FourAnd output from the lower-order encoder 140.
Selection signal SEL₁And SEL_TwoUsing the
Mode and R mode output from encoder 120
Select one higher-level data from each higher-level data of
Agate OR₁, OR_TwoConversion code D via₁, D _Two
Output as

Specifically, one input terminal of AND gate A ₁ is connected to one line (upper side) of encoder line LN ₁₂₁ for generating L mode data of upper encoder 120, and the other input terminal is connected to the other input terminal. Lower encoder 14
It is connected to a select line LN ₁₄₂ for outputting a selection signal SEL ₁ 0. One input terminal of the AND gate A ₂ is connected to one line (upper side) of an encoder line LN ₁₂₂ for generating R mode data of the upper encoder 120, and the other input terminal is a selection signal SEL _{2 of the} lower encoder 140. Is output to the selection line LN ₁₄₃ that outputs The outputs of these AND gates A ₁ and A ₂ are 2
It is connected to each input terminal of the input gate OR _1.

One input terminal of the AND gate A ₃ is connected to the other line (lower side) of the encoder line LN ₁₂₁ for generating L mode data of the upper encoder 120, and the other input terminal is used to select the lower encoder 140. It is connected to a select line LN ₁₄₂ for outputting a signal SEL _1. One input terminal of the AND gate A ₄ is connected to the other line (lower side) of the encoder line LN ₁₂₂ for generating R mode data of the upper encoder 120, and the other input terminal is a selection signal SEL _{2 of the} lower encoder 140.
Is output to the selection line LN ₁₄₃ that outputs The outputs of these AND gates A ₃ and A ₄ are connected to respective input terminals of a two-input OR gate OR ₂ .

[0068] XOR gate EXO ₁ has lower data BD ₃ and the upper comparator 11 output from one line of the data lines LN _{14 1} of the lower encoder 140
2 and the output level of AND gate A _U2
In an exclusive OR operation of a signal obtained by inverting, and outputs the result as the lower order bit conversion code D _3. The exclusive OR gate EXO ₂ is connected to the data line L of the lower encoder 140.
Lower data BD ₄ output from the other line of N _{14 1}
And the output level of the AND gate A _U2 of the upper comparator 112 takes the exclusive OR of the inverted signal by an inverter 160, and outputs the result as the lower order bit conversion code D _4.

Next, the operation of the above configuration will be described. For example, if the sampling voltage V _s of the sampled analog signal is V _RB <V _S <V ₂ , the outputs of the comparators C _U1 and C _U2 of the upper comparators 111 and 112 all become “L”, and the AND gate A "0" from _U1 and A _U2 ,
A _U3 outputs a binary signal of “1”. As a result, the binary signal [001] is
Input to 0. In the upper encoder 120, [0] is applied to two columns of encoder lines [LN ₁₂₁ ] for generating L mode data by a so-called wired OR circuit.
0], the higher-order data of [01] is generated on two columns of encoder lines [LN ₁₂₂ ] for generating data for the R mode, and output to the selection gate 120.

[0070] In addition, sampling voltage V _s is V ₂ <V _S
<If V _1, comparator C _U1 upper comparator 111
Is "L", the comparator C _{U2 of the} upper comparator 112
Output becomes "H" of "0" from the AND gate A _U1 and A _U3 upper comparator 111, the AND gate A _U2 of the upper comparator 112 binary signal "1" is output, respectively. As a result, a binary signal [010] is input to the upper encoder 120. In the upper encoder 120, a so-called wired OR circuit is used.
Higher order data of [10] is generated in two columns of encoder lines [LN ₁₂₁ ] for generating L mode data, and higher order data of [01] is generated in two columns of encoder lines [LN ₁₂₂ ] for generating R mode data. And output to the selection gate 120.

[0071] In addition, sampling voltage V _s is V ₁ <V _S
If < _VRT , the comparator C _{U1 of the} upper comparator 111
Is “H”, the comparator C _{U2 of the} upper comparator 112
Is "L", and a binary signal of "1" is output from the AND gate A _U1 of the upper comparator 111 and "0" is output from the AND gates A _U2 and A _{U3 of the} upper comparator 112, respectively. As a result, the binary signal [100] is input to the upper encoder 120. In the upper encoder 120, a so-called wired OR circuit is used.
Higher order data of [10] is generated on two columns of encoder lines [LN ₁₂₁ ] for generating L mode data, and [11] is generated on two columns of encoder lines [LN ₁₂₂ ] of generating R mode data. And output to the selection gate 120.

In parallel with this, each AND gate A
Transistor Q of each switching block of the matrix circuit 100 connected to the control line binary output signal in the _{U (1, 2, 3)} is "1" _{(x 1, x 2, x} 3) ₃ is controlled to be turned on for each row, and fine quantization of the quantization level is executed.

For example, when only the output of AND gate A _U3 attains “1” level, switching blocks S _{31 to} S _31
37 transistor Q ₃ is turned on, the reference resistor R ₉ to R
Divided by the reference voltage ₁₆ e ₉ to e ₁₅ and the sampling voltage V _S is differentially amplified by the switching block S ₃₁ to S _37, it is compared by the low-order comparator 131-137. Similarly, when the output of the AND gate A _U2 is "1" level switch block S ₂₁ to S ₂₇ is activated
_{, A} differential amplification operation is performed, and the lower comparator 13
A comparison by 1 to 137 is performed.

As described above, the lower conversion code is the sampled voltage V _S on a row-by-row basis of the switching block.
Is compared with the reference voltage divided by the reference resistance element in the row, and binary signals corresponding to the comparison result are output from the AND gates A _{D1 to} A _D7 and A _{D8 of} the lower comparators 131 to 137. Become.

At this time, the upper two bits D₁, D_TwoConvert
Input analog signal V_INIs V_IN<V_TwoIn the lower 2
Bit D_Three, D_FourThe analog signal when converting_IN
<E ₁₂Or the upper 2 bits D₁, D_TwoConvert
When the analog signal is V _Two<V_IN<V₁In the lower two
D_Three, D_FourThe analog signal when converting₈<
V_INOr the upper 2 bits D₁, D_TwoConvert
When the analog signal is V₁<V_INWith lower 2 bits
D_Three, D_FourThe analog signal when converting_IN<E_Four
And the lower comparators 131-134
Gate A_D1~ A _D4From one of the AND gates
A “1” level signal is output to the lower encoder 140
The lower line encoder 140 selects the selection line LN
₁₄₂Becomes “1”. As a result, the selection signal SEL₁But
When the selection signal is input to the selection gate 150 at “1” level,
SEL_TwoIs input to the selection gate 150 at the “0” level.
You.

In the selection gate 150, the selection signal SEL₁
And only the "1" level
A₁And A_ThreeOnly activated. These andge
A₁And A_ThreeIs the license of the upper encoder 120.
LN ₁₂₁Upper side of L mode upper data generated in
And the lower bit data are supplied respectively.
You. Therefore, in the selection gate 150, in the L mode,
Each bit of the upper data is selected, and as a result,
To OR₁, OR_TwoUpper conversion code D via₁, D _TwoWhen
And output.

Specifically, when the sampling voltage V _s of the analog signal V _IN satisfies V _RB <V _S <V ₂ , the upper conversion code [D ₁ , D ₂ ] is

In [00], when V ₂ <V _S <V ₁ , the upper conversion code [D ₁ , D ₂ ] is [10],
When V ₁ <V _S <V _RT , the upper conversion code [D ₁ , D
₂ ] is output at [10].

In the lower encoder 140, the lower
AND gate A of comparator 131 _D1Output of "1"
Sometimes lower data BD_Three, BD_FourIs generated in [11]
And AND gate A of the lower comparator 132_D2Output
Is "1", the lower data BD_Three, BD_FourIs [1
0] of the lower comparator 133
A_D3Is "1", the lower data BD_Three, B
D_FourIs generated at [01] and the lower comparator 134
AND gate A_D4When the output of is “1”, the lower data
BD_Three, BD_FourBut

[00] and the data BD ₃
Is output to exclusive OR gate EXO ₁ and data BD
₄ is output to the exclusive OR gates EXO _2.

Exclusive OR gates EXO ₁ and EXO
₂ , when V _RB <V _S <V ₂ , V ₁ <V _S <V _RT ,
That is, the switching from the bottom of the matrix circuit 100 in the first row and the third row block S ₃₁ ~S _37, S ₁₁ ~
If the S ₁₇ is selected, the level of the lower data the output level of the low-order encoder 140 is inverted and outputted as a lower conversion code D _3, D ₄ since application direction of the reference voltage is a forward . On the other hand, V ₂ <V
_S <When V _1, that is, when the switching block S ₂₁ to S ₂₇ from the bottom of the matrix circuit 100 and the second row is selected, the lower data from that application direction of the reference voltage are opposite The level is held as the output level of the lower encoder 140 and the lower conversion codes D ₃ and D ₃
Output as ₄ .

The input analog signal V _IN for converting the upper two bits D ₁ and D ₂ is V _IN <V ₂ , and the analog signal for converting the lower two bits D ₃ and D ₄ is e ₁₂ <V
_In the case of _IN , or when the analog signal for converting the upper two bits D ₁ and D ₂ is V ₂ <V _IN <V ₁ and the lower two bits D ₃ and D ₄ are V _IN <e ₈ , or The analog signal for converting the upper two bits D ₁ and D ₂ is V ₁ <V _IN
And when the analog signal when converting the lower two bits D ₃ and D ₄ is e ₄ <V _IN , the lower comparator 13
When a signal of “1” level is output to the lower encoder 140 from one of the AND gates A _{D5 to} A _D7 and A _D8 , the selection line LN _{143 of the} lower encoder 140 is set to “1”. 1 ".
As a result, the selection signal SEL ₂ is input to the selection gate 150 at “1” level, and the selection signal SEL ₁ is input to the selection gate 150 at “0” level.

In the selection gate 150, the selection signal SEL_Two
And only the "1" level
A_TwoAnd A_FourOnly activated. These andge
A_TwoAnd A_FourIs the license of the upper encoder 120.
LN ₁₂₂Upper side of R mode upper data generated in
And the lower bit data are supplied respectively.
You. Therefore, in the selection gate 150, in the R mode,
Each bit of the upper data is selected, and as a result,
To OR₁, OR_TwoUpper conversion code D via₁, D _TwoWhen
And output.

[0082] Specifically, the upper conversion code when the sampling voltage V _s of the analog signal V _IN is V _RB <V _S <V ₂ [D _1, D _2] in [01], V ₂ <V _S < Top conversion code when the V ₁ [D _1, D _2] in [01],
When V ₁ <V _S <V _RT , the upper conversion code [D ₁ , D
₂ ] is output at [11].

Further, in the lower encoder 140, the lower
AND gate A of comparator 135 _D5Output of "1"
Sometimes lower data BD_Three, BD_FourIs generated in [11]
And the lower gate 136 of the lower comparator 136_D6Output
Is "1", the lower data BD_Three, BD_FourIs [1
0] of the lower comparator 137
A_D7Is "1", the lower data BD_Three, B
D_FourIs generated at [01] and AND gate A_D8Output
When "1", lower data BD_Three, BD_FourBut

[00]
, And the data BD ₃ is output from the exclusive OR gate EX.
Is output to the O _1, data BD ₄ exclusive OR gates E
It is output to the XO _2.

Exclusive OR gate EXO₁And EXO
_TwoThen, V_RB<V_S<V_TwoAnd V ₁<V_S<V_RTNoto
That is, the first row from the bottom of the matrix circuit 100
And the switching block S in the third row₃₁~ S₃₇, S
₁₁~ S₁₇When is selected, the direction of application of the reference voltage is
Since it is forward direction, the level of lower data is lower encoder.
The output level of the encoder 140 is inverted and the lower conversion code
D_Three, D_FourIs output as On the other hand, V_Two<V
_S<V₁, That is, below the matrix circuit 100
From the switching block S in the second row_{twenty one}~ S₂₇Is selected
The reference voltage is applied in the opposite direction.
And the level of the lower data is output from the lower encoder 140.
Held at the power level and the lower conversion code D_Three, D
_FourIs output as

As described above, according to the present embodiment,
A signal SE for selecting L mode data and R mode data from lower encoder 140 that divides the lower code into two groups and obtains the converted code of this group.
L ₁ and SEL ₂ are output and the upper encoder 120 is output.
The L-mode data and the R-mode data output from are selected to obtain the upper conversion codes D ₁ and D ₂ , so that the selection signal can be directly transmitted without using an inverting gate or a prohibition gate unlike a conventional circuit. It can be used to select higher data. Therefore, the selection gate 1 of the selection signal
No and child delay for the output input of the upper encoder 120 to 50, thereby the speed of the conversion process.

Further, in addition to eliminating the necessity of an inversion gate and a prohibition gate, the number of selection signals can be reduced to two, and the number of upper codes to be selected and the number of input gates of the selection gate can also be reduced to two. Further, the upper comparator for the uppermost row of the matrix circuit 100 is also used as the upper comparator 111 for detecting a change in data between the third row and the second row, and the upper comparator for the lowermost row is used for the second row and the second row. Upper comparator 1 that detects a change in data between the first row
12, the number of higher-order comparators and the number of switching block rows, which conventionally required (2 ^a -1) and 2 ^a rows, are reduced to (2 ^a -2) and (2 ^a -1).
^a- 1) The number of rows can be reduced. Therefore, there is an advantage that an A / D conversion circuit capable of reducing the chip area and the power consumption can be realized.

FIG. 4 is a circuit diagram of an A / D conversion circuit according to the present invention.
FIG. 9 is a circuit diagram showing a second embodiment. The present embodiment is the
The difference from the first embodiment is that the lower encoder 120 is selected.
LN line₁₄₂And the selection signal is SEL₁
Is generated, and the selection signal SEL is generated.₁The inverter
The signal whose level has been inverted at 170 is the selection signal SEL. _TwoNiyo
As an alternative signal, the AND gate A of the selection gate 150_Two
And A_FourTo supply the other input of
It is in.

According to the second embodiment, in addition to the effects of the first embodiment, a simple configuration can be realized, and the chip area can be further reduced.

In the first and second embodiments, the A / D conversion circuit corresponding to 4 bits has been described as an example.
Further, it goes without saying that the present invention can be applied to an A / D conversion circuit corresponding to multiple bits.

In the first and second embodiments described above, the upper encoder 120 and the lower encoder 140
The other output pin buffers B _{U1 to} B _U3 and B _D1 to
A configuration has been shown that placing the B _D8, these other output pins buffer _{B U1 ~B U3, B D1 ~B} D8 , the upper encoder 120
The lower encoder 140 is provided to reliably drive the lower encoder 140 and does not need to be provided depending on the capacity of the upper encoder 120 and the lower encoder 140, which are so-called loads.

[0091]

As described above, according to the present invention,
The inversion gate and the inhibition gate, which are conventionally required, are not required, and the conversion processing can be sped up. Further, in addition to eliminating the necessity of an inversion gate and a prohibition gate, the number of selection signals can be reduced, the number of high-order codes to be selected and the number of input gates of the selection gate can be reduced. Since the number and the number of switching block rows can be reduced, there is an advantage that the chip area and power consumption can be reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of an A / D conversion circuit according to the present invention.

FIG. 2 is a diagram showing the correspondence between the output of each AND gate of a high-order comparator of the circuit of FIG. 1 and the output data of each encoder of a high-order encoder.

FIG. 3 is a diagram showing a correspondence relationship between outputs of AND gates of lower and upper comparators of the circuit of FIG. 1 and output conversion codes;

FIG. 4 is a circuit diagram showing a second embodiment of the A / D conversion circuit according to the present invention.

FIG. 5 is a circuit diagram illustrating a configuration example of a conventional A / D conversion circuit.

FIG. 6 is a diagram showing an upper conversion code pattern of the circuit of FIG. 5;

FIG. 7 is a diagram showing a lower conversion code pattern of the circuit of FIG. 5;

FIG. 8 is a diagram illustrating a relationship between quantization levels of an A / D conversion circuit.

[Explanation of symbols]

100 Matrix circuits 111 and 112 Upper comparators A _{U1 to} A _U3 Upper AND gate 120 Upper encoder LN ₁₂₁ L mode line LN ₁₂₂ R mode line 131 to 137 Lower comparators A _{D1 to} A _D8 lower aND gate 140 ... lower encoder LN ₁₄₁ ... data line LN _142, LN ₁₄₃ ... selection line 150 ... select gates A ₁ to A ₄ ... aND gates 160 ... inverter 170 ... inverter R ₁ to R ₁₆ ... reference resistance element OR ₁ , OR ₂ ... OR gate EXO ₁ , EXO ₂ ... Exclusive OR gate

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-1-190029 (JP, A) JP-A-2-123829 (JP, A) JP-A-2-125530 (JP, A) JP-A-2-125 126725 (JP, A) JP-A-2-128524 (JP, A) JP-A-2-141028 (JP, A) JP-A-2-132920 (JP, A) JP-A-2-137420 (JP, A) JP-A-2-202224 (JP, A) JP-A-4-196923 (JP, A) JP-A-63-299615 (JP, A) JP-A-2-77931 (JP, U) (58) Fields investigated (Int.Cl. ⁷ , DB name) H03M 1/00-1/88

Claims (7)

(57) [Claims] 1. A plurality of reference resistance elements connected in series between two reference potentials, arranged in a matrix and activated for each row by a higher-order conversion output signal. compared the reference voltage was pressurized and the object to be converted input signal, a plurality of switching blocks for detecting the presence or absence of the lower bit data and redundant bit data, the 1/2 offset
Multiple reference voltages derived for determining the high-order bit taken
Point, high reference voltage point (VRT) and low reference voltage point (VR
B) sandwiched between two adjacent points
The divided voltage and the redundant divided voltage extended to both sides thereof are 1
Multiple switching blocks received in a row
Lock and a voltage step corresponding to the resolution of the number of high-order bits generated between adjacent rows, excluding at least the top row or the bottom row of the switching block matrix. Comparing at least one data change point detection circuit for detecting a data change point, and converting conversion codes of adjacent upper bits according to two modes set in advance according to the detection result of the data change point detection circuit. A high-order encoder to be obtained, and a column-based output of each switching block is divided into two groups corresponding to the two modes, and a predetermined lower-order conversion code is provided for each divided group according to the presence or absence of lower bit data and redundant bit data. And each switch
Input voltage from the output of the
Are two reference signals corresponding to the two upper bit conversion codes.
A lower encoder that detects which of the pressure ranges belongs to, and generates a selection signal for selecting the conversion code to which the higher encoder belongs from the two upper bit conversion codes; A selection gate for selectively outputting one of the two high-order bit conversion codes output from the encoder based on the selection signal output from the low-order encoder. Analog / digital conversion circuit. 2. The resistance element according to claim 1, wherein said reference resistance element is folded back over a predetermined number of rows so as to correspond to a matrix arrangement of said switching blocks, and generates a reference voltage having a maximum value. And the row of the resistor element that generates the lowest reference voltage are arranged with a predetermined period shifted with respect to the rows of the other resistor elements, and the output conversion code value of the higher-order encoder is the reference voltage level of each row. 2. The analog / digital conversion circuit according to claim 1, wherein the setting is made in accordance with the transition direction. 3. The analog / digital conversion circuit according to claim 2, wherein said predetermined period is a half period. 4. A switching block array arranged in a matrix is divided into two column groups based on a predetermined column, and these column group outputs are configured to correspond to the two groups of the lower encoder. 4. The analog / digital conversion circuit according to claim 1, wherein the output conversion code value of the upper encoder is set to have a difference in magnitude in the order of one mode and the other mode. 5. The analog / digital conversion circuit according to claim 1, wherein said two groups are divided based on a switching point of an upper bit in an output conversion code. 6. The analog / digital converter according to claim 1, wherein said lower encoder is configured to generate two selection signals corresponding to two division groups.
Digital conversion circuit. 7. The analog according to claim 1, wherein the lower encoder is configured to generate one selection signal according to one of two divided groups. / Digital conversion circuit.