JPS62263719A - Ad converter - Google Patents

Abstract

PURPOSE:To obtain an A/B converter with high accuracy at a high speed by adjusting the gain of an amplifier in the blanking period of a video signal twice while including the gain of a sample-and-hold circuit, keeping the gain of each amplifier constant at a period till the next blanking so as to apply pipeline processing. CONSTITUTION:Various pulses are formed by a blanking pulse shaping circuit 27 based on a blanking pulse from a terminal 6 when the blanking period of a picture signal comes, a switch 24 is connected to a ground potential and the electric charge in a capacitor 22 is discharged because a switch 25 is closed tentatively. A comparator 23 keeps closing a switch 26 when an output of an amplifier 1 is larger than a full scale voltage (VFS) to charge up the capacitor 22 via a resistor 28 from a bias power supply 29. As the voltage rises, a MOS TR is going to be turned on, an output voltage of the amplifier 1 is lowered and smaller than the voltage VFS. The output of the comaprator 23 is inverted momentarily to turn off the switch 26 and since the output is VFS with respect to the input of the votlage difference of VFS/2, the gain of the amplifier is kept just twice.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a high-precision, high-speed, low-power AD converter, and more particularly to a structure that improves the conversion speed and conversion accuracy of a cascaded AD converter.

Conventional technology A parallel type is excellent as a high-speed AD converter. In this method, for an n-bit AD converter, 2n-1 comparators are prepared, a reference voltage to be compared is applied to these, and this reference voltage is compared with the input voltage. It detects the level. Although this method can increase the conversion speed, it has the disadvantage that it requires a large number of comparators, which increases the number of elements, and that the power consumption increases in proportion to the number of elements. On the other hand, there is a cascade type method that reduces the number of elements and reduces the power consumption [for example, 1983 IEEE I
international 5olid-3tateC
circuitsConference Diges+t
(Aiiiii International Rid State Circuit Conference Digest)'
P178:] This method uses an amplifier i with double the gain.
The number of bits of the AD converter is connected in series, and this amplifier successively compares the differences between the three full-scale voltages and the input signal voltage, determines the magnitude, and outputs each bit in sequence. It's something you get.

Problems to be Solved by the Invention This method requires only the same number of amplifiers and comparators as the number of pits, but unless the gain of the amplifier is doubled with an accuracy of less than the bit precision of the AD converter, conversion errors will accumulate. and the correct conversion will not be obtained. Further, even if the gain of the amplifier is set accurately by trimming or the like, there is a possibility that the source of error becomes large due to changes in ambient temperature, changes over time, etc. Furthermore, cascade type AD
The converter has the disadvantage that the conversion speed is slower than a parallel type because the amplifiers are connected in multiple stages.

Means for Solving the Problems The present invention provides an AD converter for converting an analog video signal or the like into a digital signal, in which a plurality of sample and hold circuits and an amplifier are connected in series. means for comparing the output with a reference voltage and outputting a digital signal, and adjusting the gain of the amplifier to double including the gain of the sample and hold circuit within the blanking period of the video signal, and adjusting the gain of the amplifier to twice the gain of the amplifier until the next blanking. This AD converter is characterized by maintaining the gain of each amplifier constant during a period and performing pipeline processing.

According to the present invention, the gain of the amplifier, which is a major cause of conversion errors in the AD converter, is calibrated using the blanking period of the video signal, so that correct conversion is always performed. Since calibration is performed including errors in the sample and hold circuits at each stage, errors do not accumulate even if a plurality of sample and hold circuits are used.

- Since power conversion is processed bit by bit in a pipeline manner in synchronization with the clock, the conversion speed can be increased by a factor of two times the number of bits while maintaining the response speed of the amplifier. Furthermore, since the calibration is performed during the blanking period when no conversion is necessary, the conversion time does not become longer due to the calibration.

Furthermore, since calibration is performed at short intervals, changes in ambient temperature can be quickly dealt with, and changes over time can also be calibrated.

Embodiment FIG. 1 shows a block diagram of a cascade type AD converter of the present invention. As an example, a 10 bit AD converter will be explained. 1-1 to 1-9 are high gain amplifiers, 2--1 to 2
-10 is a comparator, 3-1 to 3-9 are sample and hold circuits, and 4-1 to 4-9 are feedback resistors for the amplifiers 1-1 to 1-9, which control the gains of the amplifiers. 6-1 to 6-9
is a control circuit that controls the values of variable resistors 4-1 to 4-9, 6 is a blanking pulse input terminal, 7 is an image signal input terminal, and 8 is a full scale voltage (VFS) that determines the dynamic range of the AD converter. )=input terminal, 9 is the input terminal of full scale voltage (vFs/2).

Next, the operation of the AD converter of the present invention will be explained. First, it is assumed that the state of the converter is in a cycle that allows conversion. terminal 7
The analog image signal inputted from is sampled by the sample and hold circuit 3-1, and the value at that time is held until the conversion is completed.

This output is compared with the full-scale voltage of H in the comparator 2-1, and if it is larger than this, 1 is output to the MSB.

On the other hand, the output of the sample-and-hold circuit 3-1 is input to the amplifier 1-1 whose gain is adjusted to 2 with 10-bit accuracy, and twice the difference from the voltage of 1Fs/2 is output. This difference output 2 (v, n-vFs/2) is input to the sample-and-hold circuit 3-2 and held for the next conversion period. This difference output is input to the comparator 2-2 during this time, and v
It is compared with the Fs/2 voltage, and if it is larger, 1 is output as the 2nd bit output.

On the other hand, the sample and hold circuit 3-1 contains the next video signal, and at the same time the 2nd bit is converted, the MS of the next data is
B is converted. In addition, the output 2 (vin-vFs/ri) of the sample and hold circuit 3-2 is input to the amplifier 1-2,
Similarly, it is held in the sample hold circuit 3-3 and used for converting the third bit. For the following time, change to H1 and 1
It is converted bit by bit according to the sampling period up to the 0th bit.

Therefore, if the data from the MSB to 9 bits is latched until the LSB data is output, this data becomes the digital signal of the analog image input signal.

It takes 10 sample periods from the initial input to the output of the digital signal, but after that the converted data is output continuously. Therefore, one comparator 2 or amplifier 1 only needs to be able to convert one bit of data during one sample period, so that the conversion speed can be increased.

What is important here is that in order to reduce the conversion error to 10 pits or less, the gains of amplifiers 1-1 to 1-9 must be exactly doubled with 10-bit accuracy. The accuracy of the sample and hold circuits inserted between each stage must also be within this accuracy. The gain adjustment method of this amplifier, which is the key point of the present invention, will be described below. Gain adjustment is performed during the blanking period of the image signal. Since the adjustment method is the same for each amplifier, one sample-and-hold circuit amplifier will be described based on FIG.

Items equivalent to those in Figure 1 are given the same numbers. The dotted line 4 is a variable resistor (MOS in this example) transistor 21 and capacitor 2.
Consists of 2. The dotted line 6 is a circuit for controlling the variable resistor, which consists of a comparator 23, a switch 24°26.26, a blanking pulse shaping circuit 27, a resistor 28 for supplying the entire arbitrary current, and a bias power supply 29 (VB).

During the blanking period of the image signal, the blanking pulse shaping circuit 2 uses the blanking pulse from the terminal 6.
7 generates various pulses, and first the switch 24 is connected to ground potential. Furthermore, the charge in the capacitor 22 is discharged by temporarily closing the switch 25. After that, the sample and hold circuit 3 holds the ground voltage. In this state M
Since the value of OS resistor 21 is large, the output of amplifier 1 is vFs
will be a larger value. Here, the comparator 23 compares the output of the amplifier 1 with vFs, and keeps the switch 26 closed while the output of the amplifier 1 is greater than vFs, and bias power supply 2
9, a current flows through the resistor 28 and charges the capacitor 22. As the voltage of the capacitor 22, that is, the gate voltage of the MOS transistor 21 increases, the MOS transistor begins to turn on and its resistance decreases. Accordingly, the output voltage of amplifier 1 decreases and becomes smaller than vFs. At this moment, the output of the comparator 23 is inverted and the switch 26 is turned off. The gate of the MOS transistor 21 is opened, and the gate voltage is kept constant for a certain period of time. The output is vF for an input with a voltage difference of V F 3 /2.
Since s, the gain of the amplifier remains exactly twice. It is necessary to increase the capacity so that the double gain can be maintained with 10-bit precision at least until the next blanking period. Furthermore, since this gain adjustment includes errors in the sample and hold circuits, variations in characteristics of the many sample and hold circuits used are also corrected.

Through the above operations, the gain of the amplifier 1 is adjusted to double.

In addition to the effects of the invention, the cascade type A/D converter of the present invention utilizes the properties of images, achieves high precision and low power consumption with a small number of elements, and achieves a high-speed A/D converter due to pipeline processing. The structure is suitable for semiconductor integrated circuits.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the cascade type A/D converter of the present invention, and FIG. 2 is a more specific circuit for explaining the amplifier gain and adjustment method, which is the key point of the present invention. FIG. 1...Amplifier, 2...Comparator, 3...
...Sample hold circuit, 4...Variable resistor, 6...Variable resistance control circuit.

Claims (1)

[Claims] A cascade type AD converter in which amplifiers that output a difference between an input signal and a reference voltage are connected in cascade in multiple stages, and output a digital signal by comparing the output of each of the amplifiers with the reference voltage, the amplifier being connected between each of the amplifiers. and a variable feedback resistor and a gain control circuit for each of the amplifiers, and the gain of the amplifier is doubled, including the gain of the sample and hold circuit, within a blanking period of the input image signal. Adjust,
An AD characterized in that the gain of each of the amplifiers is kept constant until the next blanking, and pipeline processing is performed.
converter.