KR20150072972A - Analog to Digital Converter for interpolation using Calibration of Clock - Google Patents
Analog to Digital Converter for interpolation using Calibration of Clock Download PDFInfo
- Publication number
- KR20150072972A KR20150072972A KR1020130160711A KR20130160711A KR20150072972A KR 20150072972 A KR20150072972 A KR 20150072972A KR 1020130160711 A KR1020130160711 A KR 1020130160711A KR 20130160711 A KR20130160711 A KR 20130160711A KR 20150072972 A KR20150072972 A KR 20150072972A
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- South Korea
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- latch
- output
- clock
- differential
- input
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/002—Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/10—Calibration or testing
- H03M1/1009—Calibration
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/20—Increasing resolution using an n bit system to obtain n + m bits
- H03M1/202—Increasing resolution using an n bit system to obtain n + m bits by interpolation
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Analogue/Digital Conversion (AREA)
Abstract
Description
This embodiment relates to a method and apparatus for converting an analog signal to a digital signal for interpolation using the calibration of a clock.
It should be noted that the following description merely provides background information related to the present embodiment and does not constitute the prior art.
An analog to digital converter is an apparatus that converts an analog signal into a digital signal and receives the signals of temperature, pressure, voice, image, voltage and the like continuously measured and digitizes it.
To date, various types of ADCs have been proposed. For example, a flash ADC, a pipeline ADC, and a successive approximation register ADC (SAR ADC) have been proposed, and they are used in applications suited to their respective characteristics. Flash ADCs operate relatively fast, but they have the disadvantage that their area increases rapidly with accuracy. Pipelined ADCs support fast operation characteristics and high precision, but each stage has the disadvantage of power consumption due to the use of amplifiers. A successive approximation ADC has a drawback that it has a low power consumption rate of the circuit and a simple circuit configuration but operates relatively slowly.
Another example of an analog-to-digital converter is an ADC that uses an interpolation technique to reduce the number of exponentially increasing comparators as the number of digital output bits increases. By applying this interpolation technique, the same precision as the flash ADC described above can be realized while reducing the number of comparators. However, since the static current flows in the comparator, the power consumption is still high even if the number of comparators is reduced.
One of the ADCs designed to solve this problem is a comparator using a latch capable of using a dynamic current. Each latch outputs two voltage differences as an output value according to the input voltage at the time when the clock is turned on, which is a problem in inputting the clock signal at the correct timing.
The present embodiment has a main purpose in interpolating an SR latch by inputting a clock signal at an accurate timing in an analog-to-digital converter.
According to an aspect of the present invention, there is provided a semiconductor memory device including a plurality of first latches, each of the first latches receiving an analog input voltage corresponding to the analog signal and each reference voltage and amplifying two voltage differences according to the first clock, A first latch stage outputting a first differential (+) output and a first differential (-) output; (+) And (-) input terminals of the differential output of one first latch and amplifies two voltage differences according to the second clock to output a second differential (+) output and a second differential output -) output of the first latch and a first differential (-) output of the adjacent first latch receiving a low reference voltage adjacent to the reference voltage of the first latch and a first differential (- And a second latch that receives the outputs of the first and second differential amplifiers and outputs a second differential (+) output and a negative (-) output by amplifying the two voltage differences according to the second clock, only; (-) output value of any one of the second latches and a (+) output value of the adjacent lower second latch of any one of the second latches to generate an interpolation output of a High signal or a Low signal A third SR latch terminal; And when the analog input voltage corresponding to the third SR latch is input to the first latch, receiving the output of the third SR latch, and when the output is the Low signal, And a second clock adjusting circuit for adjusting the delay time of the second clock to be longer than the first clock when the delay time of the output signal is the High signal.
As described above, according to the present embodiment, the present embodiment has the effect of interpolating the SR latch by inputting the clock signal at the correct time in the analog-to-digital converter.
In this embodiment, adding a plurality of SR latches reduces the number of latches in the front end, thereby achieving high precision while reducing power consumption.
1 is a diagram illustrating an analog-
2A shows the output characteristics of the latch when the difference between the analog input voltage Vin and the reference voltage V1 is smaller than the difference between the analog input voltage Vin and the reference voltage V2.
2B is a diagram showing the output characteristics of the latch when the difference between the analog input voltage Vin and the reference voltage V1 is larger than the difference between the analog input voltage Vin and the reference voltage V2.
3A is a diagram of a multi-stage latch interpolation apparatus.
3B shows the operation of the third
FIGS. 4 and 5 are views showing a driving method of the third
6 is an overall configuration diagram of a circuit for generating the
FIG. 7 is a diagram illustrating an appropriate timing for inputting the
8A is a detailed second
8B shows the values of the pulses Q1, Q2, and Q3 generated in a separate logic circuit (not shown) to drive the
FIG. 8C shows the adjustment of the second clock according to the detailed second
Hereinafter, the present embodiment will be described in detail with reference to the accompanying drawings. It should be noted that, in adding reference numerals to the constituent elements of the drawings, the same constituent elements are denoted by the same reference numerals even though they are shown in different drawings. In the following description of the present invention, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.
In describing the components of the present invention, terms such as first, second, A, B, (a), and (b) may be used. These terms are intended to distinguish the constituent elements from other constituent elements, and the terms do not limit the nature, order or order of the constituent elements. When a component is described as being "connected", "coupled", or "connected" to another component, the component may be directly connected to or connected to the other component, It should be understood that an element may be "connected," "coupled," or "connected."
1 is a diagram illustrating an analog-
The analog
1, only the part (a) of the analog-to-
The reference
The
The
The first differential output signal pairs {(A1 + , A1 - ), (A2 + , A2 - )} of the
2A shows the output characteristics of the latch when the difference between the analog input voltage Vin and the reference voltage V1 is smaller than the difference between the analog input voltage Vin and the reference voltage V2.
Referring to FIG. 2A, the
2B is a diagram showing the output characteristics of the latch when the difference between the analog input voltage Vin and the reference voltage V1 is larger than the difference between the analog input voltage Vin and the reference voltage V2.
2B shows an example in which the magnitude of the analog input voltage Vin is between V1 and V2 and the difference between the analog input voltage Vin and the reference voltage V1 is between the analog input voltage Vin and the reference voltage V2 The differential output signal pairs {(A1 + , A1 - ), (A2 + , A2 - )} of the
In general, the latch can not apply the interpolation method to the output of the steady state. However, interpolation is possible in a specific time interval (T1) by using a characteristic in which the time required for the latch to generate the output in the normal state is proportional to the voltage difference of the signal input to the (+) and (-) input terminals.
3A is a diagram of a multi-stage latch interpolation apparatus.
3A, the multi-stage latch interpolation apparatus includes a
The reference
The
First latch stage 320 A plurality of
The
The first differential output signal pair {(A1 + , A1 - ), (A2 + , A2 - )} of the
The third
3B shows the operation of the third
The third
Referring to FIG. 3A, the third
FIGS. 4 and 5 are views showing a driving method of the third
4 and 5, the V axis means a voltage axis in which the position in the vertical direction has a value corresponding to the corresponding threshold level.
4, when the difference between the threshold level and the input level, which is the magnitude of the input voltage at which the output level of the second latch changes, is greater than the difference between the threshold level and the input level of the adjacent second latch, The output level is output faster than the output level of the adjacent second latch if the difference between the threshold level of the second latch and the input level is smaller than the difference between the threshold level of the adjacent second latch and the input level do.
4, when the input level of the analog-to-
4, the negative (-) output of the
the output value '1' of the (+) output terminal of the
The third
Third
5, when the input level of the analog-to-
The (+) output value of the
the (-) output value of the
Third
Third
6 is an overall configuration diagram of a circuit for generating the
The analog-to-
6, the overall configuration of the circuit for generating the
The first latch stage includes a plurality of first latches, each of the first latches receives an analog input voltage corresponding to an analog signal and each reference voltage, amplifies two voltage differences according to the first clock to generate a first differential (+ ) Output and a first differential (-) output. The second latch stage includes a plurality of second latches. The differential outputs of one first latch are input to the (+) and (-) input terminals, respectively, and the two differential voltages are amplified according to the second clock to generate a second differential (-) output of one of the first latches and a first differential (-) output of one of the adjacent first latches receiving a low reference voltage adjacent to the reference voltage of the first latch And a second latch for receiving a first differential (+) output to the (+) and (-) terminals and outputting a second differential (+) output and a (-) output by amplifying two voltage differences according to the second clock do. The third SR latch stage receives the (-) output value of any one of the second latches and the (+) output value of the adjacent lower second latch of any one of the second latches to generate an interpolation output of a High signal or a
The
The
6, the input voltage 611 corresponding to the threshold level of the third
FIG. 7 is a diagram illustrating an appropriate timing for inputting the
7, the difference between the first differential (-) output (A1 - ) and the first differential (+) output A1 + of the
8A is a detailed second
The second
8B shows the values of the pulses Q1, Q2, and Q3 generated in a separate logic circuit (not shown) to drive the
FIG. 8C shows the adjustment of the second clock according to the detailed second
8, the output of the third SR latch of the third
The
8A, when the
When the
The overall operation of the
6, when the input voltage Vin corresponding to the threshold level of the
When the
When the
In accordance with the above process, the
The delay time of the
The foregoing description is merely illustrative of the technical idea of the present embodiment, and various modifications and changes may be made to those skilled in the art without departing from the essential characteristics of the embodiments. Therefore, the present embodiments are to be construed as illustrative rather than restrictive, and the scope of the technical idea of the present embodiment is not limited by these embodiments. The scope of protection of the present embodiment should be construed according to the following claims, and all technical ideas within the scope of equivalents thereof should be construed as being included in the scope of the present invention.
110: Reference voltage generator 120:
130: second latch array 310: reference voltage generator
320: first latching stage 330: second latching stage
360: third SR latch stage 810: charge pump
Claims (3)
The first latch includes a plurality of first latches, each of the first latches receives an analog input voltage corresponding to the analog signal and each reference voltage, amplifies two voltage differences according to the first clock to generate a first differential (+ A first latch stage for outputting a first differential (-) output;
(+) And (-) input terminals of the differential output of one first latch and amplifies two voltage differences according to the second clock to output a second differential (+) output and a second differential output -) output of the first latch and a first differential (-) output of the adjacent first latch receiving a low reference voltage adjacent to the reference voltage of the first latch and a first differential (- And a second latch that receives the outputs of the first and second differential amplifiers and outputs a second differential (+) output and a negative (-) output by amplifying the two voltage differences according to the second clock, only;
(-) output value of any one of the second latches and a (+) output value of the adjacent lower second latch of any one of the second latches to generate an interpolation output of a High signal or a Low signal A third SR latch terminal; And
When the analog input voltage corresponding to the third SR latch is input to the first latch, the output of the third SR latch is received, and when the output is the Low signal, And adjusting a delay time of the second clock to be longer than a delay time of the first clock when the delay time is shorter and the output is the High signal,
/ RTI >
Wherein the first latch stage, the second latch stage, and the third latch stage are configured separately from the analog-to-digital converter and have the same configuration and wiring configuration as some of the components of the analog-to- Clock calibration device.
And provides the second clock generated by the second clock adjustment circuit to the analog-to-digital converter.
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KR1020130160711A KR20150072972A (en) | 2013-12-20 | 2013-12-20 | Analog to Digital Converter for interpolation using Calibration of Clock |
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
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CN106357268A (en) * | 2016-09-29 | 2017-01-25 | 珠海格力电器股份有限公司 | Comparator delay correction circuit in ADC (analog to digital converter), method and ADC |
US20230179188A1 (en) * | 2021-12-03 | 2023-06-08 | Nanya Technology Corporation | Data receiving circuit |
US11770117B2 (en) | 2021-12-07 | 2023-09-26 | Nanya Technology Corporation | Data receiving circuit |
-
2013
- 2013-12-20 KR KR1020130160711A patent/KR20150072972A/en not_active Application Discontinuation
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
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CN106357268A (en) * | 2016-09-29 | 2017-01-25 | 珠海格力电器股份有限公司 | Comparator delay correction circuit in ADC (analog to digital converter), method and ADC |
CN106357268B (en) * | 2016-09-29 | 2019-08-23 | 珠海格力电器股份有限公司 | Comparator delay correction circuit, method and ADC in a kind of ADC |
US20230179188A1 (en) * | 2021-12-03 | 2023-06-08 | Nanya Technology Corporation | Data receiving circuit |
US11728794B2 (en) * | 2021-12-03 | 2023-08-15 | Nanya Technology Corporation | Data receiving circuit |
US11770117B2 (en) | 2021-12-07 | 2023-09-26 | Nanya Technology Corporation | Data receiving circuit |
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