KR20150072972A - Analog to Digital Converter for interpolation using Calibration of Clock - Google Patents

Analog to Digital Converter for interpolation using Calibration of Clock Download PDF

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KR20150072972A
KR20150072972A KR1020130160711A KR20130160711A KR20150072972A KR 20150072972 A KR20150072972 A KR 20150072972A KR 1020130160711 A KR1020130160711 A KR 1020130160711A KR 20130160711 A KR20130160711 A KR 20130160711A KR 20150072972 A KR20150072972 A KR 20150072972A
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South Korea
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latch
output
clock
differential
input
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KR1020130160711A
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Korean (ko)
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류승탁
김종인
민기정
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한국과학기술원
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Publication of KR20150072972A publication Critical patent/KR20150072972A/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/002—Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/10—Calibration or testing
    • H03M1/1009—Calibration
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/20—Increasing resolution using an n bit system to obtain n + m bits
    • H03M1/202—Increasing resolution using an n bit system to obtain n + m bits by interpolation

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  • Theoretical Computer Science (AREA)
  • Analogue/Digital Conversion (AREA)

Abstract

Provided is a clock calibration device comprising: a first latch end having a plurality of first latches, receiving an analog input voltage corresponding to an analog signal and a standard voltage, amplifying a different between the voltages according to a first clock, and outputting a first differential (+) output and a first differential (-) output; a second latch end having a plurality of second latches and including a second latch receiving differential outputs of a first latch through (+) and (-) input ends and outputting a second differential (+) output and a (-) output by amplifying a difference between the voltages according to a second clock, and also including a second latch receiving a first differential (-) output of a first latch and a first differential (+) output of an adjacent first latch receiving a lower standard voltage adjacent to a standard voltage of the first voltage respectively through (+) and (-) ends and outputting a second (+) output and a (-) output by amplifying a different between the voltages according to a second clock; a third SR latch end including a third SR latch receiving a (-) output value of a second latch and a (+) output value of a lower second latch adjacent to the second latch and generating an interpolation output of a high signal or a low signal; and a second clock adjusting circuit unit receiving an output of the third SR latch when an analog input voltage corresponding to the third SR latch is inputted to the first latch, wherein delay time of the second clock become shorter compared to the first clock when the output is the low signal, and delay time of the second clock becomes longer compared to the first clock when the output is the high signal.

Description

{Analog to Digital Converter for Interpolation using Timing Calibration}

This embodiment relates to a method and apparatus for converting an analog signal to a digital signal for interpolation using the calibration of a clock.

It should be noted that the following description merely provides background information related to the present embodiment and does not constitute the prior art.

An analog to digital converter is an apparatus that converts an analog signal into a digital signal and receives the signals of temperature, pressure, voice, image, voltage and the like continuously measured and digitizes it.

To date, various types of ADCs have been proposed. For example, a flash ADC, a pipeline ADC, and a successive approximation register ADC (SAR ADC) have been proposed, and they are used in applications suited to their respective characteristics. Flash ADCs operate relatively fast, but they have the disadvantage that their area increases rapidly with accuracy. Pipelined ADCs support fast operation characteristics and high precision, but each stage has the disadvantage of power consumption due to the use of amplifiers. A successive approximation ADC has a drawback that it has a low power consumption rate of the circuit and a simple circuit configuration but operates relatively slowly.

Another example of an analog-to-digital converter is an ADC that uses an interpolation technique to reduce the number of exponentially increasing comparators as the number of digital output bits increases. By applying this interpolation technique, the same precision as the flash ADC described above can be realized while reducing the number of comparators. However, since the static current flows in the comparator, the power consumption is still high even if the number of comparators is reduced.

One of the ADCs designed to solve this problem is a comparator using a latch capable of using a dynamic current. Each latch outputs two voltage differences as an output value according to the input voltage at the time when the clock is turned on, which is a problem in inputting the clock signal at the correct timing.

The present embodiment has a main purpose in interpolating an SR latch by inputting a clock signal at an accurate timing in an analog-to-digital converter.

According to an aspect of the present invention, there is provided a semiconductor memory device including a plurality of first latches, each of the first latches receiving an analog input voltage corresponding to the analog signal and each reference voltage and amplifying two voltage differences according to the first clock, A first latch stage outputting a first differential (+) output and a first differential (-) output; (+) And (-) input terminals of the differential output of one first latch and amplifies two voltage differences according to the second clock to output a second differential (+) output and a second differential output -) output of the first latch and a first differential (-) output of the adjacent first latch receiving a low reference voltage adjacent to the reference voltage of the first latch and a first differential (- And a second latch that receives the outputs of the first and second differential amplifiers and outputs a second differential (+) output and a negative (-) output by amplifying the two voltage differences according to the second clock, only; (-) output value of any one of the second latches and a (+) output value of the adjacent lower second latch of any one of the second latches to generate an interpolation output of a High signal or a Low signal A third SR latch terminal; And when the analog input voltage corresponding to the third SR latch is input to the first latch, receiving the output of the third SR latch, and when the output is the Low signal, And a second clock adjusting circuit for adjusting the delay time of the second clock to be longer than the first clock when the delay time of the output signal is the High signal.

As described above, according to the present embodiment, the present embodiment has the effect of interpolating the SR latch by inputting the clock signal at the correct time in the analog-to-digital converter.

In this embodiment, adding a plurality of SR latches reduces the number of latches in the front end, thereby achieving high precision while reducing power consumption.

1 is a diagram illustrating an analog-digital converter 100 using an interpolation technique.
2A shows the output characteristics of the latch when the difference between the analog input voltage Vin and the reference voltage V1 is smaller than the difference between the analog input voltage Vin and the reference voltage V2.
2B is a diagram showing the output characteristics of the latch when the difference between the analog input voltage Vin and the reference voltage V1 is larger than the difference between the analog input voltage Vin and the reference voltage V2.
3A is a diagram of a multi-stage latch interpolation apparatus.
3B shows the operation of the third SR latch stage 360 third SR latch.
FIGS. 4 and 5 are views showing a driving method of the third SR latch stage 360. FIG.
6 is an overall configuration diagram of a circuit for generating the second clock 350. In Fig.
FIG. 7 is a diagram illustrating an appropriate timing for inputting the second clock 650. FIG.
8A is a detailed second clock regulating circuit 670 for regulating the delay time of the second clock 650. As shown in FIG.
8B shows the values of the pulses Q1, Q2, and Q3 generated in a separate logic circuit (not shown) to drive the charge pump 810. In FIG.
FIG. 8C shows the adjustment of the second clock according to the detailed second clock adjustment circuit 670 for adjusting the delay time of the second clock 650. FIG.

Hereinafter, the present embodiment will be described in detail with reference to the accompanying drawings. It should be noted that, in adding reference numerals to the constituent elements of the drawings, the same constituent elements are denoted by the same reference numerals even though they are shown in different drawings. In the following description of the present invention, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

In describing the components of the present invention, terms such as first, second, A, B, (a), and (b) may be used. These terms are intended to distinguish the constituent elements from other constituent elements, and the terms do not limit the nature, order or order of the constituent elements. When a component is described as being "connected", "coupled", or "connected" to another component, the component may be directly connected to or connected to the other component, It should be understood that an element may be "connected," "coupled," or "connected."

1 is a diagram illustrating an analog-digital converter 100 using an interpolation technique.

The analog digital converter 100 using the interpolation technique includes a reference voltage generator 110, a first latching column 120, and a second latching column 130.

1, only the part (a) of the analog-to-digital converter 100 using the interpolation technique will be described since the remaining part except the part (a) of FIG. 1 operates in the same manner as the part (a).

The reference voltage generating unit 110 generates the reference voltages V1 and V2 and inputs the reference voltages V1 and V2 to the negative input terminals of the first latches 121 and 122. At this time, the reference voltage generator 110 may include a plurality of resistors R1 and R2 connected in series between the power supplies for supplying the two voltages Vrefp and Vrefn, respectively. The reference voltages V1 and V2 input to the negative input terminals of the first latches 121 and 122 correspond to voltages obtained by dividing between the two voltages Vrefp and Vrefn using a plurality of resistors R1 and R2. Here, both of the voltages Vrefp and Vrefn may be positive voltages, and of the two voltages Vrefp and Vrefn, Vrefp may be a positive voltage and Vrefn may be a negative voltage. Also, one of the two voltages Vrefp and Vrefn may be a ground voltage.

The first latch array 120 includes a plurality of first latches 121, 122. The plurality of first latches 121 and 122 amplify and output the difference between the reference voltages V1 and V2 and the analog input voltage Vin corresponding to the analog signal. The first latches 121 and 122 receive the reference voltages V1 and V2 and the analog input voltage Vin. The reference voltages V1 and V2 are input to the negative input terminals of the first latches 121 and 122 and the analog input voltage Vin is input to the positive input terminals of the first latches 121 and 122 . When the first clock 140 is turned on, the difference between the reference voltages V1 and V2 at the time when the first clock 140 is turned on and the analog input voltage Vin are amplified to generate the differential signal {(A1 + , A1 - ), (A2 + , A2 - )}. Here, the differential signal {(A1 + , A1 - ), (A2 + , A2 - )} may be referred to as a first differential output signal pair.

The second latch array 130 includes a plurality of second latches 131, 132, and 133.

The first differential output signal pairs {(A1 + , A1 - ), (A2 + , A2 - )} of the first latches 121 and 122 of the first latch row 120 (+) And (-) input terminals of the two latches 131, 132 and 133, respectively. (+) Output (A1 + ) of the first differential output signal pair of the first latch 121 is input to the (+) input terminal of the second latch 131 and the first differential output signal The negative (-) output (A1 - ) of the pair is input to the negative input terminal of the second latch 131. (+) Output (A2 + ) of the first differential output signal pair of the first latch 122 is input to the (+) input terminal of the second latch 133, and the first differential output signal The negative (-) output (A2 - ) of the pair is input to the negative input terminal of the second latch 133. (-) output (A1 - ) of the first differential output signal pair of the first latch 121 is input to the negative input terminal of the second latch 132 of the second latch column, (+) Output (A2 + ) of the first differential output signal pair of the second latch 132 is input to the (+) input terminal of the second latch 132 of the second latch column. The plurality of second latches 131, 132, and 133 amplify the difference between the two voltages input from the first latches 121 and 122 when the second clock 150 is turned on, (L1 + , L1 - ), (L2 + , L2 - ), (L3 + , L3 - )} Here, the differential signal {(L1 + , L1 - ), (L2 + , L2 - ), (L3 + , L3 - )} is a second differential output signal pair.

2A shows the output characteristics of the latch when the difference between the analog input voltage Vin and the reference voltage V1 is smaller than the difference between the analog input voltage Vin and the reference voltage V2.

Referring to FIG. 2A, the first latch 121 and the second latch 122 of FIG. 1 are different in the time taken for output to occur depending on the voltage difference between the signals input to the two (+) and (-) input terminals. When the magnitude of the analog input voltage Vin is located between V1 and V2 and the difference between the analog input voltage Vin and the reference voltage V1 is smaller than the difference between the analog input voltage Vin and the reference voltage V2, The differential output signal pairs {(A1 + , A1 - ), (A2 + , A2 - )} of the first latches 121 and 122 have the form as shown in FIG. That is, since the difference between the analog input voltage Vin and the reference voltage V1 is smaller than the difference between the analog input voltage Vin and the reference voltage V2, the differential output signal pair A1 + , A1 - The time required for the change becomes longer than the time required for the differential output signal pair (A2 + , A2 - ) to change to the digital level. Since the first latch 121 has a higher reference voltage V1 than the input voltage Vin, the output signal A1 + of the latch 121 generates an output having a low level and the output signal of the first latch 121 (A1 - ) generates an output having a high level. On the other hand, since the first latch 122 has a lower reference voltage V2 than the input voltage Vin, the output signal A2 + of the first latch 122 generates an output having a high level and the output of the first latch 122 The output signal A2 < - >

2B is a diagram showing the output characteristics of the latch when the difference between the analog input voltage Vin and the reference voltage V1 is larger than the difference between the analog input voltage Vin and the reference voltage V2.

2B shows an example in which the magnitude of the analog input voltage Vin is between V1 and V2 and the difference between the analog input voltage Vin and the reference voltage V1 is between the analog input voltage Vin and the reference voltage V2 The differential output signal pairs {(A1 + , A1 - ), (A2 + , A2 - )} of the first latches 121 and 122 have the form as shown in FIG. 2 (b). That is, since the difference between the analog input voltage Vin and the reference voltage V1 is larger than the difference between the analog input voltage Vin and the reference voltage V2, the differential output signal pair A1 + , A1 - Becomes shorter than the time required for the differential output signal pair (A2 + , A2 - ) to change to the digital level. The first latch 121 generates a low level output signal A1 + of the first latch 121 because the reference voltage V1 is higher than the input voltage Vin and the output of the first latch 121 The output signal A1 - generates an output having a high level. On the other hand, since the first latch 122 has a lower reference voltage V2 than the input voltage Vin, the output signal A2 + of the first latch 122 generates an output having a high level and the output of the first latch 122 The output signal A2 < - >

In general, the latch can not apply the interpolation method to the output of the steady state. However, interpolation is possible in a specific time interval (T1) by using a characteristic in which the time required for the latch to generate the output in the normal state is proportional to the voltage difference of the signal input to the (+) and (-) input terminals.

3A is a diagram of a multi-stage latch interpolation apparatus.

3A, the multi-stage latch interpolation apparatus includes a reference voltage generator 310, a first latch stage 320, a second latch stage 330, and a third SR latch stage 360.

The reference voltage generating unit 310 generates the reference voltages V1 and V2 and supplies the reference voltages V1 and V2 to the negative input terminals of the first latches 321 and 322 of the first latch stage 320 . The reference voltages V1 and V2 correspond to voltages obtained by dividing two voltages Vrefp and Vrefn by using a plurality of resistors connected in series.

The first latch stage 320 includes a plurality of first latches 321 and 322. Each of the first latches receives an analog input voltage corresponding to the analog signal and each reference voltage and when the first clock is turned on And outputs the first differential (+) output and the first differential (-) output by amplifying the two voltage differences according to the input voltage at the time of the on state.

First latch stage 320 A plurality of first latches 321 and 322 amplify and output the difference between the reference voltages V1 and V2 and the analog input voltage Vin corresponding to the analog signal. First latch stage 320 First latches 321 and 322 receive reference voltages V1 and V2 and an analog input voltage Vin. The reference voltages V1 and V2 are input to the input terminals of the first latches 321 and 322 and the analog input voltage Vin is input to the input terminals of the first latches 321 and 322 . First latch stage 320 The first latches 321 and 322 are turned on when the first clock 340 is turned on by setting the difference between the reference voltages V1 and V2 and the analog input voltages V1 and V2 And outputs differential-type signals {(A1 + , A1 - ), (A2 + , A2 - )}. Here, the differential signal {(A1 + , A1 - ), (A2 + , A2 - )} may be referred to as a first differential output signal pair.

The second latch stage 330 includes a second latch including a plurality of second latches 331, 332, and 333 and receiving the differential outputs of one first latch at the (+) and (- (-) output of the first latch of the first latch and a first differential (+) output of the adjacent first latch that receives the low reference voltage adjacent to the reference voltage of the first latch to the (+) and And a second latch for receiving an input.

The first differential output signal pair {(A1 + , A1 - ), (A2 + , A2 - )} of the first latch stage 320 first latches 321, Are input to the (+) and (-) input terminals of the second latches 331, 332, and 333, respectively. (+) Output (A1 + ) of the first differential output signal pair of the first latch 321 of the first latch stage 320 is connected to the (+) input terminal of the second latch 331 (-) output (A1 - ) of the first differential output signal pair is input to the negative input terminal of the second latch 331 (second latch stage 330). (+) Output (A2 + ) of the first differential output signal pair of the first latch stage 320 of the first latch stage 320 is connected to the (+) input terminal of the second latch stage 330 second latch 333 (-) output (A2 - ) of the first differential output signal pair is input to the negative input terminal of the second latch 333 (second latch stage 330). (-) output A1 - of the first differential output signal pair of the first latch 321 of the first latch stage 320 is connected to the negative input terminal 321 of the second latch 332 of the second latch stage 330, And the (+) output (A2 + ) of the first differential output signal pair of the first latch 322 is input to the (+) input terminal of the second latch 332. The second latch 332 of the second latch stage 330 receives the first differential output signal pair, which is the output signal of the first latch stage 320, and the second latch stage 330, the second latch 331, 333) and receives the (-) input terminal at the upper end and the (+) input terminal at the lower end. The plurality of second latches 331, 332 and 333 are turned on when the second clock 350 is turned on by applying a voltage between the two latches 321 and 322 (L1 + , L1 - ), (L2 + , L2 - ), (L3 + , L3 - )} of the differential signal. Here, the differential signal {(L1 + , L1 - ), (L2 + , L2 - ), (L3 + , L3 - )} is a second differential output signal pair. In addition, the (+) input terminal is output at the upper end and the (-) input terminal is output at the lower end in the second latch stage 330 of the plurality of second latches 331, 332 and 333.

The third SR latch stage 360 includes a plurality of third SR latches and receives the (-) output value of any one of the second latches and the (+) output value of the adjacent lower second latch of any one of the second latches To generate an interpolation output. The SR latch receives the output value of any one of the second latches of the second latch stage and outputs the output signal without receiving the clock signal.

3B shows the operation of the third SR latch stage 360 third SR latch.

The third SR latch stage 360 includes a plurality of third SR latches 361, 362, 363, 364, and 365. The third SR latch has two inputs S (Set) and R (Reset) and two outputs Q and Q '. For example, if S = 1 and R = 0, S is set to 1 and therefore the output is Q = 1 and Q '= 0. If S = 0 and R = 0, both inputs are '0', so the output is determined by the previous output state. When the previous output is Q = 1 and Q '= 0, the output is Q = 1 and Q' = 0 when S = 0 and R = If S = 0 and R = 1, R is 1, so it is in the reset state and the output is Q = 0 and Q '= 1. If S = 0 and R = 0, both inputs are '0', so the output is determined by the previous output state. When the previous output is Q = 0 and Q '= 1, the output is Q = 0 and Q' = 1 when S = 0 and R = When S = 1 and R = 1, the output is Q = 0 and Q '= 0.

Referring to FIG. 3A, the third SR latch stage 360 generates a multi-stage latch by adding a plurality of SR latches after the second row sequence of FIG. At this time, the added plurality of SR latches receive the output value of the preceding second latch stage 330 as an input value without a clock signal to determine the output state. Here, if the third SR latch stage 360 is added, the number of the first latch stage 320 latches can be reduced, thereby achieving high precision while reducing power consumption. That is, since the number of latches of the first latch stage 320 increases in proportion to 2n exponential functions with respect to the precision n bits, the number of latches must be large in order to realize high precision. However, if a plurality of SR latches are added after the second latch stage 330, high precision can be realized while reducing the number of latches of the first latch stage 320 at the front end.

FIGS. 4 and 5 are views showing a driving method of the third SR latch stage 360. FIG.

4 and 5, the V axis means a voltage axis in which the position in the vertical direction has a value corresponding to the corresponding threshold level.

4, when the difference between the threshold level and the input level, which is the magnitude of the input voltage at which the output level of the second latch changes, is greater than the difference between the threshold level and the input level of the adjacent second latch, The output level is output faster than the output level of the adjacent second latch if the difference between the threshold level of the second latch and the input level is smaller than the difference between the threshold level of the adjacent second latch and the input level do.

4, when the input level of the analog-to-digital converter 100 is at the a-point 410 on the V-axis in the driving method of the third SR latch stage 360, the input corresponding to the a- Level is between the reference voltage V1 and the reference voltage V2 and has a level value higher than the threshold level of the first latch 322 of the first latch stage 320 and is higher than the threshold level of the first latch 321 And the second latch (330) second latch (332). Here, the threshold level means a value at which the level of each of the first latch and the second latch varies. the input level corresponding to the point a is higher than the threshold level of the second latch 333 of the second latch stage 330 and lower than the threshold level of the second latch 332 Value. Also, the input level corresponding to the a point 410 has a value closer to the threshold level of the second latch 333 of the second latch stage 330. the threshold level of the second latch 333 according to the input level of the a point 410 is relatively small compared to the input level and the threshold level of the second latch stage 330 The level is relatively large compared to the input level.

4, the negative (-) output of the second latch 332 of the second latch stage 330 having a relatively large difference between the input level and the threshold level at the a point 410 of the A / The output of the third SR latch stage 360 is input to the third SR latch 364. When the second latch 332 receives an input value from the first latch, the second latch 332 receives an input value through the (-) input terminal at the upper end thereof and the (+) input terminal at the lower end thereof, (+) Output terminal on the upper side and (-) output terminal on the lower side in the same manner as the second latches 331 and 333 of the second latch 331 and 333. Here, the output value of the (-) output terminal of the second latch 332 of the second latch stage 330 is '1'.

the output value '1' of the (+) output terminal of the second latch 333 of the second latch stage 330 having a relatively small difference between the input level and the threshold level of the a point 410 is outputted more slowly, Stage 360 is input to the R input terminal of the third SR latch 364. Second Latch Terminal 330 Since the second latch 333 is a latch, it outputs a (+) input terminal at the upper end and a (-) input terminal at the lower end. Here, the output value of the (+) output terminal of the second latch 333 is '1'. The third SR latch stage 360 receives the (-) output value '1' of the second latch 332 at the S input terminal. The third SR latch 364 is set to the set state because S is 1, 1 and Q '= 0.

The third SR latch stage 360 and the third SR latch 363 are input to the S input terminal and the R input terminal, respectively, which are the output values of the second latch 332 and the second latch stage 330 . If S = 0 and R = 1, then R is 1, so the corresponding SR latch is in Reset state, so the output is Q = 0 and Q '= 1.

Third SR latch stage 360 The third SR latch 365 inputs the output values 1 and 0 of the second latch 333 of the second latch stage 330 as an input value to the S input terminal and the R input terminal, respectively . If S = 1 and R = 0, S is 1, so the corresponding SR latch is in Set state and the output is Q = 1 and Q '= 0.

5, when the input level of the analog-to-digital converter 100 is at the b-point 510 on the V-axis in the driving method of the third SR latch stage 360, the input corresponding to the b- Level is between the reference voltage V1 and the reference voltage V2 and is higher than the threshold level of the first latch 322 of the first latch stage 320 and the threshold level of the second latch 332 of the second latch stage 330 And has a level value lower than the threshold level of the first latch 321. Here, the threshold level means a value at which the level of each of the first latch and the second latch varies. the input level corresponding to point b 510 has a value higher than the threshold level of the second latch 332 of the second latch stage 330 and the threshold level of the second latch stage 330 It has a lower level value. the input level at point b 510 is closer to the threshold level of the second latch 331 than the second latch 332 of the second latch stage 330. the threshold level of the second latch 332 according to the input level of the b point 510 is relatively large compared to the input level and the threshold level of the second latch 332 of the second latch stage 330 The threshold level is relatively small compared to the input level.

The (+) output value of the second latch 332 of the second latch stage 330 having a relatively large difference between the input level and the threshold level of the analog-to-digital converter 100 is output more quickly and the third SR latch stage 360 And input to the R input terminal of the third SR latch 362. In the case of the second latch stage second latch 332, the (-) input terminal is provided at the upper end thereof and the (+) input terminal is provided at the upper end thereof to receive the input value. (+) Input terminal on the top and (-) input terminal on the bottom. Here, the output value of the (+) output terminal of the second latch 332 of the second latch stage 330 is '1'.

the (-) output value of the second latch 331 having the relatively small difference between the input level and the threshold level of the b point 510 is output more slowly so that the third SR latch stage 360 Is input to the S input terminal of the SR latch 362. Here, the second latch 331 of the second latch stage 330 outputs a (+) input terminal at the upper end and a (-) input terminal at the lower end. Here, the output value of the (-) output terminal of the second latch 331 of the second latch stage 330 is '1'. The third SR latch stage 360 receives the R = 1 from the second latch 332 of the second latch stage 330 and the third SR latch 362 is reset so that the output is Q = 0 and Q '= 1.

Third SR latch stage 360 The third SR latch 361 receives the input values 0 and 1, which are output values of the second latch stage 330 and the second latch 331, to the S input terminal and the R input terminal, respectively . If S = 0 and R = 1, R is 1, so it is in the reset state and the output is Q = 0 and Q '= 1.

Third SR latch stage 360 The third SR latch 363 inputs the output values 1 and 0 of the second latch 332 of the second latch stage 330 as an input value to the S input terminal and the R input terminal, respectively . If S = 1 and R = 0, S is 1, so it is in Set state and the output is Q = 1 and Q '= 0.

6 is an overall configuration diagram of a circuit for generating the second clock 350. In Fig.

The analog-to-digital converter 601 includes a reference voltage generator, a first latch stage, a second latch stage, and a third SR latch stage, and has a plurality of cells including the same components. The reference voltage generator 610, the first latch stage 620, the second latch stage 630, and the third latch stage 630, which are the same as one cell among the plurality of cells 602, 603, 660 is a Ripple cell 600. The Ripple cell 600 is a Ripple cell.

6, the overall configuration of the circuit for generating the second clock 350 includes a reference voltage generator 610, a first latch stage 620, a second latch stage 630, a third latch stage 660, And a second clock adjustment circuit 670. The Ripple cassette 600 includes a first clock control circuit 670 and a second clock control circuit 670. [

The first latch stage includes a plurality of first latches, each of the first latches receives an analog input voltage corresponding to an analog signal and each reference voltage, amplifies two voltage differences according to the first clock to generate a first differential (+ ) Output and a first differential (-) output. The second latch stage includes a plurality of second latches. The differential outputs of one first latch are input to the (+) and (-) input terminals, respectively, and the two differential voltages are amplified according to the second clock to generate a second differential (-) output of one of the first latches and a first differential (-) output of one of the adjacent first latches receiving a low reference voltage adjacent to the reference voltage of the first latch And a second latch for receiving a first differential (+) output to the (+) and (-) terminals and outputting a second differential (+) output and a (-) output by amplifying two voltage differences according to the second clock do. The third SR latch stage receives the (-) output value of any one of the second latches and the (+) output value of the adjacent lower second latch of any one of the second latches to generate an interpolation output of a High signal or a Low signal 3 SR latches.

The first latch stage 620, the second latch stage 630 and the third SR latch stage 660 are connected to the first latch stage 320, the second latch stage 330, 3 SR latch stages 360, respectively. When the third SR latch stage 660 receives the input voltage 611 corresponding to the threshold level of the third SR latch 662, the third SR latch stage 660, the third SR latch 662, Q = 0 and Q '= 1 as output values when the delay time of the delay circuit 650 is long. When the delay time of the second clock 650 is long, the third SR latch stage 660 always outputs a constant output value depending on the characteristics of the latch. Therefore, the delay time of the second clock 650 is long . Here, in order to increase the delay time of the second clock 650, a large voltage is applied as an initial voltage in a second clock 650 control circuit of FIG. 8 to be described later. When a large voltage is applied as an initial voltage, the delay time of the second clock 650 becomes longer compared to the first clock 640, so that the second clock 650 is generated in comparison with the first clock 640. For example, when a voltage of 0.6 V is applied as an initial voltage, the second clock 650 is generated in a slower fashion than the first clock 640.

The Ripple cell 600 receives the input voltage 611 corresponding to the threshold level of the third SR latch stage 360 and the third SR latch 662 and adjusts the delay time of the second clock 650 And finds the input timing of the second clock 650 so that the third SR latch stage 660 can be interpolated according to the second clock 650 control circuit.

6, the input voltage 611 corresponding to the threshold level of the third SR latch stage 660 and the third SR latch 662 is input. The first differential output (A1 + ) of the first latch stage 620 is input to the (+) input terminal of the second latch stage 630 latch 631 and the first differential (+ -) output (A1 - ) is input to the (-) input terminal. Here, the input voltage difference between the second latch stage 630 and the second latch 331 is A (680). The first latch stage 620, the first differential of the first latch 621 (-), the output (A1 -) the second latch end 630 of the second latch 631 (-) is input to the input terminal a first The first differential (+) output (A2 + ) of the first latch 622 of the latch stage 620 is input to the (+) input terminal of the second latch stage 630 latch 632. Here, the input voltage difference between the second latch 630 and the second latch 632 is B (690). When the input voltage 611 corresponding to the threshold level of the third SR latch 662 is inputted, the voltage of the (+) input terminal of the second latch 631 of the second latch 631 The voltage difference A 680 of the negative input terminal of the second latch stage 630 and the voltage difference B 690 of the negative input terminal of the second latch 632 and the negative input terminal of the second latch 630 are the same . The voltage difference between the voltage at the (+) input terminal of the second latch 631 of the second latch stage 630 and the voltage difference A (680) between the negative input terminal of the second latch stage 630 and the second latch 632 The second clock 650 must be input at the time when the voltage difference B (690) of the negative input terminal and the voltage difference B (690) of the negative input terminal become equal to each other, so that the third SR latch stage 660 can be interpolated.

FIG. 7 is a diagram illustrating an appropriate timing for inputting the second clock 650. FIG.

7, the difference between the first differential (-) output (A1 - ) and the first differential (+) output A1 + of the first latch 621 of the first latch stage 620 is A (680) the first differential of the first latch stage 620, a first latch 622, a first differential (+) output (A2 +) and the first latch stage 620, a first latch 621 of the (-) output (A1 - ) Is B (690). Here, the time point when the voltage difference between A (680) and B (690) have the same value is C (7100). Interpolation of the third SR 660 latch stage is possible when the second clock 650 is input at the C 710 time point.

8A is a detailed second clock regulating circuit 670 for regulating the delay time of the second clock 650. As shown in FIG.

The second clock regulating circuit 670 may be configured to include a charge pump 810 and a clock regulator 820.

8B shows the values of the pulses Q1, Q2, and Q3 generated in a separate logic circuit (not shown) to drive the charge pump 810. In FIG.

FIG. 8C shows the adjustment of the second clock according to the detailed second clock adjustment circuit 670 for adjusting the delay time of the second clock 650. FIG.

8, the output of the third SR latch of the third SR latch stage 660, which generates an interpolation output at Q'_COMP_P and Q_COMP_N, is input. Where the third SR latch is the third SR latch stage 660 and the third SR latch 662. Third SR latch stage 660 The third SR latch 662 receives the same input value as the R input terminal of the third SR latch stage 660 located directly above and the third SR latch 661, 3 SR latch stage 660 Receives the same input value as the S input terminal of the third SR latch 663. Third SR latch stage 660 The output Q 'of the third SR latch 662 is input to Q'_COMP_P and coupled to the Q1 value generated by the separate logic circuit with the first AND gate. The third SR latch stage 660 The output value Q of the third SR latch 662 is input to Q_COMP_N and connected to the Q1 value generated by the separate logic circuit by the second AND gate. When the first AND gate outputs '1', the first switch is turned on, and when the second AND gate outputs '1', the second switch is turned on. VP is VDD higher than VN and VN is GND lower than VP. There is a small-capacity capacitor C1 and a large-capacity capacitor C2. When the capacitor C2 having a large capacitance is charged, the gate voltage is increased and when the capacitor C2 having a large capacitance is discharged, the gate voltage is reduced. Here, the charging and discharging of the capacitor are operated when the third switch is on, and the third switch is operated by the value Q2. Q2 has a value generated by a separate logic circuit. Q3 initializes the operation of the second clock (650) regulating circuit, and once it is initialized, it remains open after that.

The clock regulator 820 also adjusts the delay time of the second clock 650 in response to the first clock 640 according to the voltage generated by the charge pump 810. In the circuit connected to the first clock 640, the source of the first transistor is connected to the supply voltage VDD, and the gate of the first transistor and the gate of the second transistor are connected to the first clock 640. The source of the second transistor is connected to the drain of the third transistor, and the source of the third transistor is connected to the ground (GND). The voltage generated by the charge pump 810 is connected to the gate voltage of the third transistor. In the circuit connected to the second clock 650, the drain of the first transistor and the drain of the second transistor are connected to the gate of the fourth transistor and the gate of the fifth transistor, and the source of the fourth transistor is connected to the supply voltage VDD. And the drain of the fourth transistor and the drain of the fifth transistor are connected to the second clock 650. The source of the fifth transistor is connected to ground (GND).

8A, when the first clock 640 is high and a large voltage is input to the gate voltage VG3 of the third transistor, the difference between the gate and the source of the third transistor becomes large So that the current of the third transistor flows quickly. When the current of the third transistor rapidly flows, currents of the first transistor and the second transistor rapidly flow. Also, since the currents of the first transistor and the second transistor are also rapidly flowing in V1 at the point where the drain of the first transistor, the gate of the second transistor, the gate of the fourth transistor, and the gate of the fifth transistor are connected, Lower. If the voltage of V1 rapidly decreases, the difference between the gate and the source of the fourth transistor becomes large at an early point, so that the second clock 650 becomes high at an early point.

When the first clock 640 is high and a small voltage is input to the gate voltage VG3 of the third transistor, the difference between the gate and the source of the third transistor is small, so that the current of the third transistor flows slowly. When the current of the third transistor flows slowly, the currents of the first transistor and the second transistor also flow slowly. Also, since the currents of the first transistor and the second transistor also flow slowly in V1 at the point where the drain of the first transistor, the drain of the second transistor, the gate of the fourth transistor, and the gate of the fifth transistor are connected, Lower. If the voltage of V1 is slowly lowered, the difference between the gate and the source of the fourth transistor becomes large at a later timing, so that the second clock 650 becomes high at a later timing.

The overall operation of the differential pump 810 and the clock regulator 820 shown in FIG. 8 (A) is as follows.

6, when the input voltage Vin corresponding to the threshold level of the third SR latch 662 is inputted, the third SR latch stage 660 ) The output value Q = 0, Q '= 1 of the third SR latch 662 is output. Referring to FIG. 8, when the output value Q 'of the output Q of the third SR latch 662 and the output value' 1 'of Q' of Q '= 1 are input to the Q'_COMP_P of the charge pump 810 and the output value' 0 ' pump < RTI ID = 0.0 > (810). < / RTI > When the gate voltage of the second capacitor 650 is higher than that of the first capacitor 640 as shown in FIG. 8C, the second clock 650 becomes high at an earlier point in time than the first clock 640 .

When the second clock 650 is generated faster than the first clock 640, the output values Q = 1 and Q '= 0 of the third SR latch 360 and the third SR latch 362 are output. The output value '0' of Q 'is input to the Q'_COMP_P of the charge pump 810 and the output value' 1 'of Q is input to the Q_COMP_N of the charge pump 810. If the gate voltage of the capacitor C2 is discharged after the large capacity of the capacitor C2 is discharged, the second clock 650 becomes high at a later time than the first clock 340 as shown in FIG. 8 (b) .

 When the second clock 650 is generated slowly compared to the first clock 640, the output values Q = 0 and Q '= 1 of the third SR latch stage 660 and the third SR latch 662 are output. The output value '1' of Q 'is input to the Q'_COMP_P of the charge pump 810 and the output value' 0 'of Q is input to Q_COMP_N of the charge pump 810. When the gate voltage of the second capacitor 650 is higher than that of the first clock 640 as shown in FIG. 8 (c), the capacitor C 2 is discharged at a higher speed than the first clock 640 .

 In accordance with the above process, the Riplexer 600 provides the second clock 650 generated by the second clock regulating circuit 670 to the analog-to-digital converter.

The delay time of the second clock 650 with respect to the first clock 640 is adjusted. In the above process, the delay time of the second clock 650 with respect to the first clock 640 becomes longer and shorter, and the second clock 650 is oscillated repeatedly. The second clock 650 of the multi- (350).

The foregoing description is merely illustrative of the technical idea of the present embodiment, and various modifications and changes may be made to those skilled in the art without departing from the essential characteristics of the embodiments. Therefore, the present embodiments are to be construed as illustrative rather than restrictive, and the scope of the technical idea of the present embodiment is not limited by these embodiments. The scope of protection of the present embodiment should be construed according to the following claims, and all technical ideas within the scope of equivalents thereof should be construed as being included in the scope of the present invention.

110: Reference voltage generator 120:
130: second latch array 310: reference voltage generator
320: first latching stage 330: second latching stage
360: third SR latch stage 810: charge pump

Claims (3)

CLAIMS 1. A clock calibration apparatus for an analog to digital converter,
The first latch includes a plurality of first latches, each of the first latches receives an analog input voltage corresponding to the analog signal and each reference voltage, amplifies two voltage differences according to the first clock to generate a first differential (+ A first latch stage for outputting a first differential (-) output;
(+) And (-) input terminals of the differential output of one first latch and amplifies two voltage differences according to the second clock to output a second differential (+) output and a second differential output -) output of the first latch and a first differential (-) output of the adjacent first latch receiving a low reference voltage adjacent to the reference voltage of the first latch and a first differential (- And a second latch that receives the outputs of the first and second differential amplifiers and outputs a second differential (+) output and a negative (-) output by amplifying the two voltage differences according to the second clock, only;
(-) output value of any one of the second latches and a (+) output value of the adjacent lower second latch of any one of the second latches to generate an interpolation output of a High signal or a Low signal A third SR latch terminal; And
When the analog input voltage corresponding to the third SR latch is input to the first latch, the output of the third SR latch is received, and when the output is the Low signal, And adjusting a delay time of the second clock to be longer than a delay time of the first clock when the delay time is shorter and the output is the High signal,
/ RTI > The method according to claim 1,
Wherein the first latch stage, the second latch stage, and the third latch stage are configured separately from the analog-to-digital converter and have the same configuration and wiring configuration as some of the components of the analog-to- Clock calibration device. The method according to claim 1,
And provides the second clock generated by the second clock adjustment circuit to the analog-to-digital converter.
KR1020130160711A 2013-12-20 2013-12-20 Analog to Digital Converter for interpolation using Calibration of Clock KR20150072972A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106357268A (en) * 2016-09-29 2017-01-25 珠海格力电器股份有限公司 Comparator delay correction circuit in ADC (analog to digital converter), method and ADC
US20230179188A1 (en) * 2021-12-03 2023-06-08 Nanya Technology Corporation Data receiving circuit
US11770117B2 (en) 2021-12-07 2023-09-26 Nanya Technology Corporation Data receiving circuit

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106357268A (en) * 2016-09-29 2017-01-25 珠海格力电器股份有限公司 Comparator delay correction circuit in ADC (analog to digital converter), method and ADC
CN106357268B (en) * 2016-09-29 2019-08-23 珠海格力电器股份有限公司 Comparator delay correction circuit, method and ADC in a kind of ADC
US20230179188A1 (en) * 2021-12-03 2023-06-08 Nanya Technology Corporation Data receiving circuit
US11728794B2 (en) * 2021-12-03 2023-08-15 Nanya Technology Corporation Data receiving circuit
US11770117B2 (en) 2021-12-07 2023-09-26 Nanya Technology Corporation Data receiving circuit

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