JP2010278952A - Successive approximation a/d converter circuit, and semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To correct errors resulting from switching noise generated in a comparison circuit and improve conversion accuracy without inviting an increase in area, reduction in conversion rate or increase in consumption current in a successive approximation analog-digital (AD) converter circuit. <P>SOLUTION: In the successive approximation AD converter circuit provided with the comparison circuit including a plurality of amplifier stages cascade-connected via a coupling capacitance for evaluating sizes of input analog voltage and comparison voltage, a capacitance with one terminal connected to an input terminal of a first stage of amplifier stages in the comparison circuit, a sub-DA converter circuit having a switching means capable of switching voltages to be applied to another terminal of the capacitance based on an output from the comparison circuit, and a control circuit which can generate a control signal for the sub-DA converter circuit depending on the output from the comparison circuit to allow the comparison circuit to perform a redundancy comparison as well as can execute an averaging processing of the outputs from the comparison circuit to generate correction signal of a value for a register are provided to allow to execute the redundancy comparison action using a result of a normal AD conversion action as a start value after the AD conversion action. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a technique for improving conversion accuracy in a successive approximation AD converter circuit, and more particularly to a technique suitable for use in an AD converter circuit having a chopper comparator.

  Portable electronic devices such as mobile phones, PDAs (Personal Digital Assistants), and digital cameras are equipped with a microprocessor to control the system inside the device. The microprocessor monitors the temperature and battery voltage. Control is in progress. Therefore, equipment is provided with sensors for detecting temperature, battery voltage, etc., and a microprocessor with an A / D conversion circuit for converting analog signals from these sensors into digital signals is used. There are many.

  Further, it is desired that the A / D conversion circuit built in the microprocessor or the like has a small circuit scale. As such an A / D conversion circuit, for example, an A / D conversion circuit using a so-called chopper type comparator using a CMOS inverter as an amplifier as shown in FIG. 4 is known.

  In this A / D conversion circuit, a switch (sampling switch) SS1 on the analog signal input side is turned on with the sampling clock short-circuited between the input and output terminals of the CMOS inverter, and the logical threshold voltage of the inverter is used as a reference. The input signal Vin is sampled into the capacitor Cs. Thereafter, the sampling switch SS1 is turned off, the switch SS2 on the comparison voltage input side is turned on, the comparison voltage Vref is applied to the sampling capacitor Cs, and the input and output of the CMOS inverter are shut off, whereby each inverter becomes an amplifier. Operates and changes output. At this time, since the input is amplified by the three-stage inverter, the output becomes the power supply voltage Vcc or the ground potential GND which is almost at the logic level, and the determination result of the magnitude relation between Vin and Vref is output.

JP 2003-283336 A

  In the successive approximation type AD converter circuit, a determination error may occur due to the determination being made before the comparison voltage has completely changed due to an increase in clock speed, and the AD conversion accuracy may be reduced. In order to solve such a problem, an invention has been proposed in which an error is corrected by adding a redundant comparison cycle to a normal comparison cycle to improve AD conversion accuracy (Patent Document 1).

  However, in the successive approximation type AD converter circuit, an error is caused in the AD conversion result by incorporating thermal noise generated by elements such as resistors and transistors during sampling and noise (substrate noise) due to leakage current flowing through the substrate into the sampling capacitor. In addition, an error may occur in the AD conversion result due to switching noise generated in the comparator during comparison.

  In FIG. 5, the horizontal axis represents the analog input voltage, and the relationship between the switching frequency of the comparator and the code change of the AD conversion output is shown. Among these, (A) shows the case where the variation in the switching frequency of the comparator is small, and (B) shows the case where the variation in the switching frequency of the comparator is large.

  From FIG. 5, when the variation in the frequency of the comparator is small as shown in (A), the conversion result is stable and there is little possibility of an error, but the variation in the frequency of the comparator is large as shown in (B). In this case, it can be seen that the conversion result becomes unstable and an error is likely to occur. Specifically, when ± 3.3σ becomes wider than 1 LSB (for example, 1 mV) when frequency variation forms a normal distribution, a part of frequency distribution overlaps as shown in (B), that is, what analog input Even if AD conversion is performed, a constant digital code output cannot be obtained, and an error is likely to occur.

  In particular, an AD converter circuit including a chopper comparator often has characteristics as shown in FIG. The invention described in Patent Document 1 can correct an error due to a determination error that occurs when a determination is made before the comparison voltage has completely changed due to high speed, but thermal noise, substrate noise, There is a problem that an error due to a determination error caused by switching noise of a comparator, that is, an error caused by noise generated in a circuit cannot be corrected.

  Although errors caused by taking thermal noise and substrate noise into the sampling capacitor can be reduced by measures such as increasing the capacitance value of the sampling capacitor, doing so increases the area and increases costs. In addition, other problems occur, such as a reduction in conversion speed. Further, with such a countermeasure, there is a problem that even if an error due to noise can be reduced, the error cannot be corrected.

  The present invention has been made paying attention to the above-described problems, and the object of the present invention is to correct errors caused by switching noise mainly generated in the comparison circuit in the successive approximation type AD conversion circuit and to correct the AD conversion accuracy. It is to be able to improve.

In order to achieve the above object, the present invention provides:
A comparison circuit that includes a plurality of amplification stages connected in cascade via a coupling capacitor, determines the magnitude of the input analog voltage and the comparison voltage, a register that sequentially captures and holds the determination result of the comparison circuit, and a value of the register A successive approximation AD converter circuit comprising: a local DA converter circuit that converts the voltage into a voltage and generates the comparison voltage;
A switch capable of switching between one or more capacitors having one terminal connected to the input terminal of the first amplification stage of the comparison circuit and a voltage applied to the other terminal of the capacitor based on the output of the comparison circuit A sub-DA conversion circuit having means;
A control signal for the sub DA converter circuit is generated in accordance with the output of the comparator circuit, and the comparator circuit performs a redundant comparison and averages the output of the comparator circuit to generate a correction signal for the register value. Possible control circuit,
And after the normal AD conversion operation using the local DA conversion circuit, a redundant comparison operation using the sub DA conversion circuit can be executed using the conversion result as a start value.

  According to the configuration described above, since the redundancy comparison is performed in a range that is buried in the switching noise of the amplification stage, an AD conversion value in which an error due to the switching noise of the amplification stage is corrected can be obtained. . In addition, since the redundancy comparison operation is executed using the conversion result as the start value after the normal AD conversion operation, the time required for AD conversion does not become extremely long.

  Here, preferably, the control circuit causes the redundant comparison using the sub DA conversion circuit to be executed a plurality of times, and the result of the normal AD conversion operation using the local DA conversion circuit and the redundant comparison of the plurality of times are performed. An averaging process with the result is performed, and the value of the register can be changed according to the result of the averaging process. This makes it possible to obtain a more accurate AD conversion value in which an error due to switching of the amplification stage is corrected.

  Preferably, the local DA converter circuit includes two or more capacitors weighted by powers of 2 and switch means provided corresponding to each capacitor, and the sub DA converter circuit includes: 2 or more k capacitors weighted to the power of 2, and switch means provided corresponding to each capacitor, wherein k is smaller than n and is the smallest of the n capacitors The smallest one of the k capacitors is configured to have the same capacitance value. This facilitates the design of the sub DA conversion circuit.

Further, preferably, the local DA conversion circuit includes:
A capacitor array including a plurality of weight capacitors, one terminal of which is commonly connected to the input terminal of the comparison circuit, and an input analog voltage, the first reference voltage, or the second reference, respectively, to the other terminal of the plurality of weight capacitors. A changeover switch circuit capable of applying a voltage;
Ladder resistance provided between a first node to which the first reference voltage is applied and a second node to which the second reference voltage is applied, and selection means for extracting a potential from any node of the ladder resistance And comprising
The changeover switch circuit determines a connection state according to the values of a plurality of bits on the upper side of the register, applies an input analog voltage to the other terminal of the plurality of weight capacitors in a first period, Applying the first reference voltage or the second reference voltage to the other terminal of the plurality of weight capacitors according to the value of the first register during a period;
The selection means determines a potential to be extracted according to the values of a plurality of bits on the lower side of the register, and the potential extracted by the selection means is calculated by the changeover switch circuit during the second period. Is applied to the terminal with the smallest capacitance value,
The voltage applied to the capacitor by the switch means in the sub DA conversion circuit is configured to be extracted from any node of the ladder resistor of the local DA conversion circuit.

  By configuring the local DA converter circuit with a capacitor array and a ladder resistor, an increase in the circuit scale of the local DA converter circuit can be suppressed even when the number of conversion bits of the AD converter circuit is large. Since the ladder resistor can be shared as a switching voltage generating means used in the sub DA conversion circuit, an increase in circuit scale can be suppressed.

Preferably, the comparison circuit includes:
Having a CMOS inverter as the amplification stage, a switch element provided between the input and output terminals of each CMOS inverter, and a coupling capacitor provided between the CMOS inverters,
In the first period, the switch element is turned on, a voltage corresponding to the logic threshold of the CMOS inverter is applied to one terminal of the sampling capacitor, and an input analog voltage is taken in based on the voltage,
In a second period, the sampling capacitor is charged with a charge corresponding to the potential difference between the input analog voltage and the comparison voltage, and the switch element is turned off to amplify the potential of the sampling capacitor by the CMOS inverter To be configured. Thereby, the magnitude of the input analog voltage and the comparison voltage can be determined without using a comparator such as a differential amplifier circuit having a large number of elements constituting the circuit.

  According to another aspect of the present application, in a semiconductor integrated circuit including a successive approximation AD converter circuit having a configuration as described above and a CPU, a register in which the number of comparison operations can be set by the CPU is provided. The circuit is configured to control the sub DA conversion circuit in accordance with the set value of the register. As a result, the number of redundant comparisons can be made variable according to the analog signal to be converted, and an AD conversion result having a desired conversion accuracy can be obtained within a relatively short time according to the signal characteristics. become.

  According to the present invention, in the successive approximation type AD converter circuit, it is possible to correct errors caused by switching noise mainly generated in the comparison circuit and improve AD conversion accuracy.

1 is a circuit configuration diagram showing an embodiment of a successive approximation AD converter circuit according to the present invention. FIG. 3 is a circuit configuration diagram showing a second embodiment of a successive approximation AD converter circuit according to the present invention. 5 is a time chart showing the level of the output voltage (Vref) of the local DA converter circuit for each cycle, with the time axis on the horizontal axis. It is a circuit block diagram which shows the structural example of the conventional AD converter circuit provided with the chopper type comparator. Taking the analog input voltage on the horizontal axis, the relationship between the switching frequency of the comparator and the code change of the AD conversion output is shown. (A) shows a small variation in the switching frequency of the comparator, (B) shows the comparator It is explanatory drawing which shows the case where the dispersion | variation in switching frequency of is large.

  DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, preferred embodiments of the invention will be described with reference to the drawings.

  FIG. 1 shows an embodiment of a successive approximation AD converter circuit according to the present invention. The AD conversion circuit shown in FIG. 1 is a sample-and-hold circuit 11 that alternately samples an analog input Vin input to an analog input terminal and a comparison voltage Vref applied to a reference voltage terminal to hold a difference voltage. A chopper comparator 12 that amplifies the differential voltage sampled by the sample and hold circuit 11, a successive approximation register 13 that sequentially captures the output of the chopper comparator 12, and a signal output from the register 13 The local DA conversion circuit 14 that outputs the voltage obtained by DA-converting the output code of the register 13 as the comparison voltage Vref to the sample and hold circuit 11 when the switch is switched, and the control that outputs the predetermined signal using the output of the comparator 12 as an input The circuit 15 and the CMOS input of the first stage of the comparator 12 And a sub-DA converter (SubDAC) 16 which is connected to an input terminal of the chromatography data INV1.

  The sample and hold circuit 11 includes a pair of sampling switches SS1 and SS2 that are complementarily turned on and off by a sampling clock φs and a clock / φs having a phase opposite to the sampling clock φs, a connection node between the switches SS1 and SS2, and the chopper comparator The sampling capacitor Cs is connected between 12 input terminals.

  The chopper comparator 12 has three CMOS inverters INV1, INV2, and INV3 connected in cascade through capacitors C2 and C3, and switches S1, S2, and S3 that short-circuit the input / output terminals for each inverter. It is set as the provided structure.

  In the comparator 12 of this embodiment, the switches S1, S2, and S3 are turned on during the sampling period, and the input and output of the inverters INV1, INV2, and INV3 are short-circuited. The potential is equal to the threshold value VLT. Therefore, in the sample and hold circuit 11, the switch SS1 on the input terminal side is turned on by the sampling clock φs. As a result, the input analog voltage Vin is sampled in the sampling capacitor Cs with reference to VLT. That is, Cs is charged with a charge corresponding to the potential difference between VLT and Vin. The capacitors C2 and C3 are charged with voltages (VLT2−VLT1) and (VLT3−VLT2) which are the differences between the logic threshold values of the inverters.

  At the time of comparison determination (hold period), in the sample and hold circuit 11, the reference-side switch SS2 is turned on by the sampling clock / φs. As a result, charges corresponding to the potential difference (Vref−Vin) between the input analog voltage Vin and the comparison voltage Vref remain in the sampling capacitor Cs. In the comparator 12, the switches S1, S2, and S3 are turned off by φs and the input and output of the inverters INV1, INV2, and INV3 are cut off, so that each inverter operates as an amplifier and outputs according to the input potential. Change.

  At this time, the potential difference (Vref−Vin) is transmitted to the input terminal of the first-stage inverter INV1 through the sampling capacitor Cs, and the potential difference is gradually amplified by the inverters INV1, INV2, and INV3. As a result, the result of comparing the input analog voltage Vin and the comparison voltage Vref appears at the output of the inverter INV3. Specifically, when Vin is higher than Vref, the output of the inverter INV3 is at a low level (ground potential GND), and when Vin is lower than Vref, the output of the inverter INV3 is at a high level (power supply voltage Vdd).

  The sub D / A converter circuit 16 is connected to a capacitor CDA1... CDAk having one terminal connected to the input terminal of the first-stage inverter INV1, and to the other terminal of each capacitor CDA1. Switch SW11... SW1k for selectively applying. Vref_h and Vref_l are voltages corresponding to an upper limit value and a lower limit value of a voltage range FSR (Full Scale Range) in which AD conversion is possible.

Capacity CDA1 ...... CDAk are each 2 ^0, 2 ^1, the capacitance value such that the relationship with the weight of the ...... 2 ^k-1 is set. For example, when the local DA converter circuit 14 is a charge distribution type circuit using a weight capacitor, the smallest capacitor CDak is the same as the smallest capacitor among the weight capacitors constituting the local DA converter circuit. The capacity value. The switches SW11... SW1k perform a switching operation of the voltage to be applied according to a signal from the control circuit 15. The two weighted weight capacity constituting the local DA conversion circuit 14 ^0, 2 ^1, when ...... 2 ^n, k is a positive integer smaller than n.

  The control circuit 15 has a function of averaging a plurality of redundant comparison results output from the comparator 12 by a redundant comparison operation described later, and includes a register (accumulator) that holds the redundant comparison results of the comparator 12 and a plurality of It is composed of an arithmetic circuit (adder) that takes the average of the redundant comparison results of the first time.

  The output of the comparator 12 can be supplied / shut off to the successive approximation register 13 via a transmission gate G1 such as an AND gate. The transmission gate G1 is controlled by the control circuit 15 by the local DA conversion circuit 14. When the conversion is started, the output of the comparator 12 is transmitted to the successive approximation register 13, and when the normal DA conversion is completed, the transmission of the output of the comparator 12 to the successive approximation register 13 is controlled.

  Next, the operation procedure of the AD conversion circuit of this embodiment will be described with reference to FIG. FIG. 3 shows the level of the output voltage (Vref) of the local DA converter circuit for each cycle, with the time axis on the horizontal axis.

  In FIG. 3, a period indicated by a symbol T1 is a period in which a normal AD conversion operation using the local DA converter circuit 14 is performed, and the same number of times (n times) as the number of weighting capacitors while switching the DAC output. ) Is only compared. A period indicated by a symbol T2 is a period in which a redundant comparison operation using the sub DA conversion circuit is performed, and the same sequence is repeated a plurality of times (m times) in the redundant comparison. In each redundancy comparison, the comparison is performed k times by switching the switches SW11... SW1k in FIG.

  Further, the redundancy comparison performed after the normal AD conversion is started by using the conversion result obtained by the normal AD conversion as a start value, that is, without newly sampling while holding the AD conversion value in the successive approximation register. Although not shown in FIG. 3, when m redundancy comparison sequences are completed, the lower bits of the normal AD conversion result and the k redundancy comparison results are averaged, and the average value is determined according to the average value. Then, addition or subtraction is performed on a value obtained by normal AD conversion and held in the successive approximation register.

  During normal AD conversion operation (including sampling), the voltage Vref_h is applied to the terminal of the largest capacitor CDAk by the changeover switch SW1k in the sub DA converter circuit 16, and the capacitors CDAk-1 to CDA1 smaller than that are applied. A voltage Vref_l is applied to the terminals by changeover switches SW1k-1 to SW11. In the redundant comparison, first, the voltage applied to the terminal of the largest capacitor CDAk is switched from Vref_h to Vref_l by the switch SW1k. As a result, the same state as when the reference voltage Vref output from the local DA conversion circuit 14 is lowered is set. In this state, the comparator 12 operates to perform comparison, and then, according to the output of the comparator, the voltage applied to the terminals of the capacitors CDAk-1 to CDA1 is set to Vref_h or Vref_l, thereby performing a redundant comparison. .

  According to a trial calculation by the present inventor, an SN ratio of 3 dB is improved by executing one redundancy comparison sequence after a normal AD conversion, and an SN ratio of 6 dB is executed by executing the redundancy comparison sequence three times, and the redundancy comparison sequence is executed 15 times. It was found that the SN ratio could be improved by 12 dB. Therefore, if the allowable deviation of the AD conversion output is 2 codes, +3 redundant comparisons are performed, if the allowable deviation is 3 codes, +6 redundant comparisons are performed, and if the allowable deviation is 4 codes, +15 times are compared. It is desirable to perform a redundant comparison. Even when the redundant comparison sequence is executed 15 times, the change in the reference voltage is small and the settling time is shortened in the comparison of the lower bits, so that the comparison time can be made shorter than usual and the value of k is n. Since it can be made relatively small compared to the value, the conversion time does not increase drastically.

  Further, regarding the number of comparisons in each redundant comparison sequence, that is, the number of conversion bits of the sub DA conversion circuit 16, if the error generation range of the output code of AD conversion = target value ± 2LSB, the conversion result in normal AD conversion is shifted. Therefore, it is preferable to make correction within a range of ± 4LSB, and a 3-bit redundant comparison (k = 3) may be used.

  As described above, in the present embodiment, after the normal AD conversion, the conversion result is taken over and the low-order bit redundancy comparison is performed a plurality of times and averaged to obtain the result in the center of the distribution of FIG. An output code near the end can be obtained, and a value obtained by correcting an error due to switching noise of the comparator can be obtained.

  When the AD conversion circuit is mounted on an LSI such as a microprocessor having a CPU (central processing unit), a register capable of setting the values of k and m by the CPU is provided, and the control circuit 15 However, it is also possible to configure the sub DA conversion circuit 16 to operate with the number of comparisons corresponding to the set value of this register.

  FIG. 2 shows a second embodiment of the successive approximation AD converter circuit according to the present invention. In this embodiment, a DA conversion circuit combining a charge distribution type and a resistance voltage division type is used as a local DA conversion circuit, and reference voltages (Vref_h, Vref_l) applied to capacitors (CDA1 to CDAk) in the sub DA conversion circuit. Is extracted from the voltage divided by the ladder resistor RLD of the local DA conversion circuit 14 and used.

  The local DA converter circuit 14 of FIG. 2 has a capacitor array including weighted capacitors C0, C1,... Cn-1 having a weight of 2 to the power of n, and a ladder resistor RLD including series resistors R1 to Rn. . The resistors R1 to Rn are normally set to the same resistance value. One terminals of the weight capacitors C0, C1,... Cn-1 are connected in common and connected to the input terminal of the first-stage inverter INV1 of the comparator 12.

  One of the reference voltages Vref_h, Vref_l or the input voltage Vin is applied to the other terminal of C1,... Cn-1 among the weight capacitors C0, C1,. Made possible. In addition, either the selection voltage of the ladder resistor RLD or the input voltage Vin can be applied to the other terminal of the weight capacitor C0 by the changeover switch SW0. Note that the sum of the weighting capacitors C0, C1,... Cn-1 corresponds to the sampling capacitor Cs in FIG. A ground potential may be used as the reference voltage Vref_l.

  Although not shown, the ladder resistor RLD is provided with a switch for taking out the potential of each node of the ladder resistor. In this embodiment, the change-over switches SW0 to SWn-1 are controlled by the upper bits of the successive approximation register 13, and the ladder resistor switch is controlled by the lower bits of the register 13. Specifically, when the potential of the ladder resistor RLD is used, one of the ladder resistor switches is turned on by the lower bit of the register 13, and the changeover switches SW0 to SWn-1 operate only on SW0. However, SW1 to SWn-1 do not operate.

  Further, when the weight capacitors C0, C1,... Cn-1 are used, the reference voltage Vref_h or Vref_l is transmitted to the capacitor C0 via the changeover switch SW0. SW1 to SWn-1 are connected to the Vin input terminal during sampling, and are connected to the reference voltage Vref_h or Vref_l according to the higher-order bit of the register 13 during comparison determination.

  The connection terminals of the changeover switches SW0 to SWn-1 are determined according to the value of the successive approximation register 13 and the sampling clock. FIG. 2 shows the state of each switch during the sampling period, and all the change-over switches SW0 to SWn-1 are connected to the input voltage Vin side, and the corresponding weight capacitors C0, C1,. An input voltage Vin is applied to the other terminal, and a charge corresponding to Vin is charged.

  In the comparison determination period (hold period), the changeover switches SW1 to SWn-1 are connected to either Vref_h or Vref_l according to the value of the successive approximation register at that time. The changeover switch SW0 is a selection voltage of the ladder resistor RLD, and which node voltage is selected is determined by the value of the successive approximation register.

  In the local DA converter circuit, any reference voltage of Vref_h and Vref_l is applied to the other terminal of the weight capacitors C0, C1,. Charges corresponding to the potential difference from the input voltage Vin applied immediately before remain, which is distributed among C0, C1,... Cn-1, and the voltage generated at the common connection node is the input terminal of the inverter INV1 as a comparator To be supplied.

  In the comparator, the switch S1 is turned on during the sampling period and the input / output of the inverter INV1 is short-circuited, so that the input potential and the output potential become equal to the logical threshold value VLT of the inverter. As a result, the input analog voltage Vin is sampled to the weighting capacitors C0, C1,. That is, a charge corresponding to the potential difference between VLT and Vin is charged.

  At the time of comparison determination, as described above, in the local DAC, the changeover switches SW0 to SWn-1 are connected to the reference voltage Vref_h or Vref_l according to the value of the register 13. As a result, a potential corresponding to the potential difference between the input analog voltage sampled immediately before and the comparison voltage determined by the state of the changeover switches SW0 to SWn-1 is supplied to the input terminal of the inverter INV1. At this time, since the switch S1 is turned off and the input terminal and the output terminal of the inverter INV1 are disconnected, the inverter works as an amplifier to amplify and output the input potential.

  In the resistive voltage dividing DA converter, the reference voltage Vref_h is applied to one terminal of the ladder resistor RLD and the reference voltage Vref_l is applied to one terminal of the ladder resistor RLD, and the potential difference is divided by the resistance ratio. Such a voltage is taken out by a switch controlled by a lower bit of the register 13.

As described above, by combining the resistive dividing type in charge distribution type, the DA converter, for example, 10 bits, required capacity of 2 ¹⁰ times the minimum capacitance C0 in the case of only the charge distribution type (about 1000 times) However, it is only necessary to provide a capacitor ²⁵ times (32 times) C0 and 32 resistors, which is advantageous in terms of area.

  Furthermore, in this embodiment, any voltage generated by the ladder resistor RLD is selected by a switch (not shown) and applied to the capacitors (CDA1 to CDAk in FIG. 1). The voltage to be applied can be given a degree of freedom, and it is not necessary to provide a circuit for generating a voltage to be applied only for the sub DA conversion circuit 16, and there is an advantage that the area can be reduced.

  Although the invention made by the present inventor has been specifically described based on the embodiment, the present invention is not limited to the above embodiment. For example, in the above embodiment, a comparator in which three stages of CMOS inverters are cascade-connected is shown, but two inverters may be cascade-connected, or four inverters may be cascade-connected.

  In the above embodiment, the smallest of the weighted n capacitors in the local DA converter circuit 14 and the smallest of the weighted k capacitors in the sub DA converter circuit 16 are the same. The capacity value of the maximum weighted capacity in the sub DA conversion circuit 16 is set to the same capacity value as the minimum weighted capacity in the local DA conversion circuit 14. It is also possible to set. In that case, in addition to performing the redundant comparison operation for the error correction function, the comparison result using the sub DA conversion circuit 16 is obtained from the output code obtained by the normal AD conversion using the local DA conversion circuit 14. It is also possible to output it as a digital output with an increased number of conversion bits added to the lower order.

  Further, in the above embodiment, the CMOS inverter is used as the amplification stage constituting the chopper type comparator. However, instead of the CMOS inverter, a single-ended differential amplifier circuit or a differential input-differential output amplifier circuit is used. May be used. Further, a feedback capacitor may be connected between the input terminal and the output terminal of the CMOS inverter so that the gain of the CMOS inverter can be adjusted.

  Furthermore, in the above-described embodiment, it has been described that the redundancy comparison by the sub DA conversion circuit 19 is performed after the normal AD conversion using the local DA conversion circuit 14, but the case where the input voltage hardly changes is the target. Uses the previous AD conversion result to set the output of the local DA conversion circuit 14 to omit the normal AD conversion and execute only the comparison operation using the sub DA conversion circuit 16 to obtain the AD conversion result. May be.

  In addition, weighting is performed on the results of redundant comparisons that are executed multiple times, and averaging processing is performed by removing those that have been significantly shifted by applying a median filter to the results of multiple times of redundant comparisons. May be. Further, the averaging process of the redundancy comparison result is performed more than once, the averaging process is further performed, the averaging process result is weighted, the averaging process is performed, or a filter is applied. May be. When the AD conversion circuit is mounted on an LSI (Large Scale Semiconductor Integrated Circuit) such as a microprocessor having a CPU, the averaging process and the filter process are performed by CPU software processing. It is also possible.

11 Sample / Hold Circuit 12 Comparator 13 Successive Approximation Register 14 Local DA Converter 15 Control Circuit 16 Sub DA Converter SS1, SS2 Sampling Switch S1, S2, S3 Shorting Switch Cs Sampling Capacitor C2, C3 Coupling Capacitor RLD Ladder Resistor C0 〜Cn-1 Weight capacity SW0 to SWn-1 selector switch

Claims (6)

A comparison circuit that includes a plurality of amplification stages connected in cascade via a coupling capacitor, determines the magnitude of the input analog voltage and the comparison voltage, a register that sequentially captures and holds the determination result of the comparison circuit, and a value of the register A successive approximation AD converter circuit comprising: a local DA converter circuit that converts the voltage into a voltage and generates the comparison voltage;
A switch capable of switching between one or more capacitors having one terminal connected to the input terminal of the first amplification stage of the comparison circuit and a voltage applied to the other terminal of the capacitor based on the output of the comparison circuit A sub-DA conversion circuit having means;
A control signal for the sub DA converter circuit is generated in accordance with the output of the comparator circuit, and the comparator circuit performs a redundant comparison and averages the output of the comparator circuit to generate a correction signal for the register value. Possible control circuit,
And a redundant comparison operation using the sub DA conversion circuit using the conversion result as a start value after a normal AD conversion operation using the local DA conversion circuit. Comparison type AD converter circuit.   The control circuit performs a redundancy comparison using the sub DA conversion circuit a plurality of times, and performs an averaging process between a result of a normal AD conversion operation using the local DA conversion circuit and a result of the plurality of redundancy comparisons The successive approximation AD converter circuit according to claim 1, wherein the register value can be changed according to the result of the averaging process.   The local DA conversion circuit includes two or more n capacitors weighted by a power of 2 and switch means provided corresponding to each of the capacitors, and the sub DA conversion circuit has a power of 2 2 or more weighted k capacitors, and switch means provided corresponding to each capacitor, wherein k is smaller than n, and the smallest of the n capacitors, and k 3. The successive approximation AD converter circuit according to claim 1, wherein the smallest one of the capacitors has the same capacitance value. The local DA converter circuit includes a capacitor array including a plurality of weight capacitors, one terminal of which is commonly connected to an input terminal of the comparison circuit, and an input analog voltage or a second capacitor connected to the other terminal of the plurality of weight capacitors. A changeover switch circuit capable of applying one reference voltage or a second reference voltage;
Ladder resistance provided between a first node to which the first reference voltage is applied and a second node to which the second reference voltage is applied, and selection means for extracting a potential from any node of the ladder resistance And comprising
The changeover switch circuit determines a connection state according to the values of a plurality of bits on the upper side of the register, applies an input analog voltage to the other terminal of the plurality of weight capacitors in a first period, Applying the first reference voltage or the second reference voltage to the other terminal of the plurality of weight capacitors according to the value of the first register during a period;
The selection means determines a potential to be extracted according to the values of a plurality of bits on the lower side of the register, and the potential extracted by the selection means is calculated by the changeover switch circuit during the second period. Is applied to the terminal with the smallest capacitance value,
2. The voltage applied to the capacitor by the switch means in the sub DA conversion circuit is configured to be extracted from any node of the ladder resistor of the local DA conversion circuit. The successive approximation AD converter circuit according to any one of to 3. The comparison circuit is
Having a CMOS inverter as the amplification stage, a switch element provided between the input and output terminals of each CMOS inverter, and a coupling capacitor provided between the CMOS inverters,
In the first period, the switch element is turned on, a voltage corresponding to the logic threshold of the CMOS inverter is applied to one terminal of the sampling capacitor, and an input analog voltage is taken in based on the voltage,
In a second period, the sampling capacitor is charged with a charge corresponding to the potential difference between the input analog voltage and the comparison voltage, and the switch element is turned off to amplify the potential of the sampling capacitor by the CMOS inverter The successive approximation AD converter circuit according to claim 1, wherein the successive approximation AD converter circuit is configured as described above.   6. A successive approximation AD converter circuit according to claim 1; a CPU; and a register capable of setting the number of comparison operations by the CPU; and the control circuit according to a set value of the register A semiconductor integrated circuit configured to control the sub DA conversion circuit.