JP2010251986A - Analog-to-digital converter - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress degradation of performance which is caused by variations in clocks in respective comparators. <P>SOLUTION: An A/D converter 1 includes a plurality of comparators Cmp, and a first switch SWsd which is provided on a common path to supply a reference voltage VCM to the comparators Cmp. One end of a sampling capacity Cc of respective comparators Cmp is applied with an analogue input signal Vin through a second switch SWin during a sampling period, and is applied with a corresponding reference voltage Vref through a third switch SWref during a comparison period. The other end of the sampling capacity Cc is applied with a reference voltage VCM through a fourth switch SWs and common first switch SWsd during the sampling period. Here, during a transition period between the sampling period and comparison period, after the first switch SWsd is turned off, the second and fourth switches SWin and SWref of the comparators Cmp are turned off but the third switch SWref is turned on. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to an analog / digital converter that converts an input analog signal into a digital signal by comparing it with a plurality of reference signals. For example, the present invention relates to a flash or subranging analog / digital converter.

  As a typical example of an analog / digital (A / D) converter, a parallel A / D converter called a flash method is known (for example, Japanese Patent Laid-Open No. 60-10000833 (Patent Document). 1)). In a flash A / D converter, an analog input signal is compared simultaneously with a number of reference levels. In the case of an A / D converter having an n-bit digital output, there are 2 n −1 reference levels, and there are the same number of comparators. For example, in the case of an 8-bit A / D converter, there are 255 reference levels corresponding to incremental steps between zero and full scale input values, and 255 comparators. When an input signal is sent to these comparators, a comparator having as input a reference level lower than the input signal generates an output signal of logic level “1”, for example. A comparator having as its input a reference level greater than the input signal generates an output signal of logic level “0” which is the opposite binary state. The desired digital output is given as the sum of the individual comparator outputs.

  For the purpose of reducing the number of comparators of the parallel type A / D converter, there is a series / parallel type A / D converter called a sub-ranging system (for example, Japanese Patent Laid-Open No. 63-299615). See Patent Document 2)). In the sub-ranging A / D converter, when the conversion is started, the upper bits are first determined. Then, after the upper bits are determined, the comparator group for determining the lower bits and the resistor ladder for generating the reference voltage are connected by the matrix switch, and the lower bits are converted. Therefore, when performing a total of m + n bits of A / D conversion with m bits for the upper bits and n bits for the lower bits, a series-parallel A / D converter uses 2 m-1 comparators for the upper bits. And 2 n-1 comparators for the lower bits. Compared to an m + n-bit parallel A / D converter that requires 2 (m + n) power-1 comparators, a smaller number of comparators are required.

Japanese Patent Laid-Open No. 60-1000083 JP-A 63-299615

  As described above, the main element circuit constituting the flash or sub-ranging A / D converter is a comparator, and a large number of comparators are basically arranged in an array. The operation of these comparators is controlled by a clock. In this case, since the clock is supplied to each comparator through a wiring that runs through the array of comparators, the clock delay is large due to the parasitic resistance and parasitic capacitance of the clock wiring. In addition, the timing at which the switch is turned on or off may vary due to variations in the characteristics of the switch elements inside the comparator.

  The analog input signal of the A / D converter is commonly applied to all the comparators. At this time, if the clock timing varies, the timing at which the input signal is sampled by each comparator varies. As a result, an error occurs between the sampled signals, and the error becomes an error of the A / D converter as it is, and degrades the performance of the A / D converter.

  An object of the present invention is to suppress performance deterioration due to clock variation in each comparator in an A / D converter provided with a plurality of comparators operating in parallel.

  According to one embodiment of the present invention, a reference voltage generation circuit that generates a plurality of first reference voltages, a plurality of comparators respectively corresponding to the plurality of first reference voltages, and a first switch are provided. An analog / digital converter is provided. Each comparator receives a corresponding first reference voltage, a first analog voltage signal to be digitally converted, and a common reference voltage. The first switch is provided on a common path for supplying a reference voltage to each of the plurality of comparators, is in a conductive state in the sample period, is in a non-conductive state in the comparison period, and is connected between the sample period and the comparison period. During the transition period, the conductive state is switched to the non-conductive state. Here, each comparator includes second to fourth switches, a first capacitive element, and an amplifier. The second and third switches are conductive during the sample period, are non-conductive during the comparison period, and are non-conductive after the first switch is non-conductive during the transition period. The fourth switch is non-conductive during the sample period, is conductive during the comparison period, and is conductive after the first switch is non-conductive during the transition period. The first capacitor element receives, at one end, a first analog voltage signal when the second switch is in a conductive state and a corresponding first reference voltage when the fourth switch is in a conductive state. At the end, the reference voltage is received when the third switch is in a conducting state. The amplifier receives the voltage at the other end of the first capacitor during the comparison period.

  According to this embodiment, a common first switch is provided in the upper hierarchy of the switches of each comparator, and the sampling timing of the first analog voltage signal to be digitally converted is determined by the first switch. . As a result, since the sample timings of all the comparators are aligned, it is possible to suppress the performance deterioration due to the clock variation in each comparator.

It is a block diagram which shows the structure of the A / D converter 1 by Embodiment 1 of this invention. FIG. 2 is a circuit diagram illustrating a configuration of a comparator array 10 in FIG. 1. FIG. 3 is a diagram for explaining the operation of each comparator Cmp_i in FIG. 2. FIG. 6 is a timing diagram of internal clock signals φ1d, φ1, and φ2. FIG. 4 is a diagram illustrating input / output characteristics of an amplifier Amp_i in FIG. 3. It is a figure for demonstrating the dispersion | variation in the sample timing in the conventional A / D converter. 4 is a diagram for explaining sample timing of the A / D converter 1; FIG. It is a block diagram which shows the structure of the A / D converter 2 by Embodiment 2 of this invention. It is a circuit diagram which shows the structure of each comparator Cmp_i of FIG. FIG. 10 is a diagram illustrating input / output characteristics of the amplifier Amp_i in FIG. 9. It is a circuit diagram which shows the structure of the A / D converter 3 by Embodiment 3 of this invention. It is a block diagram which shows the structure of the A / D converter 4 by Embodiment 4 of this invention. It is a block diagram which shows the structure of the A / D converter 5 by Embodiment 5 of this invention. It is a circuit diagram which shows an example of a structure of the ladder resistance 21 of FIG. FIG. 14 is a timing chart showing the operation of each clock signal and sub A / D converter of FIG. 13. It is a block diagram of the microcontroller 30 for a digital control power supply of a certain specification. It is a block diagram of the signal processing apparatus 50 for HDD of a certain specification.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The same or corresponding parts are denoted by the same reference numerals, and description thereof will not be repeated.

[Embodiment 1]
FIG. 1 is a block diagram showing a configuration of an A / D converter 1 according to Embodiment 1 of the present invention. Referring to FIG. 1, an A / D converter 1 includes a comparator array 10 in which n comparators (comparators) Cmp_1 to Cmp_n are arranged in an array, a reference voltage generation circuit 11, and an internal clock generation circuit 12. And a pre-encoder 14, an encoder 15, and a switch SWsd (first switch).

  The A / D converter 1 is a flash A / D converter that generates m-bit digital codes D_1 to D_m by digitally converting an analog input signal Vin. In order to realize m-bit resolution, the comparator array 10 includes n (n = 2 to the power of m-1) comparators Cmp_1 to Cmp_n (also collectively referred to as comparators Cmp when generically referred to or unspecified). including.

  Normally, in order to reduce the influence of noise from the power supply and ground, a differential analog input signal is input to the A / D converter, and each comparator Cmp is configured to handle a differential signal. . However, in the following, in order to simplify the configuration of the present invention, a case where a single analog input signal Vin is input will be described. A differential A / D converter will be described in the second embodiment.

  The reference voltage generation circuit 11 of FIG. 1 includes n + 1 resistance elements R_1 to R_n + 1 connected in series, and equally divides the external power supply voltage (upper limit voltage: VRT, lower limit voltage: VRB) for each constant step width. N reference voltages Vref_1 to Vref_n are output. Reference voltages Vref_1 to Vref_n (also collectively referred to as reference voltage Vref when indicating generically or indicating an unspecified one) correspond to comparators Cmp_1 to Cmp_n, respectively.

  Each comparator Cmp samples the analog input signal Vin and compares the sampled analog input signal Vin with a corresponding reference voltage Vref. The result of the size comparison is output from each of the comparators Cmp_1 to Cmp_n as signals SC_1 to SC_n (when collectively referred to as a signal SC when indicating an unspecified one).

  For example, an arbitrary i-th (i is an integer of 1 to n) comparator Cmp_i outputs an H-level signal SC_i when the input signal Vin exceeds the reference voltage Vref_i, and the input signal Vin is equal to or less than the reference voltage Vref_i. In this case, an L level signal SC_i is output. In this case, if the magnitude of the input signal Vin is larger than the zth reference voltage Vref_z and smaller than the z + 1th reference voltage Vref_z + 1, all the output signals SC of the first to zth comparators Cmp are H The output signals SC of the (z + 1) -th to n-th comparators Cmp are all at the L level. Thus, the output signals SC_1 to SC_n of the comparator array 10 have a pattern in which 1 continues to the signal SC corresponding to the input signal level, and thereafter 0 continues, and is called a so-called thermometer code.

  The internal clock generation circuit 12 receives the external clock CLK and generates internal clock signals φ1, φ2, and φ1d that are used to control the timing of sampling and signal comparison of each comparator Cmp. Internal clock signals φ1 and φ2 are output to comparator array 10, and internal clock signal φ1d is output to switch SWsd.

  The switch SWsd is provided on a common path for supplying the reference voltage VCM to each comparator Cmp. As the switch SWsd, for example, a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) is used. In the first embodiment, when the internal clock signal φ1d for controlling the switch SWsd is at the H level, the switch SWsd is in the conductive state (on state), and when the internal clock signal φ1d is at the L level, the switch SWsd is in the nonconductive state (off state). ). The function of the switch SWsd will be described later with reference to FIGS.

  The pre-encoder 14 calculates signals SC_1 to SC_n based on the thermometer code output from the comparator array 10 to generate new signals SP_1 to SP_n. Specifically, when the output signals SC_1 to SC_z from the z-th comparator array 10 are at the H level and the z + 1-th and subsequent output signals SC_z + 1 to SC_n are at the L level, the z-th output of the pre-encoder 14 is reached. The output signal SP_z becomes H level, and the other output signals become L level.

  The encoder 15 outputs m-bit digital codes D_1 to D_m corresponding to the output signals SP_1 to SP_n of the pre-encoder 14. In this specification, the pre-encoder 14 and the encoder 15 are collectively referred to as an arithmetic circuit 13.

Hereinafter, the configuration of the comparator array 10 will be described in more detail.
FIG. 2 is a circuit diagram showing a configuration of the comparator array 10 of FIG. Referring to FIG. 2, each comparator Cmp_i (hereinafter, i is an integer from 1 to n) includes a sampling capacitor Cc_i (first capacitor element), a switch SWin_i (second switch), and a switch SWs_i (first switch). 3 switches), a switch SWref_i (fourth switch), an amplifier Amp_i, and a latch circuit Lch_i. The sampling capacitor Cc_i and the three switches SWin_i, SWref_i, and SWs_i constitute a capacitor unit CA_i.

  As the switches SWin_i, SWref_i, and SWs_i, for example, MOSFETs can be used. Switching of the switches SWin_i and SWs_i is controlled by an internal clock signal φ1. In the first embodiment, the switches SWin_i and SWs_i are turned on when the internal clock signal φ1 is at the H level, and the switches SWin_i and SWs_i are turned off when the internal clock signal φ1 is at the L level. The switching of the switch SWref_i is controlled by the internal clock signal φ2. In the first embodiment, the switch SWref_i is turned on when the internal clock signal φ2 is at the H level, and the switch SWref_i is turned off when the internal clock signal φ2 is at the L level.

  In each comparator Cmp_i, the switch SWin_i is connected between a common input node of the analog input signal Vin and a terminal (node NC_i) on the input side of the sampling capacitor Cc_i. Therefore, the common analog input signal Vin is input to the node NC_i of the comparator Cmp_i when the switch SWin_i is in the ON state.

  In each comparator Cmp_i, the switch SWref_i is connected between the output node of the corresponding reference voltage Vref_i among the output nodes of the reference voltage generation circuit 11 of FIG. 1 and the input side terminal (node NC_i) of the sampling capacitor Cc_i. Is done. Therefore, the corresponding reference voltage Vref_i is input to the node NC_i of the comparator Cmp_i when the switch SWref_i is on.

  In each comparator Cmp_i, the switch SWs_i is connected between a wiring Lc that supplies the reference voltage VCM to the comparators Cmp_1 to Cmp_n and a terminal (node NA_i) on the output side of the sampling capacitor Cc_i. Here, a switch SWsd is provided on a common path for supplying the reference voltage VCM to the comparators Cmp_1 to Cmp_n. Therefore, the reference voltage VCM is input to the node NA_i of the comparator Cmp_i when both the common switch SWsd and the switch SWs_i provided for each comparator Cmp_i are on.

  The amplifier Amp_i amplifies the voltage at the node NA_i and outputs it to the latch circuit Lch_n. In the case of the first embodiment, the amplifier Amp_i is an inverting amplifier circuit that outputs an L level voltage when the input voltage exceeds the threshold voltage, and outputs an H level voltage when the input voltage is lower than the threshold voltage.

  The latch circuit Lch_i is a circuit that holds the output of the amplifier Amp_i for a predetermined time. The output of the latch circuit Lch_i is input to the arithmetic circuit 13 as the output signal SC_i described above.

Next, the operation of the comparator Cmp_i will be described.
FIG. 3 is a diagram for explaining the operation of each comparator Cmp_i in FIG. As shown in FIG. 3, in the following description, the parasitic capacitance Cs_i of the node NA_i is also considered.

FIG. 4 is a timing diagram of internal clock signals φ1d, φ1, and φ2.
Referring to FIGS. 3 and 4, first, internal clock signal φ2 becomes L level at time t1, and both internal clock signals φ1d and φ1 become H level at subsequent time t2. As a result, the switches SWin_i and SWs_i and the switch SWsd are turned on, so that the analog input signal Vin is applied to the input side terminal (node NC_i) of the sampling capacitor Cc_i, and the reference voltage VCM is applied to the output side terminal (node NA_i). Is applied. The state where the internal clock signal φ2 is at the L level and the internal clock signals φ1d and φ1 are both at the H level continues until the next time t3. A period from time t2 to time t3 is a sample period for sampling the analog input signal Vin.

  In the sample period, the charge Q_a_i represented by the following formula (1) is accumulated in the output side terminal (node NA_i) of the sampling capacitor Cc_i. However, in the following equation (1), the capacitance value of the sampling capacitor Cc_i is Cc, and the capacitance value of the parasitic capacitance Cs_i of the node NA_i is Cs.

Q_a_i = Cc × (VCM − Vin) + Cs × VCM… (1)
At time t3, the internal clock signal φ1d changes to the L level before the internal clock signal φ1. As a result, the node NA_i of each comparator Cmp_i is in a high impedance state while the sampling capacitors Cc_1 to Cc_n of all the comparators Cmp_1 to Cmp_n are connected to the common line Lc. At the node NA_i of each comparator Cmp_i, the charge Q_a_i corresponding to the input signal Vin applied immediately before this is held. That is, the analog input signal Vin is sampled at this timing.

  At the next time t4, the internal clock signal φ1 changes to the L level, so that the switches SWin_i and SWs_i are turned off. Subsequently, at time t5, the internal clock signal φ2 changes to the H level, so that the switch SWref_i is turned on. As a result, the corresponding reference voltage Vref_i is applied to the input terminal (node NC_i) of the sampling capacitor Cc_i. The period in which the internal clock signals φ1d and φ1 are at the L level and the internal clock signal φ2 is at the H level continues until time t6, and the period from time t5 to t6 is the comparison period. Further, the period from time t3 to time t5 is a transition period between the sample period and the comparison period.

  In the comparison period, the charge Q_a_i corresponding to the input signal Vin applied immediately before time t3 is held in the node NA_i. Therefore, the voltage V_a_i of the node NA_i and the charge Q_a_i have the relationship of the following equation (2).

Q_a_i = Cc × (V_a_i − Vref_i) + Cs × V_a_i… (2)
From the above equations (1) and (2), the voltage V_a_i of the node NA_i has a value as in the following equation (3).

V_a_i = VCM + Cc / (Cc + Cs) x (Vref_i-Vin) (3)
The amplifier Amp_i amplifies the voltage V_a_i expressed by the above equation (3) during the comparison period. Here, in the case of the first embodiment, the reference voltage VCM of the above equation (3) is set equal to the threshold voltage of the amplifier Amp_i.

  FIG. 5 is a diagram illustrating input / output characteristics of the amplifier Amp_i in FIG. Referring to FIG. 5, when the input voltage IN_i of the amplifier Amp_i is equal to the reference voltage VCM, the output voltage OUT_i of the amplifier Amp_i becomes a neutral voltage Vm between the H level and the L level. In other words, the reference voltage VCM is set to the threshold voltage of the amplifier Amp_i so that the output voltage OUT_i becomes the neutral voltage Vm. When the input voltage IN_i exceeds the reference voltage VCM, the output voltage OUT_i becomes L level (also referred to as “L”) smaller than Vm. When the input voltage IN_i is less than the reference voltage VCM, the output voltage OUT_i is larger than Vm. H level (also described as “H”).

The amplifier Amp_i and the latch circuit Lch_i in FIG. 3 output an L-level or H-level output signal SC_i depending on whether the voltage at the node NA_i is higher or lower than the reference voltage VCM. Therefore, as is clear from the above equation (3),
When Vref_i <Vin, SC_i = “H” (4)
When Vref_i> Vin, SC_i = “L” (5)
It becomes.

  Referring to FIGS. 3 and 4 again, latch circuit Lch_i holds the output of amplifier Amp_i immediately before time t6 when the comparison period ends. The procedure after time t6 is the same as that after time t1.

  Next, the effect of the A / D converter 1 of Embodiment 1 when compared with the prior art will be described.

  In the case of a conventional A / D converter, the switch SWsd of FIG. 3 is not provided. Therefore, in the case of the conventional A / D converter, in each comparator Cmp_i in FIG. 3, the switch SWs_i (i is an integer of 1 to n) is more than the switch SWin_i in the transition period in which the sample period shifts to the comparison period. It is controlled so as to be turned off first. Due to this control, the internal clock signal for the switch SWs_i changes from the H level to the L level before the internal clock signal for the switch SWin_i. Alternatively, it may be considered that the switch SWs_i is controlled by the internal clock signal φ1d shown in FIG. 4 and the switch SWin_i is controlled by the internal clock signal φ1.

  When the switch SWs_i is turned off, the node NA_i of each comparator Cmp_i enters a high impedance state, and thus the charge Q_a_i corresponding to the input signal Vin applied immediately before is held in the sampling capacitor Cc_i. That is, the analog input signal Vin is sampled at this timing.

  Ideally, all the timings at which the internal clock signal supplied to each comparator Cmp_i changes from “H” to “L” should be common. However, in reality, a delay occurs in the clock due to the parasitic resistance and parasitic capacitance of the clock wiring. Furthermore, the sampling timing in each comparator Cmp_i also shifts due to variations in the threshold value Vth of the MOS transistor elements constituting the switch SWs_i of each comparator Cmp_i.

  FIG. 6 is a diagram for explaining variation in sample timing in a conventional A / D converter. Referring to FIG. 6, when the timing of the internal clock signal for controlling the switch SWin_i is shifted by Δt between the x-th comparator Cmp_x (time t11) and the y-th comparator Cmp_y (time t12), The analog input signal Vin changes. As a result, an error Verr occurs between the analog signal Vin_x sampled by the xth comparator Cmp_x and the analog signal Vin_y sampled by the yth comparator Cmp_y. The error Verr increases as the time difference Δt increases or as the frequency of the analog input signal Vin increases.

  Since each comparator Cmp_i performs the next comparison operation while including this error generated at the time of sampling, the error directly affects the output signal SC_i of the comparator Cmp_i. Therefore, a large error is included in the digital codes D_1 to D_m output from the arithmetic circuit 13 using the output signal SC_i, and the performance of the A / D converter is greatly deteriorated. Due to such error characteristics, as the A / D converter becomes faster or more accurate, the accuracy degradation of the conventional A / D converter becomes larger.

  In the flash method and the sub-ranging method, the scale of the comparator array is larger than in other methods, so that the wiring of the internal clock signal becomes longer, the parasitic resistance and the parasitic capacitance increase, and the delay increases. Even if the wiring length can be shortened, the variation in the threshold value Vth of the transistors constituting the switch is determined by the manufacturing apparatus, so there is a lower limit, and it is impossible to eliminate the clock delay. Therefore, in the flash method or sub-ranging method in which the sample operation is performed by a plurality of comparators, this problem of variation in sample timing is unavoidable.

  On the other hand, in the case of the A / D converter 1 of the first embodiment, the sampling timing is determined by the internal clock signal φ1d in all the comparators Cmp. The switch SWsd controlled by the internal clock signal φ1d exists only in one place. Therefore, the delay of the clock due to the parasitic resistance and parasitic capacitance of the clock wiring and the variation in the threshold value Vth of the transistor elements constituting the switch do not affect the sampling timing.

  Also in the case of the first embodiment, the ON / OFF timing of the switch SWs_i existing in each comparator Cmp is the same as that of the conventional circuit, the delay due to the parasitic resistance and the parasitic capacitance of the clock wiring, and the transistor constituting the switch SWs_i. It is affected by variations in threshold value Vth. However, since the charge Q_a_i accumulated in the node NA_i of each comparator Cmp_i is held after the switch SWsd is turned off, an error does not occur in the sampling timing due to the timing deviation of the switch SWs_i.

  FIG. 7 is a diagram for explaining sample timing of the A / D converter 1. Referring to FIG. 7, in the case of the first embodiment, the timing at which internal clock signal φ1 changes to the L level is the xth comparator Cmp_x (time t11) and the yth comparator Cmp_y (time t12). Assume that Δt is shifted. In this case, the switch SWsd is turned off at time t10 before the internal clock signal φ1 changes to the L level. Accordingly, since the analog input Vin_i sampled immediately before the switch SWsd is turned off is common to all the comparators Cmp, the sampling error due to each comparator Cmp is basically eliminated. As a result, the output signal SC_i of each comparator Cmp_i eliminates the influence due to the deviation of the on / off timing of the switch SWs_i, thereby improving the performance of the A / D converter.

[Embodiment 2]
FIG. 8 is a block diagram showing the configuration of the A / D converter 2 according to the second embodiment of the present invention. The A / D converter 2 in FIG. 8 digitally converts the differential analog input signal Vin (Vinp, Vinn) in order to reduce the influence of noise from the power supply and the ground, and outputs an m-bit digital code D_1 to D_1. D_m is output. Similar to the first embodiment, the A / D converter 2 includes a comparator array 10A in which n comparators (comparators) Cmq_1 to Cmq_n are arranged in an array, a reference voltage generation circuit 11A, and an internal clock. A generation circuit 12, a pre-encoder 14, an encoder 15, and a switch SWsd (first switch) are included. Hereinafter, differences from the A / D converter 1 according to the first embodiment will be mainly described, and the same or corresponding parts may be denoted by the same reference symbols and description thereof may not be repeated.

  The reference voltage generation circuit 11A of FIG. 8 generates differential reference voltages Vrefp_i and Vrefn_i (where i is an integer between 1 and n, and n = 2 to the mth power-1). Specifically, the reference voltage generation circuit 11A includes n + 1 resistance elements Rp_1 to Rp_n + 1 connected in series. The reference voltage generation circuit 11A equally divides the external power supply voltage (absolute value of the upper limit voltage: VRT, absolute value of the lower limit voltage: VRB) by these resistance elements Rp_1 to Rp_n + 1, and outputs n pieces for each constant step width. Positive reference voltages Vrefp_1 to Vrefp_n are output. The reference voltage generation circuit 11A includes n + 1 resistance elements Rn_1 to Rn_n + 1 connected in series. The reference voltage generation circuit 11A equally divides the external power supply voltage (the absolute value of the upper limit voltage: VRB, the absolute value of the lower limit voltage: VRT) by these resistance elements Rn_1 to Rn_n + 1, and n pieces for each constant step width. Negative reference voltages Vrefn_1 to Vrefn_n are output. The generated positive and negative reference voltages Vrefp_i and Vrefn_i are output to the corresponding comparator Cmq_i.

  Each comparator Cmq_i (i = 1 to n) samples the positive analog input signal Vinp and the negative analog input signal Vinn. Each comparator Cmq_i has a difference (Vrefp_Vinn) between the analog input signals and a difference (Vrefp_i−Vrefn_i) between the corresponding positive reference voltage Vrefp_i supplied from the reference voltage generation circuit 11A and the corresponding negative reference voltage Vrefn_i. Compare size with. The comparison result is output from each comparator Cmq_i as a signal SC_i and is calculated by the pre-encoder 14 to generate a new signal SP_i. The encoder 15 receives this signal SP_i and outputs m-bit digital codes D_1 to D_m.

  FIG. 9 is a circuit diagram showing a configuration of each comparator Cmq_i in FIG. Referring to FIG. 9, each comparator Cmq_i (i is an integer of 1 to n) includes first and second capacitor units CAp_i and CAn_i, a differential amplifier Amq_i, and a latch circuit Lch_i.

  The first capacitor unit CAp_i receives a positive analog input signal Vinp, a corresponding positive reference voltage Vrefp_i, and a reference voltage VCM. The capacitor unit CAp_i includes a sampling capacitor Ccp_i (first capacitor element), a switch SWinp_i (second switch), a switch SWrefp_i (fourth switch), a switch SWap_i (third switch), a switch SWbp_i, and SWcp_i.

  As the switches SWinp_i, SWrefp_i, SWap_i, SWbp_i, and SWcp_i, for example, MOSFETs can be used. Switching of the switches SWinp_i, SWap_i, and SWbp_i is controlled by an internal clock signal φ1. In the second embodiment, these switches are turned on when internal clock signal φ1 is at the H level, and these switches are turned off when internal clock signal φ1 is at the L level. Further, switching of the switches SWrefp_i and SWcp_i is controlled by the internal clock signal φ2. In the case of the second embodiment, these switches are turned on when internal clock signal φ2 is at the H level, and these switches are turned off when internal clock signal φ2 is at the L level.

  In each capacitor unit CAp_i, the switch SWinp_i is connected between a common input node of the positive analog input signal Vinp and a terminal (node NCp_i) on the input side of the sampling capacitor Ccp_i. Therefore, the common positive analog input signal Vinp is input to the node NCp_i of the capacitor unit CAp_i when the switch SWinp_i is in the on state.

  Further, the switch SWrefp_i of each capacitor unit CAp_i is between the output node of the corresponding positive reference voltage Vrefp_i among the output nodes of the reference voltage generation circuit 11A of FIG. 8 and the input side terminal (node NCp_i) of the sampling capacitor Ccp_i. Connected to. Therefore, the corresponding positive reference voltage Vrefp_i is input to the node NCp_i of the capacitor unit CAp_i when the switch SWrefp_i is in the on state.

  The switch SWap_i of each capacitor unit CAp_i is connected between a wiring Lc that supplies the reference voltage VCM to the comparators Cmq_1 to Cmq_n and a terminal (node NAp_i) on the output side of the sampling capacitor Ccp_i. Here, a switch SWsd is provided on a common path for supplying the reference voltage VCM to the comparators Cmp_1 to Cmp_n. Therefore, the reference voltage VCM is input to the node NAp_i of the capacitor unit CAp_i when both the common switch SWsd and the switch SWap_i provided for each capacitor unit CAp_i are in the on state.

  The switch SWcp_i of each capacitor unit CAp_i is provided between the output-side terminal (node NAp_i) of the sampling capacitor Ccp_i and the non-inverting input terminal (node NBp_i) of the differential amplifier Amq_i. Therefore, the voltage V_ap_i of the output side terminal (node NAp_i) of the sampling capacitor Ccp_i is input to the non-inverting input terminal (node NBp_i) of the differential amplifier Amq_i when the switch SWcp_i is in the on state.

  The switch SWbp_i of each capacitor unit CAp_i is connected between the wiring Lc and the non-inverting input terminal (node NBp_i) of the differential amplifier Amq_i. Therefore, the reference voltage VCM is input to the non-inverting input terminal (node NBp_i) of the differential amplifier Amq_i when both the common switch SWsd and the switch SWbp_i provided for each capacitor unit CAp_i are in the on state. .

  The second capacitor unit CAn_i is provided in a pair with the first capacitor unit CAp_i and receives the negative analog input signal Vinn, the corresponding negative reference voltage Vrefn_i, and the reference voltage VCM. The capacitor unit CAn_i includes a sampling capacitor Ccn_i (second capacitor element), a switch SWin_i (fifth switch), a switch SWrefn_i (seventh switch), a switch SWan_i (sixth switch), a switch SWbn_i, and SWcn_i.

  Since the connection between the components of capacitor portion CAn_i is similar to that of capacitor portion CAp_i, description thereof will not be repeated. Specifically, in the above description of the capacitor unit CAp_i, the sampling capacitor Ccp_i and the switches SWinp_i, SWrefp_i, SWap_i, SWbp_i, and SWcp_i are replaced with the sampling capacitor Ccn_i and the switches SWinn_i, SWrefn_i, SWan_i, SWbn_i, and SWcn_i, respectively. Nodes NAp_i, NBp_i, and NCp_i are replaced with nodes NAn_i, NBn_i, and NCn_i, respectively. Positive analog input signal Vinp and positive reference voltage Vrefp_i are replaced with negative analog input signal Vinn and negative reference voltage Vrefn_i, respectively. Then, the non-inverting input terminal (node NBp_i) of the differential amplifier Amq_i is replaced with the inverting input terminal (node NBn_i) of the differential amplifier Amq_i.

  Next, the operation of the comparator Cmq_i will be described. Since the timings of the internal clock signals φ1d, φ1, and φ2 for controlling the switches constituting the comparator Cmq_i are the same as those in FIG. 4, the following description will be given with reference to FIGS.

  First, internal clock signal φ2 becomes L level at time t1 in FIG. 4, and both internal clock signals φ1d and φ1 become H level at subsequent time t2. A period from time t2 to the next time t3 is a sample period.

  In the sample period, since the switches SWinp_i, SWap_i, SWbp_i and the switch SWsd of the first capacitor unit CAp_i are turned on, the positive analog input signal Vinp is applied to the input side terminal (node NCp_i) of the sampling capacitor Ccp_i, The reference voltage VCM is applied to the output side terminal (node NAp_i) and the non-inverting input terminal (node NBp_i) of the differential amplifier Amq_i.

  At this time, the charge Q_ap_i shown in the following equation (6) is accumulated in the output side terminal (node NAp_i) of the sampling capacitor Ccp_i. However, in the following equation (6), the capacitance value of the sampling capacitor Ccp_i is Cc, and the capacitance value of the parasitic capacitance of the node NAp_i is Cs.

Q_ap_i = Cc × (VCM − Vinp) + Cs × VCM… (6)
Similarly, in the sample period, since the switches SWin_i, SWan_i, and SWbn_i of the second capacitor unit CAn_i are turned on, the negative analog input signal Vinn is applied to the input side terminal (node NCn_i) of the sampling capacitor Ccn_i, The reference voltage VCM is applied to the output terminal (node NAn_i) and the inverting input terminal (node NBn_i) of the differential amplifier Amq_i.

  At this time, the charge Q_an_i represented by the following equation (7) is accumulated in the output side terminal (node NAn_i) of the sampling capacitor Ccn_i. However, in the following equation (7), the capacitance value of the sampling capacitor Ccn_i is Cc, and the capacitance value of the parasitic capacitance of the node NAn_i is Cs.

Q_an_i = Cc × (VCM − Vinn) + Cs × VCM… (7)
At the next time t3, the internal clock signal φ1d changes to the L level before the internal clock signal φ1. As a result, the sampling capacitors Ccp_1 to Ccp_n and Ccn_1 to Ccn_n of all the comparators Cmq_1 to Cmq_n remain connected to the common line Lc, and the node NAp_i of the first capacitor unit CAp_i and the node NAn_i of the second capacitor unit CAn_i Becomes a high impedance state. As a result, the charge Q_ap_i corresponding to the input signal Vinp applied immediately before is held at the node NAp_i of each first capacitor unit CAp_i. Further, the charge Q_an_i corresponding to the input signal Vinn applied immediately before is held at the node NAn_i of each second capacitor unit CAn_i. Therefore, at this timing, the value of the differential analog input signal Vin (Vinp, Vinn) is sampled.

  At the next time t4, the internal clock signal φ1 changes to the L level, so that the switches SWinp_i, SWap_i, SWbp_i of the first capacitor unit CAp_i and the switches SWin_i, SWan_i, SWbn_i of the second capacitor unit CAn_i are turned off. Become.

  Subsequently, at time t5, the internal clock signal φ2 changes to the H level, whereby the switches SWrefp_i and SWcp_i of the first capacitor unit CAp_i and the switches SWrefn_i and SWcn_i of the second capacitor unit CAn_i are turned on. As a result, the corresponding positive reference voltage Vrefp_i is applied to the input side terminal (node NCp_i) of the sampling capacitor Ccp_i, and the corresponding negative reference voltage Vrefn_i is applied to the input side terminal (node NCn_i) of the sampling capacitor Ccn_i. The

  Further, the voltage V_ap_i of the output side terminal (node NAp_i) of the sampling capacitor Ccp_i is input to the non-inverting input terminal (node NBp_i) of the differential amplifier Amq_i through the switch SWcp_i. Similarly, the voltage V_an_i of the output side terminal (node NAn_i) of the sampling capacitor Ccn_i is input to the non-inverting input terminal (node NBn_i) of the differential amplifier Amq_i through the switch SWcn_i. The period in which the internal clock signals φ1d and φ1 are at the L level and the internal clock signal φ2 is at the H level continues until time t6, and the period from time t5 to t6 is the comparison period. A period from time t3 to time t5 is a transition period between the sample period and the comparison period.

  In the comparison period, the charge Q_ap_i corresponding to the input signal Vinp applied immediately before time t3 is held at the node NAp_i of the first capacitor unit CAp_i. Therefore, the voltage V_ap_i of the node NAp_i has a relationship of the following equation (8) with the charge Q_ap_i.

Q_ap_i = Cc × (V_ap_i − Vrefp_i) + Cs × V_ap_i… (8)
From the above equations (6) and (8), the voltage V_ap_i of the node NAp_i has a value as in the following equation (9).

V_ap_i = VCM + Cc / (Cc + Cs) x (Vrefp_i-Vinp) (9)
Similarly, the charge Q_an_i corresponding to the input signal Vinn applied immediately before time t3 is held at the node NAn_i of the second capacitor unit CAn_i. Therefore, the voltage V_an_i of the node NAn_i has a relationship of the following equation (10) with the charge Q_an_i.

Q_an_i = Cc × (V_an_i − Vrefn_i) + Cs × V_an_i (10)
From the above equations (7) and (10), the voltage V_an_i of the node NAn_i has a value as in the following equation (11).

V_an_i = VCM + Cc / (Cc + Cs) x (Vrefn_i-Vinn) (11)
The differential amplifier Amq_i amplifies a difference voltage (V_ap_i−V_an_i) between the voltage V_ap_i expressed by the above equation (9) and the voltage V_an_i expressed by the above equation (11) during the comparison period. Specifically, the difference voltage (V_ap_i−V_an_i) is expressed by the following equation (12).

V_ap_i − V_an_i
= Cc / (Cc + Cs) × ((Vrefp_i−Vrefn_i) − (Vinp−Vinn)) (12)
FIG. 10 is a diagram showing input / output characteristics of the differential amplifier Amq_i in FIG. Referring to FIG. 10, when the differential voltage (INp_i−INn_i) of the input voltage of differential amplifier Amq_i is 0, the differential voltage (OUTp_i−OUTn_i) of the output voltage is also 0. When the input voltage difference voltage is positive, the output voltage difference voltage is L level (negative), and when the input voltage difference voltage is negative, the output voltage difference voltage is H level (positive).

  In the case of the comparator Cmq_i in FIG. 9, since the reference voltage VCM is applied to both the inverting input terminal and the non-inverting input terminal of the differential amplifier Amq_i during the sample period, the output voltage difference voltage (OUTp_i−OUTn_i) is 0. The magnitude of the reference voltage VCM is set to a bias voltage that makes it easy to obtain a gain in designing the differential amplifier. For example, the voltage is set to 1/2 × Vdd to 2/3 × Vdd with respect to the power supply voltage Vdd.

On the other hand, during the comparison period, the differential voltage (V_ap_i−V_an_i) of the above equation (12) is input to the differential amplifier Amq_i. Therefore, the differential amplifier Amq_i and the latch circuit Lch_i in FIG. 9 output the L-level or H-level output signal SC_i depending on whether the input difference voltage (V_ap_i-V_an_i) is positive or negative. That is,
When Vrefp_i−Vrefn_i <Vinp−Vinn, SC_i = “H” (13)
When Vrefp_i-Vrefn_i> Vinp-Vinn, SC_i = “L” (14)
It becomes.

  Also in the case of the A / D converter 2 of the second embodiment, as in the case of the first embodiment, in all the comparators Cmq_i (i is an integer not less than 1 and not more than n), the sample timing is controlled by the internal clock signal φ1d. Determined. The switch SWsd controlled by the internal clock signal φ1d exists only in one place. Therefore, the clock delay due to the parasitic resistance and parasitic capacitance of the clock wiring and the variation of the threshold value Vth of the transistor elements constituting each switch do not affect the sampling timing. As a result, an error due to a shift in the on / off timing of the switch is eliminated from the output signal SC_i of each comparator Cmq_i, so that the performance of the A / D converter is improved.

[Embodiment 3]
FIG. 11 is a circuit diagram showing a configuration of an A / D converter 3 according to the third embodiment of the present invention. The comparator array 10B of FIG. 11 is divided into j comparator groups G_1 to G_j in which n comparators Cmp_1 to Cmp_n are j (j is a divisor of n, usually j = 2, 3, etc.). 2 is different from the comparator array 10 of FIG.

  Further, the A / D converter 3 of FIG. 11 includes j switches SWsd_1 to SWsd_j (a plurality of first switches) corresponding to the j comparator groups G_1 to G_j, respectively. Different from the A / D converter 1. The switch SWsd_w (w is an integer of 1 to j) is provided on a common line Lc_w that supplies the reference voltage VCM to each comparator Cmp that forms the corresponding comparator group G_w. Accordingly, the reference voltage VCM is supplied to the node NA of the comparator Cmp constituting each comparator group G_w when both the individual switch SWs and the corresponding common switch SWsd_w are in the on state.

  Switching of the switches SWsd_1 to SWsd_j is controlled by an internal clock signal φ1d. During the transition period of transition from the sample period to the comparison period, the internal clock signal φ1d is changed before the internal clock signal φ1 that controls the switch SWs of each comparator Cmp_i (i is an integer of 1 to n) changes to the L level. Changes to L level. Accordingly, the switches SWsd_1 to SWsd_j are turned off before the switch SWs.

  According to the above configuration, as in the case of the first embodiment, it is possible to eliminate an error caused by a sample timing shift between the comparators Cmp configuring each comparator group. On the other hand, compared to the case of the first embodiment in which the switch SWsd is arranged at one place, the ON / OFF timing of the switches SWsd_1 to SWsd_j between the comparator groups G_1 to G_j is shifted, so that the error reduction effect is slightly reduced. Inevitable. However, the size of each of the switches SWsd_1 to SWsd_j can be made smaller than in the case of the first embodiment in which one switch SWsd is provided. Therefore, if there is a gap in the comparator array in the layout, the size of the entire A / D converter 3 can be made smaller than that in the first embodiment by arranging in the gap.

  Since other points in FIG. 11 are the same as those in the first embodiment, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated. In the case of the A / D converter 2 having the differential configuration shown in the second embodiment, the comparators Cmq_1 to Cmq_m constituting the comparator array 10A are divided into a plurality of comparator groups. A switch SWsd can be provided on a common path for supplying the reference voltage VCM.

[Embodiment 4]
FIG. 12 is a block diagram showing the configuration of the A / D converter 4 according to the fourth embodiment of the present invention. The A / D converter 4 in FIG. 12 further includes one switch SWt (eighth switch) provided on the common wiring Lt that supplies the reference voltage VCM to the comparator groups G_1 to G_j. 11 different from the A / D converter 3. Accordingly, the reference voltage VCM is supplied to the comparators Cmp constituting each comparator group G_w (w is an integer of 1 to j) when both the corresponding switch SWsd_w and the common switch SWt are in the on state.

  Switching of the switch SWt is controlled by an internal clock signal φ1t. During the transition period in which the sample period shifts to the comparison period, the internal clock signal φ1t becomes the L level before the internal clock signal φ1d that controls the switches SWsd_1 to SWsd_j becomes the L level. As a result, the switch SWt is turned off before the switches SWsd_1 to SWsd_j.

  As described above, by providing another common switch SWt in the layer above the switches SWsd_1 to SWsd_j, it is possible to reduce the influence of the switch ON / OFF timing between the comparator groups G_1 to G_j being shifted. It is.

  Since the other points in FIG. 12 are the same as those in the third embodiment, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated. In the case of the A / D converter 2 having the differential configuration shown in the second embodiment, the comparators Cmq_1 to Cmq_m constituting the comparator array 10A are divided into a plurality of comparator groups. The reference voltage VCM can be supplied when both of the hierarchized switches SWt and SWsd are in the on state.

[Embodiment 5]
FIG. 13 is a block diagram showing the configuration of the A / D converter 5 according to the fifth embodiment of the present invention. The A / D converter 5 in FIG. 13 is a sub-ranging converter.

  There are various types of A / D converters, and there are differences in the number of stages. The stage is an element circuit having a function of taking in an analog signal and outputting a digital signal corresponding to a comparison result with a reference voltage, and performing an analog operation to generate a new analog signal. One cycle of the clock CLK is required from reading an analog signal to outputting a digital signal and an analog signal at each stage, and a half cycle delay is required between adjacent stages.

  In general, when the number of stages is increased, there is an advantage that the number of comparators that perform comparison with the reference voltage can be reduced, and there are a pipeline method, a successive approximation method, and the like that utilize this. These have the effect of reducing power consumption and size by reducing the number of comparators, but on the other hand, since the number of stages is large, one cycle is required for the operation at each stage. There is a disadvantage that the conversion time of the whole converter is long.

  On the other hand, the flash system has one stage and the sub-ranging system has two stages. These A / D converters have the advantage of a short A / D conversion time. Therefore, a flash method or a sub-ranging method is essential for a data storage system or a digital control power supply system that needs to shorten the conversion time as much as possible.

  The sub-ranging A / D converter 5 shown in FIG. 13 is characterized in that the A / D conversion operation is performed in two stages, upper and lower. First, the outline of the operation of the A / D converter 5 will be described with reference to FIG.

  FIG. 14 is a circuit diagram showing an example of the configuration of the ladder resistor 21 of FIG. FIG. 14 shows a configuration of a ladder resistor 21 for a 4-bit A / D converter of upper 2 bits and lower 2 bits. The ladder resistor 21 is a circuit that generates a plurality of reference voltages by dividing a power supply voltage (upper limit voltage: VRT, lower limit voltage: VRB) by a plurality of resistance elements connected in series.

  In the upper A / D conversion, the coarse reference voltages Vrc_1, Vrc_2, and Vrc_3 generated by the ladder resistor 21 are used for comparison with the analog input signal, and a 2-bit digital code (upper code) is obtained as a conversion result. It is done. At the same time, it is determined by the conversion operation whether the analog input signal falls within the reference voltage ranges Rc_1, Rc_2, Rc_3, and Rc_4, and the detailed in the corresponding range (Rc_2 in the example in the figure). The reference voltages Vrf_1, Vrf_2, and Vrf_3 are used for the next lower A / D conversion. In the low-order A / D conversion, the reference voltage and the analog input signal are compared, and it is determined whether the analog input signal falls within the reference voltage range Rf_1, Rf_2, Rf_3, or Rf_4. As a result, a 2-bit digital code (lower code) is obtained. A digital code of a total of 4 bits together with the previous high-order code is the A / D conversion result.

  Referring to FIG. 13 again, the sub-ranging A / D converter 5 includes a sub A / D converter (CADC) for upper A / D conversion and two sub A for lower A / D conversion. / D converter (FDAC # A, FDAC # B), arithmetic circuit 22, ladder resistor 21, switch group (MUX), internal clock generation circuit 26, switches 23, 24, 25, switch SWsd ( First switch).

  In the case of the A / D converter 5 of FIG. 13, in order to perform an interleave operation (alternate operation), two sub-A / D converters for lower-order A / D conversion, FDAC # A and FDAC # B, are provided. Yes. These sub A / D converters FDAC # A and FDAC # B are the same circuit and have a function of lower A / D conversion independently.

  The upper and lower sub A / D converters CADC, FDAC # A, and FDAC # B each include a plurality of comparators. Since the detailed configuration of the sub A / D converter is similar to that of comparator array 10 of the first embodiment, description thereof will not be repeated. Internal clock signals φ11 and φ12 for controlling the operation of the sub A / D converter CADC correspond to the internal clock signals φ1 and φ2 of the first embodiment, respectively. Similarly, internal clock signals φ21 and φ22 for controlling sub A / D converter FDAC # A correspond to internal clock signals φ1 and φ2 of the first embodiment, respectively. The internal clock signals φ31 and φ32 that control the sub A / D converter FDAC # B correspond to the internal clock signals φ1 and φ2 of the first embodiment, respectively.

  The arithmetic circuit 22 is a logic circuit that outputs an m-bit digital code by combining the conversion result of the sub A / D converter CADC and the conversion results of the sub A / D converters FDAC # A and FDAC # B.

  As already described, the ladder resistor 21 is a reference voltage generation circuit that generates a plurality of reference voltages for comparison with the analog input signal Vin to be A / D converted.

  The switch group (MUX) uses the sub-A / D converters FDAC # A and FDAC # to convert the reference voltage of the sub-range determined according to the result of the higher-order A / D conversion from the reference voltages generated by the ladder resistor 21. A switch group for applying to B.

  The internal clock generation circuit 26 is a circuit that generates internal clock signals φ1d, φ11, φ12, φ21, φ22, φ31, and φ32 based on a clock CLK applied from the outside.

  The switches 23, 24, and 25 are switches used when the two sub A / D converters FDAC # A and FDAC # B for low-order A / D conversion are interleaved.

  The switch SWsd is provided on a common path for supplying the reference voltage VCM, as in the case of the first embodiment. Switching of the switch SWsd is controlled by an internal clock signal φ1d. The switch SWsd is turned on when the internal clock signal φ1d is at the H level, and the switch SWsd is turned off when the internal clock signal φ1d is at the L level.

  FIG. 15 is a timing chart showing the operation of each clock signal and sub A / D converter of FIG. Hereinafter, the operation of the A / D converter 5 will be described with reference to FIGS. 13 and 15.

  At time t31 in FIG. 15, internal clock signals φ1d, φ11, and φ21 change to the H level. As a result, the sub A / D converter CADC and the sub A / D converter FDAC # A both sample the analog input signal Vin at the same timing (sample period Sa # 1). At this time, the switch 23 is connected to the sub A / D converter FDAC # A side, and the switches 24 and 25 are connected to the sub A / D converter FDAC # B side.

  At the next time t32, the internal clock signal φ1d changes to the L level before the internal clock signals φ11, φ21. As a result, the switch SWsd is turned off, and the value (# 1) of the analog input signal Vin at this time is sampled.

  After the internal clock signals φ11 and φ21 change to L level at the next time t33, the internal clock signal φ12 changes to H level at time t34. As a result, the sub A / D converter CADC compares the sample value (# 1) of the analog input signal Vin with the coarse reference voltage for higher-order A / D conversion (CADC comparison period Co # 1). As a result, a higher-order digital code is obtained, and it is determined in which range the sample value (# 1) of the analog input signal Vin is included.

  At the next time t35, the internal clock signal φ12 changes to the L level, so that the comparison period Co # 1 of the sub A / D converter CADC ends.

  At the next time t36, the internal clock signals φ1d, φ11, φ22, and φ31 change to the H level. At this time, the switch 23 is connected to the sub A / D converter FDAC # B side, and the switches 24 and 25 are connected to the sub A / D converter FDAC # A side. The switch group (MUX) is a fine reference voltage for low-order A / D conversion included in the voltage range corresponding to the sample value (# 1) of the analog input signal Vin based on the determination result of the comparison period Co # 1 of CADC Is applied to the sub A / D converter FDAC # A. While the internal clock signal φ22 from time t36 to time t40 is at the H level (FADC # A comparison period Co # 1), the sub A / D converter FDAC # A outputs the sample value (# 1) is compared with the lower A / D conversion reference voltage. As a result, a lower digital code is obtained, and the arithmetic circuit 22 outputs the A / D conversion result by combining the upper digital code and the lower digital code.

  Further, from time t36 to the next time t37, the sub A / D converter CADC and the sub A / D converter FDAC # B are both the same in parallel with the comparison operation of the sub A / D converter FDAC # A. The analog input signal Vin is sampled at the timing (sample period Sa # 2).

  At the next time t37, the internal clock signal φ1d changes to the L level before the internal clock signals φ11 and φ31. As a result, the switch SWsd is turned off, and the value (# 2) of the analog input signal Vin at this time is sampled.

  After the internal clock signals φ11 and φ31 change to L level at the next time t38, the internal clock signal φ12 changes to H level at time t39. In response to this change, the sub A / D converter CADC compares the sample value (# 2) of the analog input signal Vin with the coarse reference voltage for the higher A / D conversion (CADC comparison period Co # 2). ). As a result, a higher-order digital code is obtained, and it is determined in which range the analog input signal Vin is included.

  The internal clock signal φ12 changes to the L level at the next time t40, whereby the comparison period Co # 2 of the sub A / D converter CADC ends. At this time, since the internal clock signal φ22 also changes to the L level, the comparison period Co # 1 of the sub A / D converter FDAC # A described above ends.

  At the next time t41, the internal clock signals φ1d, φ11, φ21, and φ32 change to the H level again. At this time, the switch 23 is connected to the sub A / D converter FDAC # A side, and the switches 24 and 25 are connected to the sub A / D converter FDAC # B side. The switch group (MUX) is a fine reference voltage for low-order A / D conversion included in the voltage range corresponding to the sample value (# 2) of the analog input signal Vin based on the determination result of the comparison period Co # 2 of CADC Is applied to the sub A / D converter FDAC # B. Then, while the internal clock signal φ32 after time t41 is at the H level (the FADC # B comparison period Co # 2), the sub A / D converter FDAC # B has a lower value than the sample value (# 2) of the analog input signal Vin. Comparison with the reference voltage for A / D conversion is performed. As a result, a lower digital code is obtained, and the arithmetic circuit 22 outputs the A / D conversion result by combining the upper digital code and the lower digital code.

  In addition, while the internal clock signal φ1d after time t41 is at the H level, the sub A / D converter CADC and the sub A / D converter FDAC are parallel to the comparison operation of the sub A / D converter FDAC # B. Both #A sample the analog input signal Vin at the same timing.

  As described above, the sub A / D converter FDAC # A and the sub A / D converter FDAC # B operate alternately. The purpose is to halve the operating speed of the sub A / D converter CADC by alternately operating two sub A / D converters FDAC # A and FDAC # B. Since the accuracy required for the sub A / D converters FDAC # A and FDAC # B is much stricter than that of the sub A / D converter CADC, it is generally difficult to operate at the same speed as the sub A / D converter CADC. In many cases, there is a demerit that the power consumption becomes very large even if possible. As a countermeasure, such an alternating operation (interleave operation) is performed.

  Also in the case of the A / D converter 5 of the fifth embodiment, as in the case of the first embodiment, the comparator array constituting the sub A / D converters CADC, FDAC # A, and FDAC # B has an internal clock. The timing of the sample is determined by the signal φ1d. The switch SWsd controlled by the internal clock signal φ1d exists only in one place. For this reason, the deviation of the on / off timing of the switch caused by the delay of the clock due to the parasitic resistance or parasitic capacitance of the clock wiring or the variation of the threshold value Vth of the transistor elements constituting the switch does not affect the timing of the sample. As a result, the influence of the switch on / off timing shift is eliminated from the output signals of the sub A / D converters CADC, FDAC # A, and FDAC # B, thereby improving the performance of the A / D converter. .

  In the fifth embodiment, the case of a single analog input signal has been described. However, even in the case of a sub-ranging converter that performs A / D conversion on a differential analog input signal, a common reference voltage VCM is supplied. A common switch SWsd can be provided on the path.

  In the fifth embodiment, only one switch SWsd is provided. However, as in the third embodiment, switches SWsd_1 to SWsd_3 are provided for each of the sub A / D converters CADC, FDAC # A, and FDAC # B. You can also. In this case, a switch SWt at a higher level may be provided as in the fourth embodiment. In this case, the reference voltage VCM is supplied to the sub A / D converters CADC, FDAC # A, and FDAC # B when both of the hierarchized switches SWt, SWsd_1 to SWsd_3 are in the on state.

[Application Example of A / D Converter of Embodiments 1 to 5 to Semiconductor Device]
The flash A / D converters 1 to 4 and the sub-ranging A / D converter 5 described above are system LSIs (Large-Scale Integration) for data storage such as HDDs (Hard Disk Drives) and digital control. It can be suitably used in a semiconductor device such as a power supply microcontroller.

  In the fields of data storage and digital control, A / D converters of flash type or sub-ranging type are frequently used. The reason is that there is a feedback control signal loop including an A / D converter in the system, and there is little time allowance for the feedback. For this reason, it is necessary to minimize the time required for the A / D converter to sample the analog signal and output the corresponding digital code (that is, the conversion time) as much as possible.

  As already described, the flash-type and sub-ranging A / D converters are configured by arranging a number of comparators in an array. For this reason, the timing at which the analog input signal is sampled for each comparator tends to vary due to the delay of the clock and the variation in characteristics of the switch elements. In the A / D converters 1 to 5 of the first to fifth embodiments, the sample timing for each comparator is provided by providing a common switch on the supply line of the reference voltage supplied to the sampling capacitor constituting each comparator. Can be aligned.

Hereinafter, application examples of the A / D converters of the first to fifth embodiments to a semiconductor device will be described.
FIG. 16 is a block diagram of a microcontroller 30 for a digital control power supply having a certain specification. Referring to FIG. 16, the digital control power supply includes a microcontroller 30, a switching circuit 31 such as a DC-DC converter, a smoothing circuit 32 that smoothes the output of the switching circuit 31, and an output voltage for feedback control. And a voltage detection unit 33 for detection.

  The microcontroller 30 is a circuit that generates a PWM (Pulse-Width Modulation) signal for controlling the switching element of the switching circuit 31 based on the detected voltage detected by the voltage detector 33. As shown in FIG. 16, the microcontroller 30 includes an A / D converter 41, a reference voltage circuit 42 that generates a reference voltage for the A / D converter 41, and a signal processing circuit 43.

  The A / D converter 41 is a high-speed A / D converter of a flash method or a sub-ranging method, and digitally converts the detection voltage detected by the voltage detection unit 33. The reference voltage circuit 42 is a circuit that generates the reference voltage VCM of FIG. 1, the power supply voltages (VRT, VRB) input to the reference voltage generation circuit 11, and the like.

  The signal processing circuit 43 is a digital signal processor (DSP) that executes a control algorithm for the switching circuit 31 based on a control signal and a detection voltage input from the outside, and a digital that generates a PWM signal based on a calculation result of the DSP. And a PWM signal generator.

  By applying the A / D converter described in Embodiments 1 to 5 to the A / D converter 41 described above, a high-performance digital control power supply can be realized.

  FIG. 17 is a block diagram of a signal processing device 50 for an HDD having a certain specification. The signal processing device 50 is a circuit that generates a write signal corresponding to the write data received from the hard disk controller (HDC) and generates read data based on the read signal from the magnetic head. Further, the signal processing circuit 50 outputs data for positioning the magnetic head to the servo control circuit based on a read signal from the magnetic head.

  As shown in FIG. 17, the signal processing circuit 50 includes an interface circuit 56 for exchanging data with an external hard disk controller (HDC) and the like, and a write driver 59 for generating a write signal based on the write data. Including.

  Further, the signal processing circuit 50 is a circuit for reading a signal from the hard disk, and includes a variable gain amplifier 51, an analog filter 52, an A / D converter 53, a digital filter 54, a detection circuit 55, a read / write. A voltage-controlled oscillator (VCO) 57 and a voltage-controlled oscillator (VCO) 58 for servo control.

  The variable gain amplifier 51 variably amplifies the amplitude of the read signal that has deteriorated and attenuated due to the nonlinear electromagnetic characteristics of the magnetic head to a predetermined amplitude level. The analog filter 52 removes noise from the analog signal output from the variable gain amplifier 51. The A / D converter 53 converts the output of the analog filter 52 into a digital signal. The digital filter 54 removes noise from the digital signal output from the A / D converter 53. The detection circuit 55 generates read data based on the output of the digital filter 54. Voltage control oscillators (VCO) 57 and 58 for reading / writing and servo control generate a clock signal that is a reference for sampling of the A / D converter 53 based on the output of the detection circuit 55.

  By applying the A / D converter described in the first to fifth embodiments to the A / D converter 53 described above, a high-speed signal processing device 50 for HDD can be realized.

  The embodiment disclosed this time must be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  1 to 5 A / D converter, 10, 10A, 10B comparator array, 11, 11A reference voltage generation circuit, 12, 26 internal clock generation circuit, 21 ladder resistor (reference voltage generation circuit), Amp_i amplifier, Amq_i differential amplifier , CA_i, CAp_i, CAn_i Capacitors, Cc_i, Ccp_i, Ccn_i Sampling capacitors (capacitance elements), Cmp_i, Cmq_i comparators, G_1 to G_j comparator groups, SWsd, SWsd_1 to SWsd_j First switch, SWin_i, SWinp_i SWref_i, SWrefp_i 4th switch, SWs_i, SWap_i 3rd switch, SWin_i 5th switch, SWrefn_i 7th switch, SWan_i 6th switch , SWbp_i, SWcp_i, SWbn_i, SWcn_i switch, SWt eighth switch, VCM reference voltage, Vin analog input signal, Vinp positive analog input signal, Vinn negative analog input signal, Vref_i, Vrc reference voltage, Vrefp_i positive reference voltage , Vrefn_i Negative reference voltage.

Claims (5)

A reference voltage generation circuit for generating a plurality of first reference voltages;
A plurality of comparators respectively corresponding to the plurality of first reference voltages, each receiving a corresponding first reference voltage, a first analog voltage signal to be digitally converted, and a common reference voltage;
Provided on a common path for supplying the reference voltage to each of the plurality of comparators, is conductive in the sample period, is non-conductive in the comparison period, and is between the sample period and the comparison period A first switch that switches from a conductive state to a non-conductive state during the transition period;
Each of the plurality of comparators is
Second and third switches that are conductive in the sample period, non-conductive in the comparison period, and non-conductive after the first switch is non-conductive in the transition period;
A fourth switch that is non-conductive during the sample period, is conductive during the comparison period, and is conductive after the first switch is non-conductive during the transition period;
One end receives the first analog voltage signal when the second switch is in a conductive state and the corresponding first reference voltage when the fourth switch is in a conductive state. A first capacitive element that receives the reference voltage when the third switch is conductive;
An analog / digital converter including an amplifier to which the voltage of the other end of the first capacitor element is input during the comparison period. The reference voltage generation circuit further generates a plurality of second reference voltages that form a plurality of differential reference voltages in pairs with the plurality of first reference voltages, respectively.
Each of the plurality of comparators further receives a second analog voltage signal paired with the first analog voltage signal to form a differential analog voltage signal;
Each of the plurality of comparators is
Fifth and sixth switches that are conductive during the sample period, non-conductive during the comparison period, and non-conductive after the first switch is non-conductive during the transition period;
A seventh switch that is non-conductive during the sample period, is conductive during the comparison period, and is conductive after the first switch is non-conductive during the transition period;
One end receives the second analog voltage signal when the fifth switch is conductive and the corresponding second reference voltage when the seventh switch is conductive, and the other end receives the second reference voltage. And a second capacitive element that receives the reference voltage when the sixth switch is in a conductive state,
2. The analog / digital converter according to claim 1, wherein in each of the plurality of comparators, a voltage of the other end of the second capacitor element is further input to the amplifier during the comparison period. An analog / digital converter,
A reference voltage generation circuit for generating a plurality of first reference voltages;
A plurality of comparators each corresponding to the plurality of first reference voltages, each receiving a corresponding first reference voltage, a first analog voltage signal to be digitally converted, and a common reference voltage;
The plurality of comparators are divided into a plurality of groups,
The analog / digital converter further corresponds to each of the plurality of groups, and each of the analog / digital converters is provided on a common path for supplying the reference voltage to each comparator constituting the corresponding group, and is conducted during the sample period. A plurality of first switches that are in a state, in a non-conduction state in a comparison period, and switched from a conduction state to a non-conduction state in a transition period between the sample period and the comparison period;
Each of the plurality of comparators is
Second and third switches that are conductive during the sample period, non-conductive during the comparison period, and are non-conductive after the plurality of first switches are non-conductive during the transition period When,
A fourth switch that is non-conductive during the sample period, is conductive during the comparison period, and is conductive after the plurality of first switches are non-conductive during the transition period;
One end receives the first analog voltage signal when the second switch is in a conductive state and the corresponding first reference voltage when the fourth switch is in a conductive state. A first capacitive element that receives the reference voltage when the third switch is conductive;
An analog / digital converter including an amplifier to which the voltage of the other end of the first capacitor element is input during the comparison period. The reference voltage generation circuit further generates a plurality of second reference voltages that form a plurality of differential reference voltages in pairs with the plurality of first reference voltages, respectively.
Each of the plurality of comparators further receives a second analog voltage signal paired with the first analog voltage signal to form a differential analog voltage signal;
Each of the plurality of comparators is
Fifth and sixth switches that are conductive during the sample period, are non-conductive during the comparison period, and are non-conductive after the plurality of first switches are non-conductive during the transition period When,
A seventh switch that is non-conductive during the sample period, is conductive during the comparison period, and is conductive after the plurality of first switches are non-conductive during the transition period;
One end receives the second analog voltage signal when the fifth switch is conductive and the corresponding second reference voltage when the seventh switch is conductive, and the other end receives the second reference voltage. And a second capacitive element that receives the reference voltage when the sixth switch is in a conductive state,
5. The analog / digital converter according to claim 4, wherein in each of the plurality of comparators, a voltage of the other end of the second capacitive element is further input to the amplifier during the comparison period. The analog / digital converter further includes an eighth switch provided on a common path for supplying the reference voltage to each of the plurality of first switches,
The eighth switch is conductive during the sample period, is non-conductive during the comparison period, and is non-conductive before the plurality of first switches are non-conductive during the transition period. 5. An analog / digital converter according to claim 3 or 4.

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