CN114035635A

CN114035635A - Reference voltage generating circuit and method for modulator

Info

Publication number: CN114035635A
Application number: CN202111343044.0A
Authority: CN
Inventors: 廖望; 侯江; 郭亮; 黄晓宗; 苏豪; 雷昕; 甘明富; 谢向阳; 侯东平; 陈雪
Original assignee: CETC 24 Research Institute
Current assignee: CETC 24 Research Institute
Priority date: 2021-11-12
Filing date: 2021-11-12
Publication date: 2022-02-11
Anticipated expiration: 2041-11-12
Also published as: CN114035635B

Abstract

The invention belongs to the technical field of analog integrated circuits, and particularly relates to a reference voltage generating circuit and a reference voltage generating method for a modulator; the circuit is controlled by the output of the 1-bit comparator of the modulator, and specifically comprises a differential reference voltage generation circuit and a reference V_EBA voltage generating circuit; the differential reference voltage generation positive terminal is connected with the common terminal positive terminal, the differential reference voltage generation negative terminal is connected with the common terminal negative terminal, and the reference V is connected with the reference V_EBThe voltage generation positive terminal circuit is connected with a common terminal positive terminal and a reference V_EBThe voltage generation negative terminal circuit is connected with a public terminal negative terminal; the invention can directly adjust the positive temperature coefficient delta V in the reference voltage by modifying the size of the C1_ x/C2_ y capacitor, connecting/disconnecting the C3_ z and the like_EBAnd negative temperature coefficient voltage V_EBThereby adjusting the absolute value of the reference voltage.

Description

Reference voltage generating circuit and method for modulator

Technical Field

The invention belongs to the technical field of analog integrated circuits, and particularly relates to a reference voltage generating circuit and method of a modulator in a Delta-Sigma ADC.

Background

Delta-Sigma ADC combines the sampling technique and the noise shaping technique, so that the quantization noise is moved to a high-frequency range, the signal-to-noise ratio in the signal bandwidth is improved, and finally, the high-frequency noise is filtered by a down-sampling filter and then a digital result is output. Delta-Sigma ADC has the advantages of high signal-to-noise ratio, high precision and the like, and is widely applied to various fields of precision instruments, high-precision signal acquisition and processing, digital temperature sensors, medical equipment and the like.

The Delta-Sigma modulator is one of important modules, as shown in figure 1, the circuit is a 1 st order 1 modulator, as shown in figure 2, the 1 st order 1 modulator is composed of an integrator, a quantizer and a feedback DAC, a 1 bit quantizer (comparator) converts an analog signal into a digital signal, the quantized output result is fed back to a former stage integrator every time to reduce the quantization error and improve the conversion precision, the digital result is fed back to the former stage of the modulator according to the output of the comparator, and the 1 bit DAC function is realized by controlling a reference voltage.

The reference voltage is used as a reference source of the modulator and the Delta-Sigma ADC, and the precision of the reference voltage directly determines the performance of the modulator and the whole ADC, so the reference source design is used as an important consideration of the performance of the Delta-Sigma ADC. The traditional reference voltage generating circuit needs to combine a negative temperature coefficient voltage and a positive temperature coefficient voltage to form a reference voltage which is almost irrelevant to temperature and then output the reference voltage to the inside of a modulator, and a stable reference source is provided for the modulator in each comparison period.

Disclosure of Invention

The invention provides a circuit and a method for generating a reference voltage of a modulator, aiming at the requirement of the modulator on the high-precision reference voltage. The purpose of the invention is realized by the following technical scheme:

in a first aspect thereof, the present invention provides a reference voltage generation circuit for a modulator, the circuit being controlled by the result output from a 1-bit comparator of the modulator, comprising in particular a differential reference voltage generation circuit and a reference V_EBA voltage generating circuit; the differential reference voltage generation positive terminal is connected with the common terminal positive terminal, the differential reference voltage generation negative terminal is connected with the common terminal negative terminal, and the reference V is connected with the reference V_EBThe voltage generation positive terminal circuit is connected with a common terminal positive terminal and a reference V_EBThe voltage generation negative terminal circuit is connected with a public terminal negative terminal;

each differential reference voltage generating circuit comprises a first input voltage source and a second input voltage source, each input voltage source is connected with one end of a first switch and one end of a second switch, the other end of the first switch is connected with an upper plate of a first capacitor and an upper plate of a second capacitor, the other end of the second switch is connected with an upper plate of a third capacitor, and a lower plate of the third capacitor is connected with an upper plate of a fourth capacitor, one end of the third switch and one end of the fourth switch; the common-mode voltage VCM is connected with the lower plates of the first capacitor, the second capacitor and the fourth capacitor and the other end of the third switch, the other end of the fourth switch is connected with a positive end or a negative end of a common end, and the other end of the first switch of any one of a first input voltage source and a second input voltage source is connected with the other end of the second switch of the other input voltage source; and the other ends of the fourth switches of the two input voltage sources are connected with each other;

each reference V_EBVoltage generating circuitEach input voltage source is connected with one end of a fifth switch and one end of a sixth switch, the other ends of the fifth switch and the sixth switch are respectively connected with corresponding branches, the other end of each branch is connected with a fifth capacitor and a higher-level plate of a sixth capacitor, and the lower-level plate of the sixth capacitor is connected with the higher-level plate of a seventh capacitor, one end of the seventh switch and one end of an eighth switch; the other ends of the fifth switch, the seventh switch and the lower plate of the fifth capacitor and the seventh capacitor are connected with a common-mode voltage VCM, the other end of the eighth switch is connected with a positive end or a negative end of a common end, and the other end of the fifth switch of any one of a third input voltage source and a fourth input voltage source is connected with the other end of the sixth switch of the other input voltage source; and the other ends of the eighth switches of the two input voltage sources are connected to each other.

In a second aspect of the present invention, the present invention also provides a reference voltage generating method for a modulator, the method comprising:

determining a differential reference voltage generating circuit and a reference V at the current cycle based on the output of the 1-bit comparator of the modulator_EBA switch state in the voltage generation circuit;

controlling and connecting a corresponding capacitor according to the switching state of the current period, and generating corresponding positive/negative reference voltage;

respectively calculating to obtain the charge distribution of the positive end and the negative end of the public end based on the positive/negative reference voltage generated in the current period, and obtaining the corresponding differential charge distribution difference;

according to the charge conservation principle, obtaining a differential voltage value based on the differential charge distribution difference of the previous period and the differential charge distribution difference of the current period;

and determining the generated positive/negative reference voltage value according to the difference of the front and rear differential voltage values.

The invention has the beneficial effects that:

1. compared with the traditional reference voltage generation mode, the resistor is mismatched and sensitive to temperature after actual process processing, so that the generated reference voltage drifts from the absolute value and the temperature drift; the reference voltage is generated by using the capacitor in a charge redistribution mode, the capacitor is insensitive to temperature, and meanwhile the capacitor can be better matched;

2. the invention modifies the size of the C1_ x/C2_ y capacitor, and can directly adjust the positive temperature coefficient delta V in the reference voltage by connecting/disconnecting the C3_ z and the like_EBAnd negative temperature coefficient voltage V_EBThereby adjusting the absolute value of the reference voltage;

3. by adopting the switch time sequence, the switching of the capacitance switch can be directly realized according to the output result of the 1-bit comparator in the modulator in the period, whether a reference voltage value is added or subtracted is determined, and no additional clock period is needed. Meanwhile, after the opposite-phase switches are switched in the period, the differential voltage value is not changed;

4. the reference voltage of the period is directly established at the clock falling edge, and the constant/reference voltage value is added/reference voltage value is subtracted at the next clock falling edge according to the output result of the comparator.

Drawings

FIG. 1 is a schematic diagram of a reference voltage generating circuit;

FIG. 2 is a schematic diagram of a 1-order 1-bit modulator;

FIG. 3 is a differential reference voltage generating positive terminal circuit of the present invention;

FIG. 4 is a differential reference voltage generating negative terminal circuit of the present invention;

FIG. 5 shows a reference V according to the present invention_EBA voltage generating positive terminal circuit;

FIG. 6 shows a reference V according to the present invention_EBA voltage generating negative terminal circuit;

FIG. 7 is the switch operating sequence of the present invention;

FIG. 8 is an example of the timing of the operation of the switch of the present invention (when the comparator output is 1,1,0,0, 1);

FIG. 9 shows the circuit connection relationship when the output result of the comparator is equal to 1;

fig. 10 shows the circuit connection relationship when the comparator output result is 1;

FIG. 11 shows the circuit connection relationship when the output result of the comparator is equal to 0;

fig. 12 shows the circuit connection relationship when the comparator output result is 0;

fig. 13 shows the circuit connection relationship when the comparator output result is 1.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The high precision reference is an important unit in a CMOS temperature sensor, as shown in FIG. 1, and the basic principle is to apply a negative temperature coefficient voltage V_EBWith positive temperature coefficient voltage Δ V_EBIn combination, by adjusting the coefficients α and β, a reference voltage V can be obtained that is approximately independent of temperature_REF＝α△V_EB+βV_EB。

Referring to fig. 3 to 6, in an embodiment of the present invention, a reference voltage generating circuit for a modulator, which is controlled by the output of a 1-bit comparator of the modulator, specifically includes a differential reference voltage generating circuit and a reference V_EBA voltage generating circuit; the differential reference voltage generation positive terminal circuit 10 is connected to a common terminal positive terminal, the differential reference voltage generation negative terminal circuit 11 is connected to a common terminal negative terminal, and the reference V is set_EBThe voltage generation positive terminal circuit 20 is connected to a common terminal positive terminal, reference V_EBThe voltage generation negative terminal circuit 21 is connected with a common terminal negative terminal;

each reference V_EBThe voltage generation circuit comprises a third input voltage source and a fourth input voltage source, each input voltage source is connected with one end of a fifth switch and one end of a sixth switch, the other ends of the fifth switch and the sixth switch are respectively connected with corresponding branches, the other end of each branch is connected with a fifth capacitor and a higher-level plate of a sixth capacitor, and the lower-level plate of the sixth capacitor is connected with the higher-level plate of a seventh capacitor, one end of the seventh switch and one end of an eighth switch; the other ends of the fifth switch, the seventh switch and the lower plate of the fifth capacitor and the seventh capacitor are connected with a common-mode voltage VCM, the other end of the eighth switch is connected with a common-terminal positive terminal P, and the other end of the fifth switch of any one of a third input voltage source and a fourth input voltage source is connected with the other end of the sixth switch of the other input voltage source; and the other ends of the eighth switches of the two input voltage sources are connected to each other.

FIG. 3 shows a differential reference voltage generating positive terminal circuit according to an embodiment of the present invention, and as shown in FIG. 3, the differential reference voltage generating positive terminal circuit 10 includes a first input voltage source a V_EB1And a second input voltage source a V_EB2Each input voltage source is connected with one end of a first switch SB0/SB3 and a second switch SB1/SB2, the other end of the first switch SB0/SB3 is connected with the upper-level plate of a first capacitor C2_0/C2_1 and a second capacitor C1_0/C1_3, the other end of the second switch SB1/SB2 is connected with the upper-level plate of a third capacitor C1_1/C1_2, and the lower-level plate of the third capacitor C1_1/C1_2The upper-stage plate of a fourth capacitor C2_2/C2_3, one end of a third switch SB _0/SB _1 and one end of a fourth switch SBC _0/SBC _1 are connected to the plate; the common-mode voltage VCM is connected to the lower-stage plate of the first capacitor C2_0/C2_1, the second capacitor C1_0/C1_3, the fourth capacitor C2_2/C2_3 and the other end of the third switch SB _0/SB _1, and the common-terminal positive terminal P is connected to the other end of the fourth switch SBC _0/SBC _1, wherein the other end of the first switch SB0/SB3 of any one of the first input voltage source and the second input voltage source is connected to the other end of the second switch SB1/SB2 of the other input voltage source, that is, the other end of the first switch SB0 is connected to the second switch SB1, and the other end of the first switch SB3 is connected to the second switch SB 2; and the other ends of the fourth switches SBC _0/SBC _1 of the two input voltage sources are connected to each other.

The positive terminal 10 of the differential reference voltage generating circuit of the present invention includes a switch SB0, a switch SB1, a switch SB2, a switch SB3, a switch SBC _0, a switch SBC _1, a switch SB _0, a switch SB _1, a capacitor C1_0, a capacitor C1_1, a capacitor C1_2, a capacitor C1_3, a capacitor C2_0, a capacitor C2_1, a capacitor C2_2, and a capacitor C2_ 3. One end of the switch SB0 and the switch SB2 is connected with the input voltage a V_EB1One end of the switch SB1 and one end of the switch SB3 are connected with the input voltage a V_EB2The other ends of the switch SB0 and the switch SB1 are connected to the upper plates of capacitors C1_0, C1_1 and C2_0, the other ends of the switch SB2 and the switch SB3 are connected to the upper plates of capacitors C1_2, C1_3 and C2_1, the lower plate of the capacitor C2_0 is connected to the common mode voltage VCM, the lower plate of the capacitor C1_0 is connected to the common mode voltage VCM, the lower plate of the capacitor C1_1 is connected to the upper plate of the capacitor C2_2, the switch SBC _0 and the switch SB _0, the other end of the switch SBC _0 is connected to the common mode voltage VCM, the other end of the switch SB _0 is connected to the positive terminal (P) of the common terminal, the lower plate of the capacitor C2_2 is connected to the common mode voltage VCM, the lower plate of the capacitor C2_1 is connected to the common mode voltage VCM, the lower plate of the capacitor C1_3 is connected to the common mode voltage VCM, and the lower plate of the capacitor C1_2 is connected to the upper plate of the capacitor C2, Switch SBC _1 and switch SB _1 are connected, the other end of switch SBC _1 is connected with common mode voltage VCM, the other end of switch SB _1 is connected with the positive end (P) of the common terminal, and the lower pole plate of capacitor C2_3 is connected with common mode voltage VCM.

FIG. 4 shows a reference V according to an embodiment of the present invention_EBVoltage generating positive terminal circuit, shown in FIG. 4, with reference V_EBThe voltage generating positive side circuit 11 comprises a third input voltage source V_EB3Each input voltage source is connected with one end of a fifth switch SC3/SC0 and one end of a sixth switch SC2/SC1, the other ends of the fifth switch SC3/SC0 and the sixth switch SC2/SC1 are respectively connected with corresponding branches, in each branch, the other ends of the branches are connected with an upper-stage plate of a fifth capacitor C3_0/C3_1 and a sixth capacitor C2_4/C2_5, and a lower-stage plate of the sixth capacitor C2_4/C2_5 is connected with an upper-stage plate of a seventh capacitor C2_6/C2_7, one end of a seventh switch SC _0/SC _1 and one end of an eighth switch SCC _0/SCC _ 1; the common mode voltage VCM is connected to the lower plate of the fifth capacitor C3_0/C3_1 and the seventh capacitor C2_6/C2_7 and the other end of the seventh switch SC _0/SC _1, and the common terminal negative terminal N is connected to the other end of the eighth switch SCC _0/SCC _1, wherein the other end of the fifth switch SC3/SC0 of any one of the third input voltage source and the fourth input voltage source is connected to the other end of the sixth switch SC2/SC1 of the other input voltage source, that is, the other end of the fifth switch SC 387sc 3 is connected to the sixth switch SC2, and the other end of the fifth switch SC0 is connected to the sixth switch SC 1; and the other ends of the eighth switches of the two input voltage sources are connected to each other.

The reference VEB voltage generating circuit 11 of the present invention includes a switch SC0, a switch SC1, a switch SC2, a switch SC3, a switch SCC _0, a switch SCC _1, a switch SC _0, a switch SC _1, a capacitor C3_0, a capacitor C3_1, a capacitor C2_4, a capacitor C2_5, a capacitor C2_6, and a capacitor C2_ 7. One ends of the switch SC0 and the switch SC2 are connected to the ground GND, and one ends of the switch SC1 and the switch SC3 are connected to the input voltage 1 × V_EB3The other ends of the switch SC0 and the switch SC1 are connected with the upper plates of capacitors C3_0 and C2_4, the other ends of the switch SC2 and the switch SC3 are connected with the upper plates of capacitors C3_1 and C2_5, the lower plate of the capacitor C3_0 is connected with a common-mode voltage VCM, the lower plate of the capacitor C3_1 is connected with the common-mode voltage VCM, the lower plate of the capacitor C2_4 is connected with the upper plate of a capacitor C2_6, one end of the switch SCC _0 and one end of the switch SC _0, and the lower plate of the capacitor C2_5 is connected with the upper plate of the capacitor C2_6The upper polar plate of electric capacity C2_7, switch SCC _1, the one end of switch SC _1 links to each other, the lower polar plate of electric capacity C2_6 links to each other with common mode voltage VCM, the lower polar plate of electric capacity C2_7 links to each other with common mode voltage VCM, the other end of switch SCC _0 links to each other with common mode voltage VCM, the other end of switch SCC _1 links to each other with common mode voltage VCM, the other end and the positive end of common terminal (P) of switch SC _0 and switch SC _1 link to each other.

FIG. 5 shows a reference voltage generating negative terminal circuit according to an embodiment of the present invention, as shown in FIG. 3, and the differential reference voltage generating negative terminal circuit 20 of the present invention includes a first input voltage source a V_EB1And a second input voltage source a V_EB2Each input voltage source is connected with one end of a first switch SB4/SB7 and a second switch SB5/SB6, the other end of the first switch SB4/SB7 is connected with an upper plate of a first capacitor C2_8/C2_9 and a second capacitor C1_4/C1_7, the other end of the second switch SB5/SB6 is connected with an upper plate of a third capacitor C1_5/C1_6, and the lower plate of the third capacitor C1_5/C1_6 is connected with an upper plate of a fourth capacitor C2_10/C2_11, one end of a third switch SB _2/SB _3 and a fourth switch SBC _2/SBC _ 3; the common-mode voltage VCM is connected to the lower-stage plate of the first capacitor C2_8/C2_9, the second capacitor C1_4/C1_7, the fourth capacitor C2_10/C2_11 and the other end of the third switch SB _2/SB _3, and the common-terminal negative terminal N is connected to the other end of the fourth switch SBC _2/SBC _3, wherein the other end of the first switch SB4/SB7 of any one of the first input voltage source and the second input voltage source is connected to the other end of the second switch SB5/SB6 of the other input voltage source, that is, the other end of the first switch SB4 is connected to the second switch SB5, and the other end of the first switch SB7 is connected to the second switch SB 6; and the other ends of the fourth switches SBC _2/SBC _3 of the two input voltage sources are connected to each other.

The negative terminal 20 of the differential reference voltage generating circuit of the present invention comprises a switch SB4, a switch SB5, a switch SB6, a switch SB7, a switch SBC _2, a switch SBC _3, a switch SB _2, a switch SB _3, a capacitor C1_4, a capacitor C1_5, a capacitor C1_6, a capacitor C1_7, a capacitor C2_8, a capacitor C2_9, a capacitor C2_10, and a capacitor C2_ 11. One end of the switch SB5 and the switch SB7 is connected with the input voltage aV_EB1One end of the switch SB4 and one end of the switch SB6 are connected with the input voltage a V_EB2The other ends of the switch SB4 and the switch SB5 are connected to the upper plates of capacitors C1_4, C1_5 and C2_8, the other ends of the switch SB6 and the switch SB7 are connected to the upper plates of capacitors C1_6, C1_7 and C2_9, the lower plate of the capacitor C2_8 is connected to common mode voltage VCM, the lower plate of the capacitor C1_4 is connected to common mode voltage VCM, the lower plate of the capacitor C1_5 is connected to the upper plate of capacitor C2_10, switch SBC _2 and switch SB _2, the other end of the switch SBC _2 is connected to common mode voltage VCM, the other end of the switch SB _2 is connected to the positive terminal (N), the lower plate of the capacitor C2_10 is connected to common mode voltage VCM, the lower plate of the capacitor C2_9 is connected to common mode voltage VCM, the lower plate of the capacitor C1_7 is connected to common mode voltage VCM, and the lower plate of the capacitor C1_6 is connected to the upper plate of the capacitor C68611 _11, Switch SBC _3, switch SB _3 link to each other, and the other end of switch SBC _3 links to each other with common mode voltage VCM, and the other end of switch SB _3 links to each other with common terminal positive terminal (N), and the bottom plate of electric capacity C2_11 links to each other with common mode voltage VCM.

FIG. 6 shows a reference V according to an embodiment of the present invention_EBThe voltage generating negative side circuit, as shown in FIG. 6, is identical to the corresponding positive side circuit, and shows the reference V_EBThe voltage generating negative terminal circuit 21 includes a third input voltage source V_EB3Each input voltage source is connected with one end of a fifth switch SC7/SC4 and one end of a sixth switch SC6/SC5, the other ends of the fifth switch SC7/SC4 and the sixth switch SC6/SC5 are respectively connected with corresponding branches, in each branch, the other ends of the branches are connected with an upper-stage plate of a fifth capacitor C3_2/C3_3 and a sixth capacitor C2_12/C2_13, and a lower-stage plate of the sixth capacitor C2_12/C2_13 is connected with an upper-stage plate of a seventh capacitor C2_14/C2_15, one end of a seventh switch SC _2/SC _3 and an eighth switch SCC _2/SCC _ 3; the common mode voltage VCM is connected to the lower plate of the fifth capacitor C3_2/C3_3 and the seventh capacitor C2_14/C2_15 and the other end of the seventh switch SC _2/SC _3, and the common terminal negative terminal is connected to the other end of the eighth switch SCC _2/SCC _3, wherein the other end of the fifth switch SC7/SC4 of any one of the third input voltage source and the fourth input voltage source is connected to the other end of the sixth switch SC6/SC5 of the other input voltage source, that is, the other end of the fifth switch SC7/SC4 of the other input voltage source is connected to the other end of the sixth switch SC6/SC5 of the other input voltage source, that is, the lower plate of the fifth capacitor C3_2/C3_3 and the seventh capacitor C2_14/C2_15 are connected to the common mode voltage VCM, and the other end of the eighth switch SC _2/SC _3 is connected to the common terminal of the third input voltage sourceThe other end of the fifth switch SC7 is connected with a sixth switch SC6, and the other end of the fifth switch SC4 is connected with a sixth switch SC 5; and the other ends of the eighth switches SCC _2/SCC _3 of the two input voltage sources are connected to each other.

The reference VEB voltage generating circuit 21 of the present invention includes a switch SC4, a switch SC5, a switch SC6, a switch SC7, a switch SCC _2, a switch SCC _3, a switch SC _2, a switch SC _3, a capacitor C3_2, a capacitor C3_3, a capacitor C2_12, a capacitor C2_13, a capacitor C2_14, and a capacitor C2_ 15. One ends of the switch SC5 and the switch SC7 are connected to the ground GND, and one ends of the switch SC4 and the switch SC6 are connected to the input voltage 1 × V_EB3The other ends of the switch SC4 and the switch SC5 are connected with the upper plates of capacitors C3_2 and C2_12, the other ends of the switch SC6 and the switch SC7 are connected with the upper plates of capacitors C _3 and C2_13, the lower plate of the capacitor C3_3 is connected with the common-mode voltage VCM, the lower plate of the capacitor C2_12 is connected with the upper plate of the capacitor C2_14 and the switch SCC _2, one end of a switch SC _2 is connected, a lower pole plate of a capacitor C2_13 is connected with an upper pole plate of a capacitor C2_15, one end of a switch SCC _3 and one end of a switch SC _3 are connected, a lower pole plate of a capacitor C2_14 is connected with a common-mode voltage VCM, a lower pole plate of a capacitor C2_15 is connected with the common-mode voltage VCM, the other end of the switch SCC _2 is connected with the common-mode voltage VCM, the other end of the switch SCC _3 is connected with the common-mode voltage VCM, and the other ends of the switch SC _2 and the switch SC _3 are connected with a common-terminal positive end (N). In the embodiment of the invention, the positive temperature coefficient delta V in the reference voltage can be directly adjusted by modifying the size of the equivalent capacitor C1/C2, connecting/disconnecting the equivalent capacitor C3 and the like_EBAnd negative temperature coefficient voltage V_EBWherein C1 equivalent capacitance (C1_ x), C2 equivalent capacitance (C2_ y) and C3 equivalent capacitance (C3_ z) refer to the same or different capacitance connected respectively, for example, in the first half cycle, C1 equivalent capacitance may be C1_0 and C1_3, and in the last half cycle, C1 equivalent capacitance may be C1_1 and C1_ 2.

Unless otherwise noted, all ADC-bit comparator output results are updated on the falling clock edge of the cycle.

As shown in the figureIn this clock cycle, the current comparison result D0 is output at the clock falling edge time a, and the next result is updated at the falling edge b of the next clock cycle. The SC3 signal outputs the comparator result D0 (0 if the comparator output D0 is equal to 0, otherwise 1) during the first half period of the current clock, and outputs the inverse of the comparator result D0 during the second half period

The next comparator result D1 is updated at the next cycle time b, SC3 outputs the comparator result D1 at the low level of the first half cycle of the clock (if the comparator output D1 is 0,0 is output, otherwise 1 is output), and outputs the inverse of the comparator result D1 at the second half cycle

The SC0 signal is the SC3 signal delayed by one-half clock cycle. The correspondence of the remaining signals is: SC2 ═ SC3, SC1 ═ SC 0; SB 0-SC 3, SB 1-SC 2, SB 2-SC 1, and SB 3-SB 0. SCC _0 is in phase with the clock, and SCC _1 is in phase with the clock; SCC _0 ═ SBC _1 ═ SB _0 ═ SC _ 1; SCC _1 ═ SBC _0 ═ SB _1 ═ SC _ 0. For example, it is assumed that when the comparator output result is 1,1,0,0,1, the respective switching timings are as shown in fig. 8. When the switch input signal in each period is 1, the logic level is high, and the switch is turned on or off; when the switch input signal is equal to 0, the logic level is low, and the switch is turned off.

In the embodiment of the present invention, the first switch of the first input voltage source and the first switch of the second input voltage source are controlled by the result output from the same 1-bit comparator, the sixth switch SC2 of the fourth voltage input source is the fifth switch SC3 of the third voltage input source, and the sixth switch SC1 of the third voltage input source is the fifth switch SC0 of the fourth voltage input source; the first switch SB0 of the first voltage input source is the fifth switch SC3 of the third voltage input source, the second switch SB1 of the second voltage input source is the sixth switch SC2 of the fourth voltage input source, the second switch SB2 of the first voltage input source is the sixth switch SC1 of the third voltage input source, and the first switch SB3 of the second voltage input source is the first switch SB0 of the first voltage input source; the eighth switch SCC _0 of the fourth input voltage source is in phase with the clock, and the eighth switch SCC _1 of the third input voltage source is in phase with the clock; the eighth switch SCC _0 of the fourth input voltage source is the fourth switch SBC _1 of the second input voltage source and the third switch SB _0 of the second input voltage source is the seventh switch SC _1 of the third input voltage source; the eighth switch SCC _1 of the third input voltage source is the fourth switch SBC _0 of the first input voltage source is the third switch SB _1 of the first voltage input source is the seventh switch SC _0 of the fourth voltage input source.

As shown in fig. 9, for example, in the period Φ, assuming that the comparator output result is 1, in the Φ phase where the clock is low, the level signals of the respective switches are:

signal	Logic level
		Clock CLK (phi)	0
The comparison result of the present period	1
		SC3/SB0	1
SC2/SB1	0
		SC0/SB3	0
SC1/SB2	1
		SCC_0/SC_1/SBC_1/SB_0	0
SCC_1/SC_0/SBC_0/SB_1	1

The capacitance connection is as shown in fig. 9(Φ phase), then the charge distribution with respect to the positive common terminal is calculated as:

(aV_EB1-Vxp1)×8C+(V_EB3-Vxp1)×4C (1)

for the common-side negative terminal, the charge is calculated as:

(aV_EB2-Vxn1)×8C+(0-Vxn1)×4C (2)

because of the fully differential design, the positive terminal minus the negative terminal [ (1) - (2) ] yields:

(a△V_EB-△V₁)×8C+V_EB3×4C-△V₁×4C (3)

wherein Vxp1 represents the positive terminal voltage value of the common terminal in the phase phi of the cycle, Vxn1 represents the negative terminal voltage value of the common terminal in the phase phi of the cycle, and DeltaV_EB＝V_EB1-V_EB2；△V₁Representing the differential voltage value in phase phi of the cycle and C representing the capacity of each capacitor.

In the period phi to phi, the level signals of the switches are:

signal	Logic level
		Clock CLK (phi)	1
The comparison result of the present period	1
		SC3/SB0	0
SC2/SB1	1
		SC0/SB3	1
SC1/SB2	0
		SCC_0/SC_1/SBC_1/SB_0	1
SCC_1/SC_0/SBC_0/SB_1	0

The capacitance connection is as shown in fig. 9 (phi phase), then the charge distribution relative to the positive common terminal is calculated as:

(aV_EB2-Vxp2)×8C+(0-Vxp2)×4C (4)

for the common-side negative terminal, the charge is calculated as:

(aV_EB1-Vxn2)×8C+(V_EB3-Vxn2)×4C (5)

because of the fully differential design, the positive terminal minus the negative terminal [ (4) - (5) ] yields:

(-a△V_EB-△V₂)×8C-V_EB3×4C-△V₂×4C (6)

because of the two switching times, the total amount of charge is the same, i.e. equation (3) is equal to (6),

obtaining:

i.e. two phases within the period phi, differential voltage values occur

And (6) jumping.

Wherein Vxp2 represents the voltage value of the positive terminal of the common terminal in the period-phi phase, Vxn2 represents the voltage value of the negative terminal of the common terminal in the period-phi phase, and DeltaV₂Representing the differential voltage value in the cycle-phi phase.

As shown in fig. 10, in the period Φ 1, assuming that the comparator output result is 0, the level signal of each switch is:

The capacitance connection is as shown in fig. 10(Φ 1 phase), and the charge distribution is calculated as:

(aV_EB1-Vxp3)×8C+(V_EB3-Vxp3)×4C (7)

for the common-side negative terminal, the charge is calculated as:

(aV_EB2-Vxn3)×8C+(0-Vxn3)×4C (8)

because of the fully differential design, the positive terminal minus the negative terminal [ (7) - (8) ] yields:

(a△V_EB-△V₃)×8C+V_EB3×4C-△V₃×4C (9)

then according to the principle of conservation of charge, equation (6) is (9), which yields:

that is, the output result of the comparator is 1 → 1, and the previous period of the differential voltage value is subtracted by gamma (alpha delta V)_EB+ βV_EB3) Wherein α Δ V_EB+βV_EB3Adding gamma (alpha delta V) as reference voltage value in the period_EB+βV_EB3) The overall differential voltage value is unchanged. In this example 2, 1 respectively, and gamma is the overall reference voltage value adjustable coefficient of

Wherein Vxp3 represents the positive terminal voltage value of the common terminal in the phase of phi 1 cycle, Vxn3 represents the negative terminal voltage value of the common terminal in the phase of phi 1 cycle, and DeltaV₃Representing the differential voltage value in phase at period Φ 1.

In the period phi 1, the output result of the comparator is still 1, and in the phase phi 1 with high clock, the level signals of the switches are:

signal	Logic level
		Clock CLK (phi 1)	1
The comparison result of the present period	1
		SC3/SB0	0
SC2/SB1	1
		SC0/SB3	1
SC1/SB2	0
		SCC_0/SC_1/SBC_1/SB_0	1
SCC_1/SC_0/SBC_0/SB_1	0

The capacitance connection is as shown in fig. 10 (phi 1 phase), the charge distribution with respect to the positive common terminal is calculated as:

(aV_EB2-Vxp4)×8C+(0-Vxp4)×4C (10)

for the common-side negative terminal, the charge is calculated as:

(aV_EB1-Vxn4)×8C+(0-Vxn4)×4C (11)

because of the fully differential design, the positive side minus the negative side [ (10) - (11) ] yields:

(a△V_EB-△V₄)×8C-V_EB3×4C-△V₄×4C (12)

because of the two switching operations, the total amount of charge is the same, i.e. equation (9) is (12), which results in:

i.e. the differential voltage value is subtracted during the period phi 1

Wherein Vxp4 represents the voltage value of the positive terminal of the common terminal in the phase of-phi 1, Vxn4 represents the voltage value of the negative terminal of the common terminal in the phase of-phi 1, and DeltaV₂Representing the differential voltage value in the cycle-phi phase.

Entering a period phi 2, assuming that the output result of the comparator is 0, and in a phi 2 phase with a low clock, the level signals of the switches are:

signal	LogicLevel of electricity
		Clock CLK (phi)	0
The comparison result of the present period	0
		SC3/SB0	0
SC2/SB1	1
		SC0/SB3	0
SC1/SB2	1
		SCC_0/SC_1/SBC_1/SB_0	0
SCC_1/SC_0/SBC_0/SB_1	1

The capacitance connection is as shown in fig. 11(Φ 2 phase), and the charge distribution is calculated as:

(aV_EB1-Vxp5)×8C+(V_EB3-Vxp5)×4C (13)

for the common-side negative terminal, the charge is calculated as:

(aV_EB2-Vxn5)×8C+(0-Vxn5)×4C (14)

because of the fully differential design, the positive side minus the negative side [ (13) - (14) ] yields:

(-a△V_EB-△V₅)×8C+V_EB3×4C-△V₅×4C (15)

then according to the principle of conservation of charge, equation (12) is (15), which yields:

wherein Vxp5 represents the positive terminal voltage value of the common terminal in the phase phi 2 of the cycle, Vxn5 represents the negative terminal voltage value of the common terminal in the phase phi 2 of the cycle, and DeltaV₅Representing the differential voltage value in phase phi 2 of the cycle.

As shown in fig. 11, in the period Φ 2, in the Φ phase where the clock is high, the level signals of the respective switches are:

the capacitance connection is as shown in fig. 11 (phi 2 phase), then the charge distribution relative to the common terminal positive terminal is calculated as:

(aV_EB1-Vxp6)×8C+(V_EB3-Vxp6)×4C (16)

for the common-side negative terminal, the charge is calculated as:

(aV_EB2-Vxn6)×8C+(0-Vxn6)×4C (17)

because of the fully differential design, the positive terminal minus the negative terminal [ (16) - (17) ] yields:

(-a△V_EB-△V₆)×8C+V_EB3×4C-△V₆×4C (18)

two times of switch switching, the total amount of charge is the same, namely, the formula (15) is equal to (18), and the following result is obtained:

△V₆＝△V₅

within the period phi 2, the differential voltage value is half the first periodThe period (. PHI.2) is unchanged. That is, the output result of the comparator is from 1 → 0, and the difference voltage value is added with gamma (alpha delta V)_EB+βV_EB3) Wherein α Δ V_EB+βV_EB3For reference voltage values, in this example 2, 1 respectively, gamma for the overall reference voltage value can be adjusted by a factor of

Wherein Vxp6 represents the voltage value of the positive terminal of the common terminal in the phase of-phi 2, Vxn6 represents the voltage value of the negative terminal of the common terminal in the phase of-phi 2, and DeltaV₆Representing the differential voltage value in the cycle- Φ 2 phase.

In the period Φ 3, assuming that the comparator output result is still 0, the level signal of each switch is at Φ 3 phase where the clock is low

The capacitance connection is as shown in fig. 12(Φ 3 phase), and the charge distribution is calculated as:

(aV_EB2-Vxp7)×8C+(0-Vxp7)×4C (19)

for the common terminal negative terminal, the charge is calculated as

(aV_EB1-Vxn7)×8C+(V_EB3-Vxn7)×4C (20)

Because of the fully differential design, the positive terminal minus the negative terminals [ (19) - (20) ] results

(-a△V_EB-△V₇)×8C-V_EB3×4C-△V₇×4C (21)

Then, according to the principle of conservation of charge, equation (21) is equal to (18) to obtain

That is, the output result of the comparator is 0 → 0, and the differential voltage value is subtracted by a (beta delta V) from the previous period_EB+ γV_EB3)。

Wherein Vxp7 represents the positive terminal voltage value of the common terminal in the phase phi 3 of the cycle, Vxn7 represents the negative terminal voltage value of the common terminal in the phase phi 3 of the cycle, and DeltaV₇Representing the differential voltage value in phase phi 3 of the cycle.

In the period phi 3, the output result of the comparator is still 0, and in the phase phi 3 with high clock, the level signals of the switches are:

the capacitance connection is as shown in fig. 12 (phi 3 phase), the charge distribution relative to the common terminal positive terminal is calculated as:

(aV_EB1-Vxp8)×8C+(V_EB3-Vxp8)×4C (22)

for the common terminal negative terminal, the charge is calculated as

(aV_EB2-Vxn8)×8C+(0-Vxn8)×4C (23)

Because of the fully differential design, the positive terminal minus the negative terminals [ (22) - (23) ] results

(a△V_EB-△V₈)×8C+V_EB3×4C-△V₈×4C (24)

Because of the two switching times, the total charge is the same, i.e. the formula (24) is equal to (21), and the total charge is obtained

I.e. within the period phi 3, the differential voltage value is subtracted

That is, the output result of the comparator is from 0 → 0, and the previous period of the differential voltage value is subtracted by a (beta delta V)_EB+ γV_EB3) In the reverse phase (when the level is high) of the cycle, α x (β Δ V) is added_EB+γV_EB3) The overall differential voltage value is unchanged.

Wherein Vxp8 represents the voltage value of the positive terminal of the common terminal in the phase of-phi 3, Vxn8 represents the voltage value of the negative terminal of the common terminal in the phase of-phi 3, and DeltaV₈Representing the differential voltage value in the cycle-3 phase.

Entering a period Φ 4, assuming that the comparator output results jump from 0 to 1, in the Φ 4 phase where the clock is low, the level signals of the respective switches are:

the capacitance connection is as shown in fig. 13(Φ 4 phase), then the charge distribution with respect to the positive common terminal is calculated as:

(aV_EB2-Vxp9)×8C+(0-Vxp9)×4C (25)

for the common terminal negative terminal, the charge is calculated as

(aV_EB1-Vxn9)×8C+(V_EB3-Vxn9)×4C (26)

Because of the fully differential design, the positive terminal minus the negative terminals [ (25) - (26) ] results

(-a△V_EB-△V₉)×8C-V_EB3×4C-△V₉×4C (27)

Then, according to the principle of conservation of charge, the formula (27) is equal to (24) to obtain

Wherein Vxp9 represents the positive terminal voltage value of the common terminal in the phase phi 4 of the cycle, Vxn9 represents the negative terminal voltage value of the common terminal in the phase phi 4 of the cycle, and DeltaV₉Representing the differential voltage value in phase phi 4 of the cycle.

In the period phi 4, the clock is high in phi phase, and the level signal of each switch is

The capacitance connection is as shown in fig. 13 (phi 4 phase), then the charge distribution relative to the common terminal positive terminal is calculated as:

(aV_EB2-Vxp10)×8C+(0-Vxp10)×4C (28)

for the common terminal negative terminal, the charge is calculated as

(aV_EB1-Vxn10)×8C+(V_EB3–Vxn10)×4C (29)

Because of the fully differential design, the positive terminal minus the negative terminals [ (28) - (29) ] results

(-a△V_EB-△V₁₀)×8C+V_EB3×4C-△V₁₀×4C (30)

Two times of switch switching, the total amount of charge is the same, namely, the formula (30) is equal to (27), and the result is

△V₁₀＝△V₉

In the period phi 4, the differential voltage value is unchanged. That is, the comparator output is subtracted from 0 → 1, the differential voltage value is subtracted by gamma (alpha delta V)_EB+βV_EB3) Wherein α Δ V_EB+βV_EB3For reference voltage values, in this example 2, 1 respectively, gamma for the overall reference voltage value can be adjusted by a factor of

Wherein Vxp10 represents the voltage value of the positive terminal of the common terminal in the period-phi 4 phase, Vxn10 represents the voltage value of the negative terminal of the common terminal in the period-phi 4 phase, and DeltaV₁₀Representing the differential voltage value in the cycle-4 phase.

Through the above analysis, the comparison result (the case of 1 → 1 → 0 → 0 → 1) is traversed, that is, when the present cycle to the next cycle as the comparator output result is from 1 → 0, the differential voltage value is added

If the comparator output results from 0 → 1, then the differential voltage value is subtracted

In summary, when the two comparisons are different, the difference value

Through the implementation, the invention can determine the switching of each switch through the output result of the comparator, and the constant differential voltage value can be realized in the period through the charge conservation principle. In the next period, a reference voltage is added or subtracted to or from the differential voltage value according to the output result of the comparator. The invention is also suitable for reference voltage generation of modulation in Delta-Sigma ADCs of other various architectures.

In the embodiment of the invention, the constant/added/subtracted reference voltage value is directly determined according to the output result of the comparator at the clock falling edge establishment and the next clock falling edge.

Through the steps, the reference voltage trimming circuit provided by the invention realizes the generation of the reference voltage and the addition and subtraction of the reference voltage under the output result state of each comparator.

As can be seen from the above embodiments, the present invention can realize the addition or subtraction of the differential voltage to or from the reference voltage in the present period without additional period according to the output result of the comparator by the reference voltage generation of the modulator in the Delta-Sigma ADC. Negative trimming, the method solves the problems that the traditional reference voltage depends on a resistor, the resistor occupies a large layout area, has poor precision and is sensitive to temperature, and the problems can be solved by directly generating the reference voltage by adopting a switched capacitor circuit.

Other embodiments of the invention will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the invention following, in general, the principles of the invention and including such departures from the present disclosure as come within known or customary practice within the art to which the invention pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the invention being indicated by the following claims.

In the description of the present invention, it is to be understood that the terms "coaxial", "bottom", "one end", "top", "middle", "other end", "upper", "one side", "top", "inner", "outer", "front", "center", "two ends", and the like, indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, are not to be construed as limiting the present invention.

In the present invention, unless otherwise specifically stated or limited, the terms "mounted," "disposed," "connected," "fixed," "rotated," and the like are to be construed broadly, e.g., as meaning fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; the terms may be directly connected or indirectly connected through an intermediate, and may be communication between two elements or interaction relationship between two elements, unless otherwise specifically limited, and the specific meaning of the terms in the present invention will be understood by those skilled in the art according to specific situations.

Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.

Claims

1. A reference voltage generation circuit for a modulator, the circuit being controlled by the result output from a 1-bit comparator of the modulator, includes a differential reference voltage generation circuit and a reference V_EBA voltage generating circuit; the differential reference voltage generation positive terminal is connected with the common terminal positive terminal, the differential reference voltage generation negative terminal is connected with the common terminal negative terminal, and the reference V is connected with the reference V_EBThe voltage generation positive terminal circuit is connected with a common terminal positive terminal and a reference V_EBThe voltage generation negative terminal circuit is connected with a public terminal negative terminal;

each differential reference voltage generating circuit comprises a first input voltage source and a second input voltage source, each input voltage source is connected with one end of a first switch and one end of a second switch, the other end of the first switch is connected with an upper plate of a first capacitor and an upper plate of a second capacitor, the other end of the second switch is connected with an upper plate of a third capacitor, and a lower plate of the third capacitor is connected with an upper plate of a fourth capacitor, one end of the third switch and one end of the fourth switch; the common-mode voltage VCM is connected with the lower plates of the first capacitor, the second capacitor and the fourth capacitor and the other end of the third switch, the other end of the fourth switch is connected with a positive end or a negative end of a common end, and the other end of the first switch of any one of the first input voltage source and the second input voltage source is connected with the other end of the second switch of the other input voltage source; and the other ends of the fourth switches of the two input voltage sources are connected with each other;

each reference V_EBThe voltage generation circuit comprises a third input voltage source and a fourth input voltage source, each input voltage source is connected with one end of a fifth switch and one end of a sixth switch, the other ends of the fifth switch and the sixth switch are respectively connected with corresponding branches, in each branch, the other end of the branch is connected with a fifth capacitor and a higher-level plate of a sixth capacitor, and the lower-level plate of the sixth capacitor is connected with a higher-level plate of a seventh capacitor, one end of a seventh switch and one end of an eighth switch; the other ends of the fifth switch, the seventh switch and the lower plate of the fifth capacitor and the seventh capacitor are connected with a common-mode voltage VCM, the other end of the eighth switch is connected with a positive end or a negative end of a common end, and the other end of the fifth switch of any one of a third input voltage source and a fourth input voltage source is connected with the other end of the sixth switch of the other input voltage source; and the other ends of the eighth switches of the two input voltage sources are connected to each other.

2. The reference voltage generating circuit of claim 1, wherein the first input voltage source is a x V_EB1The second input voltage source is a V_EB2The third input voltage source is 1 x V_EB3The fourth input voltage source is the ground GND, and a represents the input voltage source coefficient.

3. A reference voltage generating circuit for a modulator according to claim 1, wherein the circuit is controlled by the result outputted from the 1-bit comparator of the modulator, that is, the switching of each switch is controlled by the result outputted from the comparator.

4. The reference voltage generating circuit for a modulator according to claim 1, wherein the first switch of the first input voltage source and the first switch of the second input voltage source are controlled by the result output from the same 1-bit comparator, and wherein a sixth switch of the fourth voltage input source is a fifth switch of the third voltage input source, and wherein a sixth switch of the third voltage input source is a fifth switch of the fourth voltage input source; the first switch of the first voltage input source is the fifth switch of the third voltage input source, the second switch of the second voltage input source is the sixth switch of the fourth voltage input source, the second switch of the first voltage input source is the sixth switch of the third voltage input source, and the first switch of the second voltage input source is the first switch of the first voltage input source; the eighth switch of the fourth input voltage source has the same phase with the clock, and the eighth switch of the third input voltage source has the opposite phase with the clock; the eighth switch of the fourth input voltage source is equal to the fourth switch of the second input voltage source, which is equal to the seventh switch of the third input voltage source; the eighth switch of the third input voltage source is the fourth switch of the first input voltage source, and the seventh switch of the fourth voltage input source, where "═ indicates that the input control signals are the same.

5. A method for reference voltage generation for a modulator, the method comprising:

determining the differential reference voltage generation circuit and the reference V at the current cycle based on the output of the 1-bit comparator of the modulator_EBA switch state in the voltage generation circuit;

respectively calculating the charge distribution of the positive end and the negative end of the public end based on the positive/negative reference voltage generated in the current period, and obtaining the corresponding differential charge distribution difference;

6. The method of claim 5, wherein the differential reference voltage generation circuit and the reference V are determined according to the result output from the 1-bit comparator of the modulator_EBThe switching state in the voltage generation circuit includes modifying the sizes of the first equivalent capacitor C1 and the second equivalent capacitor C2 according to the output result of the 1-bit comparator of the modulator, and determining the current period differential reference voltage generation circuit and the reference V by connecting/disconnecting the third equivalent capacitor C3_EBSwitch states in the voltage generating circuit.

7. A method of generating reference voltages for use in a modulator according to claim 5 including establishing a clock falling edge after determining the positive/negative reference voltage value generated and determining directly on the next clock falling edge from the comparator output result the constant/reference voltage value added/reference voltage value subtracted.