CN111555727B - High-gain low-noise switched capacitor adjustable gain amplifier - Google Patents
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G3/00—Gain control in amplifiers or frequency changers without distortion of the input signal
- H03G3/20—Automatic control
- H03G3/30—Automatic control in amplifiers having semiconductor devices
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G3/00—Gain control in amplifiers or frequency changers without distortion of the input signal
- H03G3/008—Control by switched capacitors
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Abstract
The invention provides a high-gain low-noise switched capacitor adjustable gain amplifier, which comprises an external signal source, a square wave generator, a switched capacitor integrator and a feedback circuit with a signal amplifying function, wherein the external signal source and the square wave generator are connected with the switched capacitor integrator, the switched capacitor integrator outputs through the feedback circuit, the switched capacitor integrator comprises 7 CMOS switching tubes which are started by forward pulses, a sampling capacitor, an adjustable feedback capacitor and an integrating capacitor, and the feedback circuit comprises an operational amplifier. The integrated frequency of the feedback capacitor is reduced in time to reduce the capacitance of the feedback capacitor, so that the PGA noise is reduced while high gain is realized, the layout area of the circuit is not increased, the power consumption and the cost are reduced, the detection precision and the detection efficiency of the circuit are improved, the integrated frequency feedback circuit is suitable for various sensor interfaces, signal conditioning chips and signal links, and the integrated frequency feedback circuit has great market development prospects in automobile electronics, white household appliances, industrial automation and the Internet of things.
Description
Technical Field
The invention relates to the field of integrated circuit design, in particular to a high-gain low-noise switched capacitor adjustable gain amplifier.
Background
Switched capacitor adjustable gain amplifiers (programmable gain amplifier, PGA) are commonly used in sensor signal detection, analog-to-digital signal conversion (ADC) and digital-to-analog (DAC) conversion circuits. However, the currently-used switched capacitor PGA circuit often uses a method of increasing the ratio of the input capacitance and the feedback capacitance of the switched capacitor amplifier or using a cascade of two-stage switched capacitor amplifiers when achieving higher gain. The former achieves high gain while noise amplification of the switched capacitor is substantial, and the latter suffers from disadvantages in terms of both power consumption and chip area for delta.
As shown in fig. 1, the common single-ended output switched capacitor PGA is an example, the control clock signal of the CMOS switch is an equal-time-length two-phase square wave with non-overlapping characteristics, the pulse square wave of the first phase is a sampling time, the pulse square wave of the second phase is an amplifying or integrating time, and the charges of the sampling capacitor and the adjustable feedback capacitor are integrated by a feedback path through an operational amplifier. In the figure 120, the non-overlapping pulse generator generates the gate control signal of the switching tube, and phi 1 and phi 2 are the sampling and integration periods, respectively.
This achieves sampling and amplification of the signal over a period of time. According to the working principle of the switch capacitor, the amplification factor of the PGA at phi 2 is the ratio of the input capacitor to the feedback capacitor:
Gain＝Vout(n)/Vin(n)＝C 104 /C 108
where n is the number of pulse cycles.
Noise from the switched capacitor is a key indicator affecting the accuracy of the output signal, and the high-amplification PGA should be designed to reduce noise as much as possible. In fig. 1, the switched capacitor noise entering the inverting input of the op-amp is expressed in terms of charge:
where K is a constant and T is an absolute temperature value.
If converted to the input switched capacitor 104, the equivalent noise voltage at the input is expressed as:
the noise voltage at the output is:
in equation (3), the Gain is a value set for amplifying the PGA signal, and generally Gain >1, it can be seen that the equivalent output noise of PGA must be increased by the capacitance of the adjustable capacitor 108 when Gain is a set value. But increasing the capacitance of capacitor 108 is severely limited,
1. increasing the capacitance value of 108, and correspondingly increasing the capacitance value of 104 is needed to keep the Gain unchanged; at the same time, in order to keep a certain system bandwidth, filter noise and prevent the closed loop feedback coefficient of the operational amplifier 111 from decreasing to affect the integration precision, the capacitance of the integration capacitor 102 must also be increased. As a result, the area required for the chip must be significantly increased and the cost increased.
2. If the capacitance of 108 and 104 is increased at the same time, the power consumption is increased, because the charge-discharge current required for the op-amp 111 to complete integration is significantly increased and the chip power consumption is increased.
In practical application, most PGAs with a fully differential structure have unchanged principle. The above equation for switched capacitor noise is the same as the problem encountered.
Disclosure of Invention
The invention aims to provide the high-gain low-noise switch capacitor adjustable gain amplifier, which reduces the integrated frequency of the feedback capacitor in time to reduce the capacitance value of the feedback capacitor, reduces the noise of a switch capacitor circuit under the condition of realizing high gain, simultaneously does not increase the layout area of the circuit, reduces the power consumption and the cost, improves the detection precision and the efficiency of a signal detection circuit, is suitable for various sensor interfaces, signal conditioning chips and signal links, and has great market development prospect in automobile electronics, white household appliances, industrial automation and the Internet of things.
The technical solution for realizing the purpose of the invention is as follows:
a high gain low noise switched capacitor adjustable gain amplifier comprising: the external signal source is connected with the switch capacitor integrator, and the square wave generator is used for generating a frequency division control clock signal to the switch capacitor integrator which outputs through the feedback circuit; the switching capacitor integrator comprises 7 CMOS switching tubes started by forward pulse, a sampling capacitor, an adjustable feedback capacitor and an integrating capacitor, wherein the feedback circuit comprises an operational amplifier, and the CMOS switching tubes started by the forward pulse are all connected with the square wave generator and comprise a first CMOS switching tube, a second CMOS switching tube, a third CMOS switching tube, a fourth CMOS switching tube, a fifth CMOS switching tube, a sixth CMOS switching tube and a seventh CMOS switching tube; one end of the second CMOS switch tube is connected with an external signal source to acquire an input signal, the other end of the second CMOS switch tube is connected with one end of the sampling capacitor and one end of the third CMOS switch tube, and the other end of the third CMOS switch tube is grounded; the other end of the sampling capacitor is commonly connected with one end of the first CMOS switching tube, one end of the fourth CMOS switching tube and one end of the adjustable feedback capacitor, and the other end of the fourth CMOS switching tube is grounded; the other end of the first CMOS switch tube is connected with the reverse input end of the operational amplifier; the two ends of the integrating capacitor are respectively connected with the reverse input end and the output end of the operational amplifier, and the positive input end of the operational amplifier is grounded; the other end of the adjustable feedback capacitor is commonly connected with one end of a fifth CMOS switching tube, one end of a seventh CMOS switching tube and one end of a sixth CMOS switching tube, the other end of the fifth CMOS switching tube and the other end of the seventh CMOS switching tube are grounded, the other end of the sixth CMOS switching tube is connected with the output end of an operational amplifier, and the output end of the operational amplifier is a total output end output signal; the square wave generator comprises an oscillator circuit, a phase non-overlapping circuit and a frequency divider which are connected in sequence and is used for generating an equal-time long double-phase non-overlapping clock signal, wherein the square wave of a first phase is sampling time, and the square wave of a second phase is integration time.
Further, in the high-gain low-noise switched capacitor adjustable gain amplifier of the invention, the square wave generator outputs a clock signal to the sampling capacitor, and the sampling capacitor is controlled to sample and integrate an input signal in two time periods of one clock period, wherein the sampling time period = integration time period.
Furthermore, the high-gain low-noise switched capacitor adjustable gain amplifier of the invention, the square wave generator outputs the clock signal to the adjustable feedback capacitor, and controls the adjustable feedback capacitor to sample and integrate the input signal in two time periods of one clock period, wherein the sampling time period is the sampling time period after N times of frequency division, namely: every N periods, wherein 1 period is an effective sampling period, the rest N-1 periods are null samples, N is a frequency division coefficient and is controlled by a frequency divider, and the integration time period of the N is consistent with the integration time period of a control sampling capacitor.
Further, in the high-gain low-noise switched capacitor adjustable gain amplifier of the invention, the average sampled charge amount of the feedback capacitor (108) is: (Q) 108 ) AVE ＝Vout·C 108 /N。
The use of a high gain low noise switched capacitor adjustable gain amplifier as described in any of the above in a switched capacitor adjustable gain circuit for signal detection, analog to digital conversion, sensor signal amplification and conditioning.
A sampling and integrating time control method of a switching capacitor adjustable gain amplifier is used for respectively controlling a sampling time period and an integrating time period of an adjustable feedback capacitor of the switching capacitor adjustable gain amplifier:
1) Controlling the clock signal of the integration time period of the adjustable feedback capacitor to be consistent with the clock signal of the integration time period of the sampling capacitor;
2) The clock signal controlling the sampling time period of the adjustable feedback capacitor is a clock signal subjected to frequency division by N times, namely the effective sampling time period of the adjustable feedback capacitor in every N periods is 1 period, the sampling of other N-1 periods is null sampling, and the sampling voltage is 0 in null sampling, wherein N is a frequency division coefficient.
Compared with the prior art, the technical scheme provided by the invention has the following technical effects:
the high-gain low-noise switched capacitor adjustable gain amplifier provided by the invention has the advantages that the amplification factor is increased, the real capacitance value of the adjustable feedback capacitor is not reduced to cause noise increase, the capacitance value of the adjustable feedback capacitor is not increased, the capacitance value of the integrating capacitor 102 is synchronously increased to cause the increase of the chip area and the charge and discharge flow of the operational amplifier, and the high amplification factor is obtained, and meanwhile, the occupied chip area and the occupied power consumption are not increased.
Drawings
Fig. 1 is a circuit schematic of a conventional single-ended output switched capacitor PGA.
Fig. 2 is a circuit schematic of a high gain low noise switched capacitor adjustable gain amplifier of the present invention.
Fig. 3 is a schematic diagram of a control clock for a high gain low noise switched capacitor adjustable gain amplifier of the present invention with a frequency division multiple of 4.
Fig. 4 is a schematic diagram of a fully differential architecture of a high gain low noise switched capacitor adjustable gain amplifier of the present invention.
Reference numerals meaning: 101: signal sources, 103, 105, 106, 107, 109, 110, 209: forward pulse on CMOS switching tube, 102: integration capacitance, 104: sampling capacitance, 108: the adjustable feedback capacitance, 111 is an operational amplifier, 301: differential mode input signal, 302: common mode input signals, 303-312: CMOS switching tubes, 320, 321: input capacitance pair, 322, 323: feedback capacitance pair, 324, 325: integrating capacitance pair, 331: and a fully differential output operational amplifier.
Detailed Description
Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals refer to the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the drawings are exemplary only for explaining the present invention and are not to be construed as limiting the present invention.
A high gain low noise switched capacitor adjustable gain amplifier, as shown in fig. 2, comprising: the external signal source is connected with the switch capacitor integrator, and the square wave generator is used for generating a frequency division control clock signal to the switch capacitor integrator, and the switch capacitor integrator outputs through the feedback circuit.
The switched capacitor integrator comprises 7 CMOS switching tubes started by forward pulse, a sampling capacitor 104, an adjustable feedback capacitor 108 and an integrating capacitor 102, wherein the feedback circuit comprises an operational amplifier 111, and the CMOS switching tubes started by the forward pulse are all connected with the square wave generator and comprise a first CMOS switching tube 103, a second CMOS switching tube 105, a third CMOS switching tube 106, a fourth CMOS switching tube 107, a fifth CMOS switching tube 109, a sixth CMOS switching tube 110 and a seventh CMOS switching tube 209.
One end of the second CMOS switch tube 105 is connected with an external signal source to acquire an input signal, the other end of the second CMOS switch tube 105 is commonly connected with one end of the sampling capacitor 104 and one end of the third CMOS switch tube 106, and the other end of the third CMOS switch tube 106 is grounded; the other end of the sampling capacitor 104 is commonly connected with one end of the first CMOS switch tube 103, one end of the fourth CMOS switch tube 107 and one end of the adjustable feedback capacitor 108, and the other end of the fourth CMOS switch tube 107 is grounded; the other end of the first CMOS switch tube 103 is connected with the reverse input end of the operational amplifier 111; the two ends of the integrating capacitor 102 are respectively connected with the reverse input end and the output end of the operational amplifier 111, and the positive input end of the operational amplifier 111 is grounded; the other end of the adjustable feedback capacitor 108 is commonly connected with one end of the fifth CMOS switch tube 109, one end of the seventh CMOS switch tube 209 and one end of the sixth CMOS switch tube 110, the other end of the fifth CMOS switch tube 109 and the other end of the seventh CMOS switch tube 209 are grounded, the other end of the sixth CMOS switch tube 110 is connected with the output end of the operational amplifier 111, and the output end of the operational amplifier is a total output end output signal.
The square wave generator comprises an oscillator circuit, a phase non-overlapping circuit and a frequency divider which are connected in sequence and is used for generating an equal-time long double-phase non-overlapping clock signal, wherein the square wave of a first phase is sampling time, and the square wave of a second phase is integration time.
Example 1
A high gain low noise switched capacitor adjustable gain amplifier, as shown in fig. 2, comprising: the external signal source is connected with the switch capacitor integrator, and the square wave generator is used for generating a frequency division control clock signal to the switch capacitor integrator, and the switch capacitor integrator outputs through the feedback circuit.
The switched capacitor integrator comprises 7 CMOS switching tubes started by forward pulse, a sampling capacitor 104, an adjustable feedback capacitor 108 and an integrating capacitor 102, wherein the feedback circuit comprises an operational amplifier 111, and the CMOS switching tubes started by the forward pulse are all connected with the square wave generator and comprise a first CMOS switching tube 103, a second CMOS switching tube 105, a third CMOS switching tube 106, a fourth CMOS switching tube 107, a fifth CMOS switching tube 109, a sixth CMOS switching tube 110 and a seventh CMOS switching tube 209.
One end of the second CMOS switch tube 105 is connected with an external signal source to acquire an input signal, the other end of the second CMOS switch tube 105 is commonly connected with one end of the sampling capacitor 104 and one end of the third CMOS switch tube 106, and the other end of the third CMOS switch tube 106 is grounded; the other end of the sampling capacitor 104 is commonly connected with one end of the first CMOS switch tube 103, one end of the fourth CMOS switch tube 107 and one end of the adjustable feedback capacitor 108, and the other end of the fourth CMOS switch tube 107 is grounded; the other end of the first CMOS switch tube 103 is connected with the reverse input end of the operational amplifier 111; the two ends of the integrating capacitor 102 are respectively connected with the reverse input end and the output end of the operational amplifier 111, and the positive input end of the operational amplifier 111 is grounded; the other end of the adjustable feedback capacitor 108 is commonly connected with one end of the fifth CMOS switch tube 109, one end of the seventh CMOS switch tube 209 and one end of the sixth CMOS switch tube 110, the other end of the fifth CMOS switch tube 109 and the other end of the seventh CMOS switch tube 209 are grounded, the other end of the sixth CMOS switch tube 110 is connected with the output end of the operational amplifier 111, and the output end of the operational amplifier is a total output end output signal.
The square wave generator comprises an oscillator circuit, a phase non-overlapping circuit and a frequency divider which are connected in sequence and is used for generating an equal-time long double-phase non-overlapping clock signal, wherein the square wave of a first phase is sampling time, and the square wave of a second phase is integration time. The square wave generator outputs a clock signal to the sampling capacitor 104, and controls the sampling capacitor 104 to sample and integrate an input signal in two periods of one clock cycle, where the sampling period=the integration period. The square wave generator outputs a clock signal to the adjustable feedback capacitor 108, and controls the adjustable feedback capacitor 108 to sample and integrate an input signal in two time periods of one clock period, wherein the sampling time period is a sampling time period after N times of frequency division, namely: every N periods, wherein 1 period is an effective sampling period, the rest N-1 periods are null samples, N is a frequency division coefficient and is controlled by a frequency divider, and the integration period of the N periods is consistent with the integration period of the control sampling capacitor 104. The feedback capacitance 108 samples an average amount of charge every N cycles as: (Q) 108 ) AVE ＝Vout·C 108 /N。
The application of a high-gain low-noise switched capacitor adjustable gain amplifier in a switched capacitor adjustable gain circuit for signal detection, analog-to-digital conversion, sensor signal amplification and conditioning.
A sampling and integration time control method of a switched capacitor adjustable gain amplifier controls the sampling time period and the integration time period of an adjustable feedback capacitor 108 of the switched capacitor adjustable gain amplifier respectively:
1) The clock signal controlling the integration period of the adjustable feedback capacitance 108 coincides with the clock signal of the integration period of the sampling capacitance 104;
2) The clock signal controlling the sampling period of the adjustable feedback capacitor 108 is a clock signal divided by N times, i.e. the effective sampling period of the adjustable feedback capacitor 108 is 1 period in every N periods, the sampling of the other N-1 periods is null sampling, i.e. the sampled voltage is 0, where N is the frequency division coefficient.
As shown in fig. 3, 220 and 221 are control signals generated by the square wave generator for controlling the CMOS switching tube, where Φ1 and Φ2 are a sampling period and an integration period, respectively, 222 and 223 are control signals processed by the frequency divider of the sixth CMOS switching tube 110 and the seventh CMOS switching tube 209, respectively, and in this embodiment, the frequency division coefficient n=4, and 224 is the output voltage waveform of Vout when the frequency division coefficient n=4.
1) During the sampling period Φ1 of the first cycle, the second, fourth, and sixth CMOS switching transistors 105, 107, and 110 are closed, and the other switching transistors are open. The sampling capacitance 104 and the adjustable feedback capacitance 108 are charged to Vin C by Vin and Vout, respectively 104 And Vout.C 108 。
2) During the integration period phi 2 of the first cycle, the third CMOS switch tube 106, the first CMOS switch tube 103 and the fifth CMOS switch tube 109 are closed and the other switch tubes are open. The charge in the sampling capacitor 104 and the adjustable feedback capacitor 108 is driven into the integrating capacitor 102, and at this time, the output voltage changes by the following amount:
ΔVout＝(Vin·C 104 -Vout·C 108 )/C 102
3) In the following 3 consecutive cycles (i.e. the second cycle to the fourth cycle), the sixth CMOS switch tube 110 remains open at all times and the seventh CMOS switch tube 209 is closed for a sampling period, as shown by 222, 223 in fig. 3, to achieve zero or "null sampling" of the adjustable feedback capacitance 108. The amount of change in output voltage after 4 cycles is:
ΔVout＝(Vin·4·C 104 - Vout·C 108 )/C 102 (4)
it can be seen from equation (4) that when the frequency division is 4, the equivalent of the adjustable feedback capacitance 108 is one fourth of the sampling capacitance 104, and from the average of the output voltages, the equivalent of the amplification is 4 times, as in 224 of fig. 3.
From each switched capacitor (sampling capacitor 104 and adjustable feedback capacitor 108), during the time period of each clock cycle, both plates of the capacitor are connected with a switch to operate, and the capacitance value of the capacitor does not change before and after improvement. The switched capacitor noise defined by equations (1) - (3) is still applicable, i.e. it is achieved that the amplification factor becomes 4 without increasing the output noise from the switched capacitor integrator.
The allocation factor is not limited to 4 in application and can be designed as other suitable integers. It should be noted that as the division multiple increases, the integration time constant increases and the bandwidth decreases.
Example 2
As shown in fig. 4, the switching capacitor adjustable gain amplifier with a fully differential structure has the same principle as a PGA circuit with single-ended output, but has more practical value due to the symmetrical structure.
The switch capacitor adjustable gain amplifier with the fully differential structure comprises an external signal source, a square wave generator with a frequency division function, a switch capacitor integrator and a fully differential output operational amplifier 331, wherein the external signal source is connected with the switch capacitor integrator, the square wave generator is used for generating a frequency division control clock signal to the switch capacitor integrator, and the switch capacitor integrator outputs through the fully differential output operational amplifier;
the external signal source comprises a differential mode input signal source 301 and a common mode input signal source 302, the differential mode input signal source 301 and the common mode input signal source 302 are sequentially connected, the other end of the common mode input signal source 302 is grounded, the switched capacitor integrator comprises 7 pairs of CMOS switching tube pairs which are turned on by forward pulses, input capacitor pairs 320 and 321, feedback capacitor pairs 322 and 323 and integrating capacitor pairs 324 and 325, and the CMOS switching tube pairs which are turned on by the forward pulses are connected with square wave generators respectively, namely 303 and 304, 305 and 306, 307 and 308, 309 and 310, 311 and 312, 313 and 314, 315 and 316;
one end of the CMOS switch tube 303 is connected with the differential mode input signal source 301 to acquire an input signal, the other end of the CMOS switch tube 303 is connected with one end of the input capacitor 320 and one end of the CMOS switch tube 305, and the other end of the CMOS switch tube 305 is grounded; the other end of the input capacitor 320 is commonly connected with one end of the CMOS switch tube 309, one end of the CMOS switch tube 307 and one end of the feedback capacitor 322, and the other end of the CMOS switch tube 307 is grounded; the other end of the CMOS switch tube 309 and one end of the integration capacitor 324 are connected with the reverse input end of the fully differential output operational amplifier 331; the other end of the integrating capacitor 324 is connected with the positive output end of the fully differential output operational amplifier 331; the other end of the feedback capacitor 322 is commonly connected with one end of the CMOS switch tube 311, one end of the CMOS switch tube 313 and one end of the CMOS switch tube 315, the other end of the CMOS switch tube 311 and the other end of the CMOS switch tube 313 are grounded, the other end of the CMOS switch tube 315 is connected with the forward output end of the full differential output operational amplifier 331, and the forward output end of the full differential output operational amplifier 331 is a total forward output end output signal.
One end of the CMOS switch tube 304 is connected with the common-mode input signal source 302 to acquire an input signal, the other end of the CMOS switch tube 304 is connected with one end of the input capacitor 321 and one end of the CMOS switch tube 306, and the other end of the CMOS switch tube 306 is grounded; the other end of the input capacitor 321 is commonly connected with one end of the CMOS switch tube 310, one end of the CMOS switch tube 308 and one end of the feedback capacitor 323, and the other end of the CMOS switch tube 308 is grounded; the other end of the CMOS switch tube 310 and one end of the integrating capacitor 325 are connected with the positive input end of the fully differential output operational amplifier 331; the other end of the integrating capacitor 325 is connected with the reverse output end of the fully differential output operational amplifier 331; the other end of the feedback capacitor 323 is commonly connected with one end of the CMOS switch tube 312, one end of the CMOS switch tube 314 and one end of the CMOS switch tube 316, the other end of the CMOS switch tube 312 and the other end of the CMOS switch tube 314 are grounded, the other end of the CMOS switch tube 316 is connected with the reverse output end of the fully differential output operational amplifier 331, and the reverse output end of the fully differential output operational amplifier 331 is a total reverse output end output signal.
The switch control signals of the CMOS switching transistors 303, 304, 307, and 308 are 220 in fig. 3, the switch control signals of the CMOS switching transistors 305, 306, 309, 310, 311, and 312 are 221 in fig. 3, the switch control signals of the CMOS switching transistors 315 and 316 are 222 in fig. 3, and the switch control signals of the CMOS switching transistors 313 and 314 are 223 in fig. 3.
The switched capacitor PGA in the above two embodiments does not increase the output noise originating from the switched capacitor while increasing the amplification factor, nor increases the chip area and power consumption. Compared with the conventional PGA circuit, the signal-to-noise ratio of the output signal is obviously improved, and the method is suitable for a signal sampling system of a sensor with low-frequency weak signal characteristics or other physical signal sources. The improved circuit has the characteristics of wide application, flexibility and variability, and can be applied to a signal acquisition system of a sensor, and can also be applied to signal processing circuits of high-precision ADC (analog-to-digital converter), DAC (digital-to-analog converter) and other switch capacitors.
While only a few embodiments of the present invention have been described, it should be noted that modifications could be made by those skilled in the art without departing from the principles of the present invention, which modifications are to be regarded as being within the scope of the invention.
Claims (6)
1. A high gain low noise switched capacitor adjustable gain amplifier comprising: the external signal source is connected with the switch capacitor integrator, and the square wave generator is used for generating a frequency division control clock signal to the switch capacitor integrator which outputs through the feedback circuit;
the switched capacitor integrator comprises 7 CMOS switching tubes started by forward pulse, a sampling capacitor (104), an adjustable feedback capacitor (108) and an integrating capacitor (102), wherein the feedback circuit comprises an operational amplifier (111), and the CMOS switching tubes started by the forward pulse are all connected with the square wave generator and comprise a first CMOS switching tube (103), a second CMOS switching tube (105), a third CMOS switching tube (106), a fourth CMOS switching tube (107), a fifth CMOS switching tube (109), a sixth CMOS switching tube (110) and a seventh CMOS switching tube (209);
one end of the second CMOS switch tube (105) is connected with an external signal source to acquire an input signal, the other end of the second CMOS switch tube (105) is commonly connected with one end of the sampling capacitor (104) and one end of the third CMOS switch tube (106), and the other end of the third CMOS switch tube (106) is grounded; the other end of the sampling capacitor (104) is commonly connected with one end of the first CMOS switch tube (103), one end of the fourth CMOS switch tube (107) and one end of the adjustable feedback capacitor (108), and the other end of the fourth CMOS switch tube (107) is grounded; the other end of the first CMOS switch tube (103) is connected with the reverse input end of the operational amplifier (111); two ends of the integrating capacitor (102) are respectively connected with an inverting input end and an output end of the operational amplifier (111), and a positive input end of the operational amplifier (111) is grounded; the other end of the adjustable feedback capacitor (108) is commonly connected with one end of a fifth CMOS switch tube (109), one end of a seventh CMOS switch tube (209) and one end of a sixth CMOS switch tube (110), the other end of the fifth CMOS switch tube (109) and the other end of the seventh CMOS switch tube (209) are grounded, the other end of the sixth CMOS switch tube (110) is connected with the output end of an operational amplifier (111), and the output end of the operational amplifier is a total output end output signal;
the square wave generator comprises an oscillator circuit, a phase non-overlapping circuit and a frequency divider which are connected in sequence and is used for generating an equal-time long double-phase non-overlapping clock signal, wherein the square wave of a first phase is sampling time, and the square wave of a second phase is integration time.
2. The high-gain low-noise switched-capacitor adjustable-gain amplifier according to claim 1, wherein the square wave generator outputs a clock signal to the CMOS switching transistor, and the sampling capacitor (104) is controlled to sample and integrate the input signal in two periods of one clock cycle, wherein the sampling period = integration period.
3. The high-gain low-noise switched-capacitor adjustable-gain amplifier according to claim 1, wherein the square wave generator outputs a clock signal to the CMOS switching tube, and the adjustable feedback capacitor (108) is controlled to sample and integrate the input signal in two periods of one clock cycle, and the sampling period is a sampling period after N times of frequency division, namely: every N periods, wherein 1 period is an effective sampling period, the rest N-1 periods are null samples, N is a frequency division coefficient and is controlled by a frequency divider, and the integration period of the N periods is consistent with the integration period of a control sampling capacitor (104).
4. A high gain low noise switched capacitor adjustable gain amplifier according to claim 3, wherein the feedback capacitor (108) samples an average amount of charge per N cycles as: (Q) 108 ) AVE ＝Vout·C 108 /N。
5. Use of a high gain low noise switched capacitor adjustable gain amplifier according to any of claims 1-4 in a switched capacitor adjustable gain circuit for signal detection, analog to digital conversion, sensor signal amplification and conditioning.
6. A method of sampling and integration time control for a switched-capacitor adjustable gain amplifier based on high gain and low noise according to any of claims 1-4, characterized by controlling the sampling time period and the integration time period of the adjustable feedback capacitor (108) of the switched-capacitor adjustable gain amplifier separately:
1) Controlling the clock signal of the integration period of the adjustable feedback capacitance (108) to coincide with the clock signal of the integration period of the sampling capacitance (104);
2) The clock signal controlling the sampling period of the adjustable feedback capacitor (108) is a clock signal subjected to frequency division by N times, namely the effective sampling period of the adjustable feedback capacitor (108) in every N periods is 1 period, the sampling of other N-1 periods is null sampling, the voltage of the null sampling is 0, and N is the frequency division coefficient.
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| CN112688687B (en) * | 2020-12-09 | 2022-07-12 | 南方电网数字电网研究院有限公司 | Method and device for acquiring physical information to be tested, computer equipment and storage medium |
| CN113381729B (en) * | 2021-06-25 | 2022-10-04 | 上海料聚微电子有限公司 | Switched capacitor integrator and control method for improving transient performance of switched capacitor integrator |
| CN113872605A (en) * | 2021-09-30 | 2021-12-31 | 江苏润石科技有限公司 | Method and circuit for reducing power consumption of Sigma-Delta integrator |
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| CN106712730A (en) * | 2016-11-30 | 2017-05-24 | 上海集成电路研发中心有限公司 | Programmable gain amplifier capable of adjusting signals |
| CN107332563A (en) * | 2017-05-31 | 2017-11-07 | 苏州真感微电子科技有限公司 | Reduce the circuit of switching capacity input current and the method for sampling of switching capacity |
| CN109547021A (en) * | 2018-10-09 | 2019-03-29 | 西安电子科技大学 | A kind of single ended signal turns the variable gain amplifier of differential output signal |
| CN110336565A (en) * | 2019-06-20 | 2019-10-15 | 深圳市德赛微电子技术有限公司 | A kind of adjustable low imbalance Sigma-delta modulator of input range |
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| CN106712730A (en) * | 2016-11-30 | 2017-05-24 | 上海集成电路研发中心有限公司 | Programmable gain amplifier capable of adjusting signals |
| CN107332563A (en) * | 2017-05-31 | 2017-11-07 | 苏州真感微电子科技有限公司 | Reduce the circuit of switching capacity input current and the method for sampling of switching capacity |
| CN109547021A (en) * | 2018-10-09 | 2019-03-29 | 西安电子科技大学 | A kind of single ended signal turns the variable gain amplifier of differential output signal |
| CN110336565A (en) * | 2019-06-20 | 2019-10-15 | 深圳市德赛微电子技术有限公司 | A kind of adjustable low imbalance Sigma-delta modulator of input range |
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