JP2015186111A - Analog/digital conversion apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an analog/digital conversion apparatus which reduces variation in a held voltage and improves conversion accuracy of conversion from an analog signal to a digital signal.SOLUTION: An analog/digital conversion apparatus 1 includes: an analog/digital conversion unit 10 including a plurality of capacitors corresponding to respective bits of a digital signal Sto charge a capacitor 11 by an inputted reference voltage Vand output a comparison voltage Vcorresponding to each bit; a hold capacitor 21 for holing voltage based on an analog signal S; a comparison unit 20 including a switch 222 for controlling the voltage held by the hold capacitor 21 by on/off operation to compare the comparison voltage Voutputted from the analog/digital conversion unit 10 with voltage based on the analog signal Sand output a comparison result S; and a filter circuit 13 connected to the capacitor 11 to reduce a high frequency component of the reference voltage Vinputted to the capacitor 11.

Description

  The present invention relates to an analog-digital conversion apparatus.

  Conventionally, various proposals have been made for analog-to-digital conversion devices in order to increase the speed and power consumption of the analog-to-digital conversion device. For example, an analog switch for holding an analog input voltage in a hold capacitor, a digital-analog converter that outputs a comparison voltage based on an input digital signal, and a comparator that compares the held voltage with the comparison voltage There has been proposed a successive approximation type analog-to-digital converter provided with an initialization circuit that initializes charges stored in a capacitor immediately before sampling an input analog signal (see, for example, Patent Document 1).

JP 2005-20721 A

  However, according to the conventional analog-to-digital converter, when the digital-to-analog converter outputs the comparison voltage, the charge may leak from the hold capacitor to the analog switch. Therefore, there has been a problem that the conversion accuracy of the digital signal output from the analog-to-digital conversion device is lowered due to a change in the voltage held by the hold capacitor.

  Therefore, an object of the present invention is to provide an analog-to-digital conversion device that can reduce fluctuations in the held voltage and improve the conversion accuracy for converting an analog signal into a digital signal.

  One aspect of the present invention is a successive approximation type analog-to-digital converter that converts an analog signal input from the outside into a digital signal and outputs the digital signal, and has a plurality of capacitors corresponding to each bit of the digital signal. A voltage output unit that charges the capacitor with the reference voltage and outputs a comparison voltage corresponding to each bit; a hold capacitor that holds a voltage based on the analog signal; and the hold capacitor that holds the voltage by an on / off operation A switch for controlling the voltage, and comparing the comparison voltage output from the voltage output unit with a voltage based on the analog signal and outputting a comparison result; and a capacitor connected to the capacitor, An analog-to-digital converter comprising: a filter circuit that reduces a high-frequency component of the input reference voltage To provide.

  ADVANTAGE OF THE INVENTION According to this invention, the fluctuation | variation of the held voltage can be reduced and the conversion precision which converts an analog signal into a digital signal can be improved.

FIG. 1 is a diagram showing an example of a circuit of an analog-digital conversion device having a 10-bit configuration according to an embodiment of the present invention. 2A and 2B are diagrams illustrating waveforms of the reference voltage and the output voltage, where FIG. 2A is a waveform of the reference voltage output from the control unit, FIG. 2B is a waveform of the reference voltage that has passed through the filter circuit, and FIG. ) Is the waveform of the output voltage output from the analog-to-digital converter according to the embodiment of the present invention, and (d) is output from the analog-to-digital converter 10 according to the comparative example having no filter circuit. The output voltage waveform is shown. FIG. 3 is a timing chart showing the operation of the analog-digital conversion apparatus.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In addition, in each figure, about the component which has the substantially same function, the same code | symbol is attached | subjected and the duplicate description is abbreviate | omitted.

[Embodiment]
FIG. 1 is a diagram showing an example of a circuit of an analog-digital conversion device having a 10-bit configuration according to an embodiment of the present invention. In FIG. 1, 512C, 2C, and 1C indicate that a capacitor array is composed of 512, 2, and 1 capacitors with a capacitance ratio of 512, 2, and 1, respectively.

The analog - digital converter 1 receives the analog signal S _a from an external device (not shown) or the like, the analog signal S _a inputted successive approximation analog outputs into digital signals S _d - digital converter is there. An external device (not shown) is a detection device or sensor such as a microphone or a thermometer that converts a physical quantity into an analog signal and outputs the analog signal.

The analog-digital conversion device 1 is charged with the reference voltage V _ref and outputs a comparison voltage V _cmp corresponding to each bit of the digital signal S _d , and outputs a plurality of output voltages V _out based on the analog signal S _a . The analog-to-digital conversion unit 10 having the capacitor 11, the comparison unit 20 that compares the comparison voltage V _cmp output from the analog-to-digital conversion unit 10 with the output voltage V _out , the reference voltage V _ref , and the analog- And a control unit 30 that controls the digital conversion unit 10, the comparison unit 20, and the like. The analog-digital conversion unit 10 is an example of a voltage output unit.

(Analog-to-digital converter)
For example, when the resolution of the analog-to-digital conversion unit 10 is 10 bits, the analog-to-digital conversion unit 10 starts from bit [9], which is the most significant bit, and includes a capacitor (not shown) from the most significant bit. 256, 128, 64, 32, 16, 8, 4, 2, 1, so that the capacity ratio is 512C, 256C, 128C, 64C, 32C, 16C, 8C, 4C, 2C, 1C, a total of 1024 A plurality of capacitors 11 are formed.

Analog - to Digital converter 10, furthermore, (in this embodiment, 10 including those not shown) multiple provided corresponding to the bit [9] ~ [0] of the digital signal S _d of A switch 12 and a filter circuit 13 for reducing a high frequency component of the control signal _Sctr are provided. Further, each capacitor 11 is connected to each capacitor 11 and the ground GND based on the switching signal _Sch3 output from the control unit 30, and is connected to a reset switch 41 for discharging the charge charged in each capacitor 11. ing.

As the switch 12 and the reset switch 41, a semiconductor switch formed of a MOSFET (metal oxide film insulated gate field effect transistor) or the like is used. Switch 12 has a contact point 12a to be connected to the capacitor 11 corresponding to each bit, and a contact 12b for inputting the reference voltage _{V ref} from the control unit 30, and a contact point 12c that inputs the analog signal _{S a.} The switch 12 switches the connection between the contact 12a and the contact 12b and the connection between the contact 12a and the contact 12c based on the switching signal _Sch2 transmitted by the control unit 30.

FIG. 2 is a diagram illustrating waveforms of the reference voltage V _ref and the output voltage V _out , (a) is a waveform of the reference voltage V _ref output from the control unit 30, and (b) is passed through the filter circuit. The waveform of the reference voltage V _ref ′, (c) is the waveform of the output voltage V _out output from the analog-digital conversion unit 10, and (d) is the analog-digital conversion according to the comparative example that does not have a filter circuit. The waveform of output voltage _Vout 'output from the part is shown.

  The filter circuit 13 includes a resistor R inserted between the contact 12b of the switch 12 corresponding to bit [9] which is the most significant bit and the control unit 30, and a capacitor inserted between the resistor R and the ground GND. 131.

The filter circuit 13 receives a reference voltage V _ref having a steep rectangular waveform as shown in FIG. 2A from the control unit 30, and the input reference voltage V _ref rises as shown in FIG. 2B. The reference voltage V _{ref ′} with the falling edge delayed is output to the capacitor 11 corresponding to bit [9]. As shown in FIG. 2C, the capacitor 11 outputs an output voltage _{Vout of,} for example, 2.5 V with a reduced slew rate. In this way, an analog - digital conversion unit 10 outputs the output voltage V _out with a reduced overshoot component contained in the output voltage V _Out' shown in FIG. 2 (d), the high-frequency components such as undershoot components.

(Comparison part)
Comparing unit 20, an analog - digital converter 10 is based on the potential difference between the hold capacitor 21 for holding a voltage based on the output voltage _{V out} to be output in response to the analog signal _{S a,} the output voltage _{V out} and the reference voltage _{V cmp} comparison A chopper comparator 22 that outputs the result S _cmp to the control unit 30.

The hold capacitor 21 has an input terminal 21 a connected to the analog-digital conversion unit 10 and an output terminal 21 b connected to the chopper comparator 22. As will be described later, the threshold voltage V _{th of the} inverter 221 is output from the output voltage V _{out. Is} charged by a voltage (V _out −V _th ) obtained by subtracting, and this voltage (V _out −V _th ) is maintained. The hold capacitor 21 generates a voltage V _h greater than the threshold voltage V _th when the comparison voltage V _cmp is greater than V _{out due} to the potential difference between the held voltage (V _out −V _th ) and the comparison voltage V _cmp. When the comparison voltage V _cmp is smaller than V _out , a voltage V _h smaller than the threshold voltage V _th is output. For the hold capacitor 21, for example, a capacitor such as a film capacitor, an electrolytic capacitor, or a ceramic capacitor is used.

On the output terminal 21b side of the hold capacitor 21, a reset switch 42 for connecting the contact between the output terminal 21b and the analog-digital conversion unit 10 and the ground GND is provided. On the input terminal 21 a side of the hold capacitor 21, a reset switch 43 that connects a contact between the input terminal 21 a and the analog-digital conversion unit 10 and the ground GND is provided. The reset switches 42 and 43 connect the hold capacitor 21 and the ground GND based on the switching signal _Sch3 , and discharge the charge charged by the hold capacitor 21 to the ground GND. As the reset switches 42 and 43, semiconductor switches are used in the same manner as the switch 12 and the like.

The chopper comparator 22 is formed of an inverter 221 that outputs a comparison result based on a potential difference between the comparison voltage V _cmp and the output voltage V _out and a semiconductor switch, and a switch 222 that controls a voltage held by the hold capacitor 21 by an on / off operation. And have. The inverter 221 is an example of an inverter circuit.

The inverter 221, the threshold voltage _{V th} and the predetermined inverter 221 receives the voltage _{V h} connected to the output terminal 21b of the hold capacitor 21, when the voltage _{V h} greater than the threshold voltage _{V th} Outputs the comparison result S _cmp of 0 (Lo) to the control unit 30 and outputs the comparison result S _cmp of 1 (Hi) to the control unit 30 when the voltage V _h is smaller than the threshold voltage V _th. . As the inverter 221, a semiconductor element that inverts and outputs the level of an input signal or a circuit using the semiconductor element is used.

As the switch 222, a semiconductor switch such as a MOSFET is used similarly to the switch or the like. This semiconductor switch conducts between the source and the drain based on the voltage applied to the gate electrode. The switch 222 is turned on and off based on the switching signal _Sch1 from the control unit 30. In the on state, the switch 222 initializes the voltage (V _out −V _th ) that is held by discharging the hold capacitor 21, and in the off state. Then, the hold capacitor 21 is charged to hold the voltage (V _out −V _th ).

(Control part)
The control unit 30 is configured by a chip such as an LSI or an IC, for example, and is based on a clock signal CLK and a reset signal RST input from a CPU (not shown), a comparison result S _cmp input from the comparison unit 20, and the like, an analog-digital conversion unit 10. The comparator 20 and the reset switches 41, 42, 43 are controlled. As will be described later, the control unit 30 quantizes the voltage value of the output voltage V _out based on the comparison result S _cmp of each bit of the digital signal from the comparison unit 20, and illustrates the quantized voltage value as the digital signal S _d. Output to CPU etc.

Although not shown, the control unit 30 has ten signal lines 31 respectively connected to the switches 12 corresponding to the bits [9] to [0], and the comparison result input from the comparison unit 20 For example, a reference voltage V _{ref of} 5 V is output as a control signal S _ctr to the signal line 31 according to S _cmp .

(Operation of analog-digital converter)
Next, the operation of the analog-digital conversion apparatus 1 will be described with reference to FIG. FIG. 3 is a timing chart showing the operation of the analog-digital conversion apparatus 1. In the following description, the hexadecimal notation for the control signal S _ctr means which switch 12 of the ten signal lines 31 is output to the signal line 31 corresponding to the reference voltage V _ref. For example, when the reference voltage V _ref is output only to bit [9], it is expressed as 200 (hexadecimal number).

The control unit 30 executes the following processing in synchronization with the clock signal CLK of 2 MHz, for example. When receiving a reset signal RST from a CPU or the like (not shown) (point A), the control unit 30 outputs a switching signal _Sch3 to the reset switches 41, 42, 43, and turns off after the reset switches 41, 42, 43 are turned on. (B point). As a result, the control unit 30 performs the initialization process of the analog-digital conversion unit 10 and the hold capacitor 21 by discharging the charges charged by the capacitors 11 and the hold capacitor 21 of the analog-digital conversion unit 10 to the ground GND. .

When the initialization process is completed, the control unit 30 turns on the switching signal _Sch2 to connect the contact 12a and the contact 12c of each switch 12 of the analog-digital conversion unit 10, and receives the analog received from an external device (not shown) or the like. the signal _{S a} analog - input to the capacitors 11 of the digital conversion unit 10 (C point). Analog - each capacitor 11 of the digital conversion unit 10 is charged by the analog signal S _a inputted, outputs the output voltage V _out based on the electric charges charged in the holding capacitor 21.

The control unit 30 outputs the switching signal _Sch1 to the switch 222 of the comparison unit 20, and turns it off after turning on the switch 222 (point D). Thereby, the hold capacitor 21 holds a voltage (V _out −V _th ) based on the output voltage V _out when the switch 222 is turned off. That is, the hold capacitor 21 is charged with a voltage (V _out −V _th ) obtained by subtracting the threshold voltage V _th of the inverter 221 from the output voltage V _out .

When the hold capacitor 21 holds the voltage (V _out −V _th ), the control unit 30 turns off the switching signal _Sch2 (point E), and contacts 12a and 12b of each switch 12 of the analog-digital conversion unit 10 Connect.

When the switching signal _Sch2 is turned off, the control unit 30 outputs the control signal _Sctr (200 (hexadecimal number)) to the analog-digital conversion unit 10, and the capacitor 11 corresponding to bit [9] is connected to the filter circuit 13. The capacitor 11 outputs the comparison voltage V _cmp corresponding to bit [9] by charging with the passed reference voltage V _{ref ′} . The capacitor 11 corresponding to bit [9] outputs to the hold capacitor 21 a comparison voltage V _cmp of, for example, 2.5 V that is about half of the reference voltage V _ref .

Hold capacitor 21 outputs a voltage _{V h} to the inverter 221 based on the potential difference between the comparison voltage _{V cmp} and the output voltage _{V out.} That is, the hold capacitor 21, when the output voltage _{V out} is larger than the comparison voltage _{V cmp,} outputs a high voltage _{V h} than the threshold voltage _{V th} to the inverter 221, the output voltage _{V out} is smaller than the comparison voltage _{V cmp} In this case, a voltage V _h smaller than the threshold voltage V _th is output to the inverter 221.

Inverter 221 is larger than the voltage _{V h} threshold voltage _{V th} input from the hold capacitor 21 0 (Lo), if the voltage _{V h} inputted from the hold capacitor 21 is smaller than the threshold voltage _{V th} 1 (Hi) The comparison result S _cmp is output to the control unit 30.

The control unit 30 outputs a control signal S _ctr to the hold capacitor 21 based on the comparison result S _cmp output from the inverter 221. That is, when the comparison result S _cmp of 0 (L) is output from the inverter 221 (when the output voltage V _out is larger than the comparison voltage V _cmp ), the control unit 30 sets bit [9] and bit [8]. The reference voltage V _ref (control signal S _ctr : 300 (hexadecimal number)) is output to the corresponding signal line 31 to charge the capacitor 11 corresponding to bit [9] and bit [8]. The analog-to-digital converter 10 adds a voltage of 1.25V corresponding to bit [8] to a voltage corresponding to bit [9], for example, and outputs a voltage of 3.75V to the hold capacitor 21 as a comparison voltage _Vcmp. .

On the other hand, when the comparison result S _cmp of 1 (Hi) is output from the inverter 221 (when the output voltage V _out is smaller than the comparison voltage V _cmp ), the control unit 30 _applies the signal line 31 corresponding to bit [9]. The output reference voltage V _ref is stopped, and the reference voltage V _ref (control signal S _ctr : 100 (hexadecimal number)) is output to the signal line 31 corresponding to bit [8] (point F). At this time, the analog-digital conversion unit 10 outputs a comparison voltage V _{cmp of,} for example, 1.25 V to the hold capacitor 21 from the capacitor 11 corresponding to bit [8]. Inverter 221, based on the voltage inputted from the hold capacitor 21, and outputs the comparison result _{S cmp} of the comparison voltage _{V cmp} and the output voltage _{V out} to the controller 30.

The control unit 30 also compares the output voltage V _out with the comparison voltage V _cmp while changing the control signal S _ctr based on the comparison result S _cmp from the inverter 221 for bit [7] to bit [0]. The voltage value of the output voltage _Vout is specified and quantized. In FIG. 3, a voltage value (for example, about 0.981 V) corresponding to a control signal (0C9 (hexadecimal number)) in which bit [7], bit [6], bit [3], and bit [3] are 1 is represented. It is specified and quantized as a voltage value of the output voltage _Vout .

Control unit 30 holds the digital value the voltage value obtained by quantizing the specified output voltage V _out, and outputs the held digital values to the CPU or the like (not shown) as a digital signal S _d.

Analog - digital converter 1, by repeating the above operation, it converts the analog signal S _a which is input to the digital signal S _d.

(Effect of embodiment)
According to the present embodiment, the following effects can be obtained.
(1) In the configuration without the filter circuit 13, overshoot and undershoot as shown in FIG. 2D occur in the output voltage _Vout , and the charge corresponding to the overshoot and undershoot portions is transferred to the switch 222. Regardless of whether or not is off, the voltage (V _out −V _th ) held by the hold capacitor 21 due to leakage from the source and drain of the switch 222 may fluctuate. That is, when the voltages of the overshoot component and the undershoot component are large, the source and drain are conducted, and a part of the charge charged by the hold capacitor 21 flows as a leakage current.

In the present embodiment, by providing the filter circuit 13 in the signal line 31 corresponding to the most significant bit (bit [9]), it is possible to suppress the overshoot component and the undershoot component from the output voltage _Vout. It is possible to reduce fluctuations in the voltage (V _out −V _th ) held by the.

(2) The charge charged by the hold capacitor 21 leaks from the switch 222, and the voltage (V _out −V _th ) held by the hold capacitor 21 is, for example, 2 which is half of 4.88 mV corresponding to the least significant bit bit [0]. When .44 mV is changed, the comparison unit 20 compares 0 (L) with respect to bit [0] in order to compare the output voltage V _out and the comparison voltage V _cmp based on the changed voltage (V _out −V _th ). The comparison result S _{cmp in} which 1 (H) is inverted is output. In this case, the control unit 30 outputs the digital signal S _d in which bit [0] is inverted based on the comparison result S _cmp .

In this embodiment, consists can be suppressed variations in the voltage hold capacitor 21 is held (V _{out -V th),} it can be output by converting accurately analog signal S _a into a digital signal S _d.

(3) The conversion accuracy of the analog-digital conversion device 1 can be improved with a simple configuration provided with the filter circuit 13.

[Modification]
The embodiments of the present invention are not limited to the above-described embodiments, and various modifications and implementations are possible without departing from the scope of the present invention. For example, the filter circuit 13 may be provided corresponding to a plurality of bits of the analog-digital conversion unit 10. The filter circuit 13 may be provided outside the analog-digital conversion unit 10.

Further, the reference voltage V _ref may be output to the analog-digital conversion unit 10 from a power supply unit or the like provided separately from the control unit 30. Further, the control unit may generate the clock signal CLK and the reset signal RST.

  Further, the timing chart of the above embodiment can add, delete, replace, replace, etc. the timing and operation without departing from the scope of the present invention.

DESCRIPTION OF SYMBOLS 1 ... Digital conversion apparatus, 10 ... Analog-digital conversion part, 11 ... Capacitor, 12 ... Switch, 12a ... Contact, 12b, 12c ... Contact, 13 ... Filter circuit, 20 ... Comparison part, 21 ... Hold capacitor, 21a ... Input Terminal 21b ... Output terminal 22 ... Chopper comparator 30 ... Control unit 31 ... Signal line 41, 42, 43 ... Reset switch 131 ... Capacitor 221 Inverter 222 ... Switch CLK ... Clock signal GND ... Ground, R ... resistor, RST ... reset signal, S _a ... analog signal, S _ch1 , S _ch2 , S _ch3 ... switching signal, S _cmp ... comparison result, S _ctr ... control signal, S _d ... digital signal, V _cmp ... Comparison voltage, V _out , V _{out ′} … output voltage, V _ref , V _{ref ′} … reference voltage

Claims (3)

In a successive approximation type analog-to-digital converter that converts an analog signal input from the outside into a digital signal and outputs it,
A voltage output unit having a plurality of capacitors corresponding to each bit of the digital signal, charging the capacitor with an input reference voltage and outputting a comparison voltage corresponding to each bit;
A hold capacitor for holding a voltage based on the analog signal; and a switch for controlling a voltage held by the hold capacitor by an on / off operation, based on the comparison voltage output by the voltage output unit and the analog signal. A comparison unit that compares the voltage and outputs a comparison result;
A filter circuit connected to the capacitor for reducing a high frequency component of the reference voltage input by the capacitor;
An analog-to-digital conversion device. The filter circuit is connected to the capacitor corresponding to the most significant bit of the digital signal;
The analog-digital conversion device according to claim 1. The analog-digital conversion apparatus according to claim 1, wherein the comparison unit further includes an inverter circuit that outputs a comparison result based on a potential difference between the comparison voltage and a voltage based on the analog signal.

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