CN107359875B - Method for improving SAR-ADC circuit performance - Google Patents
Method for improving SAR-ADC circuit performance Download PDFInfo
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- CN107359875B CN107359875B CN201710468092.XA CN201710468092A CN107359875B CN 107359875 B CN107359875 B CN 107359875B CN 201710468092 A CN201710468092 A CN 201710468092A CN 107359875 B CN107359875 B CN 107359875B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M1/08—Continuously compensating for, or preventing, undesired influence of physical parameters of noise
- H03M1/0845—Continuously compensating for, or preventing, undesired influence of physical parameters of noise of power supply variations, e.g. ripple
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
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Abstract
The invention provides a method for improving the performance of an SAR-ADC circuit. The prior art has a plurality of defects. The method divides the charging time of the negative electrode of the capacitor into an initial stage and a later stage, wherein the initial stage uses the low-precision reference power supply for charging, and the later stage uses the high-precision reference power supply for charging. Specifically, three control switches are adopted in an ADC capacitance driving circuit to respectively control the grounding of a capacitor, the connection with a high-precision reference power supply and the connection with a low-precision reference power supply. Two control switches of the control power supply are connected with the capacitor driving control signal through a time sequence control circuit. When the control signal is low level, the negative pole of the capacitor is connected with the low-precision reference power supply, and when the potential of the negative pole of the capacitor is close to or reaches the potential of the low-precision reference power supply, the negative pole of the capacitor is connected with the high-precision reference power supply through the time sequence control circuit. The invention adopts the alternative use of the high-precision reference power supply and the low-precision reference power supply, reduces the requirement on a stable circuit, reduces the cost of a chip and simultaneously improves the circuit performance.
Description
Technical Field
The invention belongs to a circuit, relates to an ADC (analog-to-digital conversion) circuit, and particularly relates to a method for improving the performance of an SAR (successive approximation register) -ADC circuit.
Background
The ADC circuit converts a continuously varying analog signal into a discrete digital signal. Real-world analog signals, such as temperature, pressure, sound or images, need to be converted into digital form that is easier to store, process and transmit. ADCs can perform this function and are widely used in a variety of different electronic products.
The SAR-ADC circuit comprises an ADC capacitance driving circuit, the conventional ADC capacitance driving circuit is shown in FIG. 1 and comprises two control switches S1 and S2, one contact of one control switch S1 is grounded, one contact of the other control switch is connected with a high-precision reference power supply Vref, the other contact of the two control switches S1 and S2 is connected with one end of a capacitor C, the control ends of the two control switches S1 and S2 are connected with a capacitor driving control signal KEY, and the other end of the capacitor C is an output end. When the capacitor driving control signal is at a high level, S1 is closed, S2 is opened, and the negative electrode of the capacitor is grounded; when the capacitor driving control signal is at low level, S2 is closed, S1 is opened, and the negative electrode of the capacitor is connected with a high-precision reference power supply Vref. S1 is typically an NMOS transistor, and S2 is typically a PMOS transistor.
Because the ADC compares the analog signal with the high-precision reference power Vref, the comparison accuracy of the ADC is influenced by the fluctuation of the Vref, and the fluctuation range of the Vref is required to be within
And n is the number of bits of the ADC. High bit ADCs require less ripple on the reference supply. In the prior art, a large-capacity capacitor is added on Vref, and a power supply buffer required by a high-gain bandwidth product index is used, but the technical means not only increase the cost and the technical difficulty, but also do not change the strength of a root cause generating fluctuation on the Vref, and only reduce the influence of the fluctuation on the Vref.
Disclosure of Invention
The present invention is directed to the above-mentioned current situation of the prior art, and particularly to a method for reducing the fluctuation of Vref and improving the performance of SAR-ADC circuit.
The method comprises the steps of dividing the charging time of the negative electrode of the capacitor into an initial stage and a later stage, charging the negative electrode of the capacitor by using a low-precision reference power supply in the initial stage, and charging the negative electrode of the capacitor by using a high-precision reference power supply in the later stage; specifically, three control switches are adopted in an ADC capacitance driving circuit, one contact of each control switch is connected with one end of a capacitor, the other contact of one control switch is grounded, the other contact of the other control switch is connected with a high-precision reference power supply Vref1, and the other contact of the other control switch is connected with a low-precision reference power supply Vref 2; the control end of the control switch which is grounded is connected with the capacitance driving control signal KEY, and the control ends of the control switch which is connected with the high-precision reference power supply Vref1 and the control switch which is connected with the low-precision reference power supply Vref2 are connected with the capacitance driving control signal KEY through a time sequence control circuit.
When the capacitor driving control signal KEY is at a high level, the grounded control switch is closed, the control switch connected with the high-precision reference power supply and the control switch connected with the low-precision reference power supply are disconnected, and the negative electrode of the capacitor is grounded;
when the capacitor driving control signal KEY is at a low level, the grounded control switch is disconnected, the control switch connected with the low-precision reference power supply is firstly closed, the control switch connected with the high-precision reference power supply is kept disconnected, the negative electrode of the capacitor is connected with the low-precision reference power supply, the potential of the negative electrode of the capacitor rises, and when the potential of the low-precision reference power supply is close to or reached, the time sequence control circuit controls the control switch connected with the low-precision reference power supply to be disconnected, the control switch connected with the high-precision reference power supply to be closed, and the negative electrode of the capacitor is connected with the high-precision reference power.
The high-precision reference power supply Vref1 adopts the high-precision reference power supply standard in the existing ADC capacitance driving circuit, and the low-precision reference power supply is a common power supply without fluctuation range requirement. Further, the low-precision reference power Vref2 employs the circuit operating power VDD in the circuit.
The sequential control circuit realizes that a control switch connected with a low-precision reference power supply Vref2 and a control switch connected with a high-precision reference power supply Vref1 are sequentially switched on and switched off in two ways:
in the first mode, the capacitor charging potential is compared with the threshold potential through a comparator and then realized through a logic circuit; and the second mode is realized by a delay circuit and a logic circuit.
The specific implementation circuit of the first mode: the high-precision reference power supply Vref1, the low-precision reference power supply Vref2, three control switches, two resistors, a capacitor, two-input OR gates, a NOT gate and a comparator are included.
One contact of a first control switch S1, one contact of a second control switch S2, one contact of a third control switch S3 and one end of a non-inverting input terminal of a comparator CMP are connected with one end of a capacitor C, one end of a first resistor R1 and one end of a second resistor R2 are connected with an inverting input terminal of the comparator CMP, the other contact of the first control switch S1 and the other end of a first resistor R1 are grounded, the other contact of the second control switch S2 is connected with a high-precision reference power supply Vref1, the other contact of the third control switch S3 and the other end of the second resistor R2 are connected with a low-precision reference power supply Vref2, and the other end of the capacitor C is an output terminal; an output end of the comparator CMP and one input end of the first two-input OR gate OR1 are connected with an input end of the not gate N, an output end of the not gate N is connected with one input end of the second two-input OR gate OR2, the other input end of the first two-input OR gate OR1, the other input end of the second two-input OR gate OR2 and a control end of the first control switch S1 are connected with the capacitor driving control signal KEY, a control end of the second control switch S2 is connected with an output end of the second two-input OR gate OR2, and a control end of the third control switch S3 is connected with an output end of the first two-input OR gate OR 1.
The specific implementation circuit of the second mode: the high-precision reference power supply Vref1, the low-precision reference power supply Vref2, three control switches, a capacitor, a two-input OR gate, a NOT gate and a delay chain, wherein the delay chain is formed by connecting n NOT gates in series, and n is an even number.
One contact of the first control switch S1, one contact of the second control switch S2 and one contact of the third control switch S3 are connected with one end of a capacitor C, the other contact of the first control switch S1 is grounded, the other contact of the second control switch S2 is connected with a high-precision reference power supply Vref1, the other contact of the third control switch S3 is connected with a low-precision reference power supply Vref2, and the other end of the capacitor C is an output end; the control end of the second control switch S2 is connected to the output end of the delay chain, the control end of the third control switch S3 is connected to the output ends of the two input OR gates, one input end of the two input OR gates is connected to the output end of the not gate N, the input end of the not gate N is connected to the output end of the delay chain, and the other input end of the two input OR gates, the input end of the delay chain and the control end of the first control switch S1 are connected to the capacitor driving control signal KEY.
When the capacitor driving control signal KEY transits from a high level to a low level, the level of the cathode of the capacitor is charged from the level of ground to the level of Vref. In the initial stage of charging the capacitor, the voltage of the negative electrode of the capacitor has a large variation range, and the negative electrode of the capacitor absorbs a large amount of charges from the reference power supply, so that the level of the reference power supply fluctuates greatly, and the precision of the reference power supply is reduced. In the later stage of charging of the negative electrode of the capacitor, the voltage change amplitude of the negative electrode of the capacitor is small, the negative electrode of the capacitor absorbs a small amount of charges from the reference power supply, only the level fluctuation with small amplitude of the reference power supply can be caused, and the precision of the reference power supply cannot be reduced. And the ADC only carries out level comparison after the capacitor is stably charged, namely the ADC does not carry out level comparison in the initial charging stage of the capacitor. Therefore, the low-precision reference power supply can be used in the initial stage of charging the capacitor, and the high-precision reference power supply can be used in the later stage of charging the capacitor. Thereby reducing the charge flow in the high-precision reference power supply, and therefore reducing the voltage fluctuation of the high-precision reference power supply, thereby reducing the capacity of a voltage stabilizing capacitor of the high-precision power supply or reducing the index requirement on the gain bandwidth product of the power supply buffer.
The invention divides the charging time of the negative electrode of the capacitor into an initial stage and a later stage. A low-precision reference power supply is used at the initial stage and a high-precision reference power supply is used at the later stage. The charge of the capacitor is mainly obtained from the low-precision reference power supply, and the charge obtained from the high-precision reference power supply is greatly reduced, so that the fluctuation on the high-precision reference power supply is reduced, and the processing requirement on the high-precision reference power supply is reduced. The low-precision reference supply only provides charge and is not used to determine the final level, so the operating supply VDD of the unprocessed ADC can naturally be taken as the low-precision reference supply.
The invention adopts the alternative use of the high-precision reference power supply and the low-precision reference power supply, reduces the amplitude of the fluctuation source on the Vref, fundamentally reduces the noise intensity of the Vref, reduces the requirement on a stable circuit of the Vref, and reduces the requirement on a large-capacity capacitor or a power supply buffer, thereby reducing the cost of a chip and improving the performance of the ADC.
Drawings
FIG. 1 is a circuit diagram of an ADC capacitor driving circuit in a conventional SAR-ADC circuit;
FIG. 2 is a waveform diagram of controlling timing and capacitor charging in the method of the present invention
FIG. 3 is a circuit diagram of one implementation of the present invention;
fig. 4 is a circuit diagram of another implementation of the present invention.
Detailed Description
A method for improving the performance of an SAR-ADC circuit divides the charging time of a capacitor cathode of an ADC capacitor driving circuit in the SAR-ADC circuit into an initial stage and a later stage, a low-precision reference power supply is used for charging the cathode of the capacitor in the initial stage, and a high-precision reference power supply is used for charging the cathode of the capacitor in the later stage; specifically, three control switches S1, S2 and S3 are adopted in an ADC capacitance driving circuit, one contact of each of the three control switches is connected with one end of a capacitor, the other contact of one control switch S1 is grounded, the other contact of the other control switch S2 is connected with a high-precision reference power supply Vref1, and the other contact of the other control switch S3 is connected with a low-precision reference power supply Vref 2; the control terminal of the control switch S1 is connected to the capacitor driving control signal KEY, and the control switches S2 and S3 are connected to the timing control circuit.
When the capacitor driving control signal KEY is at a high level, the grounded control switch S1 is closed, and the control switch S2 connected to the high-precision reference power supply and the control switch S3 connected to the low-precision reference power supply are opened, so that the negative electrode of the capacitor is grounded.
When the capacitor driving control signal KEY is at a low level, the control switch S1 connected to the ground is turned off, the control switch S3 connected to the low-precision reference power supply is turned on first, the control switch S2 connected to the high-precision reference power supply is kept turned off, the negative electrode of the capacitor is connected to the low-precision reference power supply, the potential of the negative electrode of the capacitor is raised, and when the potential of the low-precision reference power supply Vref2 is approached or reached, the control switch S3 connected to the low-precision reference power supply is turned off by the timing control circuit, the control switch S2 connected to the high-precision reference power supply is turned on, and the negative electrode of the capacitor is connected to the high-precision reference.
The control timing and capacitor charging waveforms are shown in fig. 2.
The realization circuit adopts three control switches, one contact of each control switch is respectively connected with one end of a capacitor, the other contact of one control switch is grounded, the other contact of the other control switch is connected with a high-precision reference power supply Vref1, and the other contact of the other control switch is connected with a low-precision reference power supply Vref 2; the control end of the grounded control switch is connected with a capacitance driving control signal KEY, and the control ends of the control switch connected with a high-precision reference power supply Vref1 and the control switch connected with a low-precision reference power supply Vref2 are connected with the capacitance driving control signal KEY through a time sequence control circuit;
the sequential control circuit realizes that a control switch connected with a low-precision reference power supply Vref2 and a control switch connected with a high-precision reference power supply Vref1 are sequentially switched on and off, and the sequential control circuit is realized by two modes: the capacitor charging potential is compared with the threshold potential through a comparator and then realized through a logic circuit; or by delay circuits and logic circuits.
One implementation circuit is shown in fig. 3: the high-precision reference power supply Vref1, the low-precision reference power supply Vref2 (in this embodiment, the Vref2 may be the circuit operating power supply VDD in the circuit), three control switches, two resistors, a capacitor, two-input OR gates, a NOT gate, and a comparator are included.
One contact of a first control switch S1, one contact of a second control switch S2, one contact of a third control switch S3 and one end of a non-inverting input terminal of a comparator CMP are connected with one end of a capacitor C, one end of a first resistor R1 and one end of a second resistor R2 are connected with an inverting input terminal of the comparator CMP, the other contact of the first control switch S1 and the other end of a first resistor R1 are grounded, the other contact of the second control switch S2 is connected with a high-precision reference power supply Vref1, the other contact of the third control switch S3 and the other end of the second resistor R2 are connected with a low-precision reference power supply Vref2, and the other end of the capacitor C is an output terminal; an output end of the comparator CMP and one input end of the first two-input OR gate OR1 are connected with an input end of the not gate N, an output end of the not gate N is connected with one input end of the second two-input OR gate OR2, the other input end of the first two-input OR gate OR1, the other input end of the second two-input OR gate OR2 and a control end of the first control switch S1 are connected with the capacitor driving control signal KEY, a control end of the second control switch S2 is connected with an output end of the second two-input OR gate OR2, and a control end of the third control switch S3 is connected with an output end of the first two-input OR gate OR 1.
Another implementation circuit is shown in fig. 4: the high-precision reference power supply Vref1, the low-precision reference power supply Vref2 (in this embodiment, the Vref2 may adopt a circuit operating power supply VDD in a circuit), three control switches, a capacitor, a two-input OR gate, a NOT gate, and a delay chain, where the delay chain is formed by connecting n NOT gates in series, and n is an even number.
One contact of the first control switch S1, one contact of the second control switch S2 and one contact of the third control switch S3 are connected with one end of a capacitor C, the other contact of the first control switch S1 is grounded, the other contact of the second control switch S2 is connected with a high-precision reference power supply Vref1, the other contact of the third control switch S3 is connected with a low-precision reference power supply Vref2, and the other end of the capacitor C is an output end; the control end of the second control switch S2 is connected to the output end of the delay chain, the control end of the third control switch S3 is connected to the output ends of the two input OR gates, one input end of the two input OR gates is connected to the output end of the not gate N, the input end of the not gate N is connected to the output end of the delay chain, and the other input end of the two input OR gates, the input end of the delay chain and the control end of the first control switch S1 are connected to the capacitor driving control signal KEY.
It is to be understood that the above examples are illustrative of the present invention and are not to be construed as limiting the invention, and any invention which does not depart from the spirit and scope of the invention is deemed to be within the scope and spirit of the invention.
Claims (4)
1. A method for improving the performance of a SAR-ADC circuit is characterized in that: the method divides the charging time of the negative electrode of the capacitor of an ADC capacitor driving circuit in the SAR-ADC circuit into an initial stage and a later stage, a low-precision reference power supply is used for charging the negative electrode of the capacitor in the initial stage, and a high-precision reference power supply is used for charging the negative electrode of the capacitor in the later stage; specifically, three control switches are adopted in an ADC capacitance driving circuit, one contact of each control switch is connected with one end of a capacitor, and the other contact of each control switch is grounded, connected with a high-precision reference power supply (Vref1) and connected with a low-precision reference power supply (Vref 2); the control end of the grounded control switch is connected with a capacitance driving control signal (KEY), the control ends of the control switch connected with a high-precision reference power supply (Vref1) and the control end of the control switch connected with a low-precision reference power supply (Vref2) are connected with the capacitance driving control signal (KEY) through a time sequence control circuit;
when the capacitor driving control signal (KEY) is in a high level, the grounded control switch is closed, the control switch connected with the high-precision reference power supply (Vref1) and the control switch connected with the low-precision reference power supply (Vref2) are disconnected, and the negative electrode of the capacitor is grounded;
when the capacitor driving control signal (KEY) is in a low level, the grounded control switch is disconnected, the control switch connected with the low-precision reference power supply (Vref2) is firstly closed, the control switch connected with the high-precision reference power supply (Vref1) is kept disconnected, the negative electrode of the capacitor is connected with the low-precision reference power supply, the potential of the negative electrode of the capacitor is increased, when the potential of the low-precision reference power supply (Vref2) is approached or reached, the timing control circuit controls the control switch connected with the low-precision reference power supply (Vref2) to be disconnected, the control switch connected with the high-precision reference power supply (Vref1) to be closed, and the negative electrode of the capacitor is connected with the high-precision reference power supply; the specific realization circuit is as follows:
the circuit comprises a high-precision reference power supply (Vref1), a low-precision reference power supply (Vref2), three control switches, two resistors, a capacitor, two-input OR gates, a NOT gate and a comparator;
one contact of a first control switch (S1), one contact of a second control switch (S2), one contact of a third control switch (S3) and one end of a non-inverting input terminal of a Comparator (CMP) are connected with one end of a capacitor (C), one end of a first resistor (R1) and one end of a second resistor (R2) are connected with an inverting input terminal of the Comparator (CMP), the other contact of the first control switch (S1) and the other end of the first resistor (R1) are grounded, the other contact of the second control switch (S2) is connected with a high-precision reference power supply (Vref1), the other contact of the third control switch (S3) and the other end of the second resistor (R2) are connected with a low-precision reference power supply (Vref2), and the other end of the capacitor (C) is an output terminal; an output end of the Comparator (CMP) and one input end of a first two-input OR gate (OR1) are connected with an input end of an NOT gate (N), an output end of the NOT gate (N) is connected with one input end of a second two-input OR gate (OR2), the other input end of the first two-input OR gate (OR1), the other input end of the second two-input OR gate (OR2) and a control end of a first control switch (S1) are connected with a capacitance driving control signal (KEY), a control end of a second control switch (S2) is connected with an output end of a second two-input OR gate (OR2), and a control end of a third control switch (S3) is connected with an output end of the first two-input OR gate (OR 1);
the high-precision reference power supply (Vref1) adopts the high-precision reference power supply standard in the existing ADC capacitance driving circuit, and the low-precision reference power supply (Vref2) is a common power supply without fluctuation range requirement.
2. The method of claim 1, wherein the method comprises: the low-precision reference power supply (Vref2) adopts a circuit working power supply (VDD) in a circuit.
3. A method for improving the performance of a SAR-ADC circuit is characterized in that: the method divides the charging time of the negative electrode of the capacitor of an ADC capacitor driving circuit in the SAR-ADC circuit into an initial stage and a later stage, a low-precision reference power supply is used for charging the negative electrode of the capacitor in the initial stage, and a high-precision reference power supply is used for charging the negative electrode of the capacitor in the later stage; specifically, three control switches are adopted in an ADC capacitance driving circuit, one contact of each control switch is connected with one end of a capacitor, and the other contact of each control switch is grounded, connected with a high-precision reference power supply (Vref1) and connected with a low-precision reference power supply (Vref 2); the control end of the grounded control switch is connected with a capacitance driving control signal (KEY), the control ends of the control switch connected with a high-precision reference power supply (Vref1) and the control end of the control switch connected with a low-precision reference power supply (Vref2) are connected with the capacitance driving control signal (KEY) through a time sequence control circuit;
when the capacitor driving control signal (KEY) is in a high level, the grounded control switch is closed, the control switch connected with the high-precision reference power supply (Vref1) and the control switch connected with the low-precision reference power supply (Vref2) are disconnected, and the negative electrode of the capacitor is grounded;
when the capacitor driving control signal (KEY) is in a low level, the grounded control switch is disconnected, the control switch connected with the low-precision reference power supply (Vref2) is firstly closed, the control switch connected with the high-precision reference power supply (Vref1) is kept disconnected, the negative electrode of the capacitor is connected with the low-precision reference power supply, the potential of the negative electrode of the capacitor is increased, when the potential of the low-precision reference power supply (Vref2) is approached or reached, the timing control circuit controls the control switch connected with the low-precision reference power supply (Vref2) to be disconnected, the control switch connected with the high-precision reference power supply (Vref1) to be closed, and the negative electrode of the capacitor is connected with the high-precision reference power supply; the specific realization circuit is as follows:
the circuit comprises a high-precision reference power supply (Vref1), a low-precision reference power supply (Vref2), three control switches, a capacitor, a two-input OR gate, a NOT gate and a delay chain, wherein the delay chain is formed by connecting n NOT gates in series, and n is an even number;
one contact of the first control switch (S1), one contact of the second control switch (S2) and one contact of the third control switch (S3) are connected with one end of a capacitor (C), the other contact of the first control switch (S1) is grounded, the other contact of the second control switch (S2) is connected with a high-precision reference power supply (Vref1), the other contact of the third control switch (S3) is connected with a low-precision reference power supply (Vref2), and the other end of the capacitor (C) is an output end; the control end of the second control switch (S2) is connected with the output end of the delay chain, the control end of the third control switch (S3) is connected with the output ends of the two input OR gates (OR), one input end of the two input OR gates (OR) is connected with the output end of the NOT gate (N), the input end of the NOT gate (N) is connected with the output end of the delay chain, and the other input end of the two input OR gates (OR), the input end of the delay chain and the control end of the first control switch (S1) are connected with the capacitor driving control signal (KEY).
4. A method of improving the performance of a SAR-ADC circuit according to claim 3, wherein: the low-precision reference power supply (Vref2) adopts a circuit working power supply (VDD) in a circuit.
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