JP2014090308A - Successive approximation register a/d converter and multi-bit delta-sigma modulator using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a multi-bit delta-sigma modulator that can use a successive approximation register A/D converter in implementing quantizers for the purpose of suppressing an increase in quantizers.SOLUTION: Capacitors 806_1-806_n with respective output side ends connected together include a first capacitor having a capacitance set at a reference capacitance, second to (n-1)th capacitors set to capacitances which are the reference capacitance weighted stepwise with inverse numbers of powers of two, and an nth capacitor having a combined capacitance set at a predetermined capacitance value. Switch groups 505_1-505_(n-1) are connected to the other ends of the capacitors, respectively, and configured to switch connections of the capacitors between an input section for an analog signal and nodes of predetermined potentials. A comparator 504 compares an input potential based on potentials held in the capacitors with first and second reference potentials.

Description

  The present invention relates to a successive approximation A / D converter and a multi-bit delta sigma modulator using the same, and more particularly, to reduce the signal amplitude input to a quantizer to reduce power consumption, and to perform quantization The present invention relates to a multi-bit delta sigma modulator that enables a quantizer to be realized by a successive approximation A / D converter in order to suppress an increase in the number of converters.

Conventionally, there is a delta-sigma (ΔΣ) modulator as a typical method for realizing narrow-band analog-digital conversion. Regarding the quantizer in the delta sigma modulator, the delta sigma modulator that performs quantization with a plurality of bits in order to improve the dynamic range of the converted digital signal is particularly referred to as a multi-bit delta sigma modulator.
FIG. 3 is a circuit configuration diagram of a conventional multi-bit delta sigma modulator, and is a circuit configuration diagram described in FIG. As shown in FIG. 3, a conventional multi-bit delta sigma modulator 200 includes an analog integrator 101, a multi-bit quantizer 102, a DA converter 103, and an adder in order to obtain a digital signal Y ′ from the analog signal X ′. 104. The resolution of the multi-bit quantizer 102 is not binary but multi-level, and as shown in FIG. 4 (see FIG. 16 of Patent Document 2), each threshold value (that is, comparison voltage) Vth′1 to Vth′1. Vth′7 was set so that the interval between them became equal potential (that is, potential difference at equal intervals).

  In such a delta-sigma modulator 200, in order to improve the conversion accuracy as an AD converter (ie, obtain a high dynamic range) without changing the configuration, the conversion speed (ie, oversampling ratio) is increased. Alternatively, it is necessary to increase the number of conversion bits of the multi-bit quantizer 102 by increasing the number of quantizers and comparators.

On the other hand, for example, Non-Patent Document 1 proposes to use a successive approximation type A / D converter (SAR-ADC) instead of using a general flash ADC as a quantizer. The increase in the number of quantizers is suppressed.
FIG. 5 is a circuit configuration diagram of a general successive approximation A / D converter. This successive approximation A / D converter A / D converts an analog input signal Ain into a digital output signal Vout of n bits (n is a natural number of 3 or more).

As shown in FIG. 5, the successive approximation A / D converter is provided with a single capacitor 506_1 having a capacitance value set to a predetermined reference capacitance C. In addition, each of the above-described reference capacitances C is set to have respective capacitances C / 2,..., C / 2 ⁽ⁿ⁻²⁾ weighted stepwise by the reciprocal of a power of 2 ^(n−). 2) Capacitors 506_2,..., 506_ (n−1) are provided. Further, the capacitance is set to one C / 2 ^{(n−2) obtained} by weighting the reference capacitance C by ½ ⁽ⁿ⁻²⁾ as in the above-described capacitor 506_ (n−1). A capacitor 506_n is provided.

The capacitor array 506 is configured by the plurality of capacitors 506_1 to 506_n described above, and the holding voltage in the corresponding capacitor among the capacitors in the capacitor array 506 is selectively applied sequentially, and an analog input signal is described as described below. A successive comparison between Ain and the reference voltage is performed.
In addition, the right ends of the capacitors 506_1 to 506_ (n−1) and the capacitor 506_n are connected to a storage node (SN in FIG. 5) that can store charges.

The left ends of the capacitors 506_1 to 506_ (n-1) are connected to the terminals O of the switch groups 505_1, 505_2, ..., 505_ (n-1), respectively.
The switch groups 505_1, 505_2,..., 505_ (n−1) have a common terminal O for each switch group and separate terminals C, P, and N corresponding thereto. When the switch 503d_k (k is a natural number of 1 to (n-1)) is turned on by the switching signal CTRL, the terminal C and the terminal O are short-circuited.

Further, when the switch 503e_k is turned on, the terminal P and the terminal O are short-circuited, and when the switch 503f_k is turned on, the terminal N and the terminal O are short-circuited. Two or more of the switches 503d_k, 503e_k, and 503f_k are not turned on at the same time.
The terminals C of the switch groups 505_1 to 505_ (n−1) and the left end of the capacitor 506_n are connected to the switch 503b and the switch 503c. When the switch 503c is turned on, the terminals C of the switches 505_1 to 505_ (n−1) and the left end of the capacitor 506_n are connected to the input node (Ain in FIG. 5).

When the switch 503b is turned on, the terminals C of the switches 505_1 to 505_ (n−1) and the left end of the capacitor 506_n are connected to a potential point of an analog common voltage VC which is a reference potential described later.
The terminals P of the switch groups 505_1 to 505_ (n−1) are connected to the potential point of the full-scale reference potential VRP on the positive side with respect to the analog common voltage VC, and the terminals of the switch groups 505_1 to 505_ (n−1). N is connected to the potential point of the full-scale reference potential VRN on the negative electrode side with respect to VC.

  The right ends of the capacitors 506_1 to 506_ (n−1) and the right end of the capacitor 506_n are connected to the switch 503a and the inverting input terminal of the comparator 504 via the storage node SN. When the switch 503a is turned on, the storage node SN is connected to the potential point of VC. The output DO of the comparator 504 is input to the control unit 501 and the output register 502.

The control unit 501 includes a combinational circuit (logic circuit) or the like, and outputs a control signal CTRL that controls switching of the switch groups 505_1 to 505_ (n−1) and the switches 503a to 503c.
That is, the control unit 501 generates the control signal CTRL based on the determination signal DO and sequentially switches the switch groups 505_1 to 505_ (n−1), and the internal voltage corresponding to the analog input voltage Ain (the potential of the storage node SN). A control signal CTRL for obtaining the above is generated and output.

In addition, the trigger clock CLK generated by the control unit 501 is supplied to the comparator 504. The comparator 504 determines the magnitude of the potential of the storage node SN and the input node voltage VC (reference potential) in synchronization with the trigger clock CLK. If SN <VC, it outputs DO = H (1), and SN> In the case of VC, DO = L (0) is output.
Further, the trigger clock CLK from the control unit 501 is supplied to the output register 502, and the determination signal DO is supplied from the comparator 504 to the output register 502.

The output register 502 holds DN = 1 (N: N is a natural number of “1 to n”) when the determination signal DO = 1 from the comparator 504 is synchronized with the trigger clock CLK, and the determination signal DO = When 0, DN = 0 is held.
Then, after receiving the determination signals D1 to Dn which are n output values from the comparator 504, the output register 502 outputs the held D1 to Dn as the digital output signal Vout as described above. It is configured.

Next, the circuit operation when the number of bits is 6 (n = 6) will be described.
FIGS. 6A to 6D show transitions of a voltage to be determined regarding a certain input in a general successive approximation A / D converter, a value of a trigger clock, a determination output signal of a comparator, and a determination result of upper 6 bits. It is a figure which illustrates the output based on.
FIG. 6A is a diagram illustrating an example in which the voltage of the inversion polarity of the potential of the storage node SN, which is the determination target voltage, is plotted, with the vertical axis representing voltage and the horizontal axis representing time. FIG. 6B is a diagram illustrating an example of a change in the trigger clock CLK output from the control unit 501, and illustrates determination timings at regular intervals of the comparator 504. Further, FIG. 6C is a diagram illustrating an example of the value of the determination output signal DO of the comparator 504.

In FIGS. 6A to 6D, VRP−VC = VC−VRN = VR is taken as an example. Under this condition, an input voltage Ain of Ain = (10.8 / 16) × VR is sampled. It represents the case.
As an initial state, when the voltage of the capacitors 506_1 to 506_n follows the analog input voltage Ain, the switch 503a and the switch 503c are turned on and the switch 503b is turned off. In addition, the switch group switches 503d_1 to 503d_ (n−1) are turned on, and the switches 503e_1 to 503e_ (n−1) and the switches 503f_1 to 503f_ (n−1) are turned off.

  At the time when the analog input voltage Ain is sampled (discretized) by the capacitors 506_1 to 506_n, the switch 503a is turned off by the control signal CTRL from the control unit 501, and the switch 503c is turned off immediately. Thereafter, when the switch 503b is turned on, the polarity of the sampled Ain is inverted and appears as -Ain [V] in the storage node SN. Here, the switch 503b and the switch 503c have a non-overlapping relationship that does not turn on at the same time.

  When the charge redistribution is sufficiently performed after the switching of the switches 503a, 503b, and 503c as described above and the parasitic capacitance is ignored for convenience, at the time when the potential of the storage node SN sufficiently converges to −Ain, The first determination rising clock in FIG. 6B (the timing of “1st Judge” in FIG. 6A) is input to the comparator 504. In response to the input of the first determination rising clock, the comparator 504 compares the potential of the storage node SN with the reference voltage VC.

This comparison in the comparator 504 is directly a comparison between the potential of the storage node SN and the reference voltage VC. However, as can be easily understood from the above-described phenomenon, the potential of the storage node SN is substantially uniquely determined. It can be regarded as a comparison between -Ain (and hence Ain) and the reference voltage VC.
Therefore, the comparator 504 outputs DO = 1 when -Ain <VC, that is, Ain> VC, and the first determination is DO = 0 when -Ain> VC, ie, Ain <VC. Output as a result.

  When the first determination result in the above is DO = 1, the control unit 501 controls the switch group 505_1, the switch 503d_1 is turned off, and the switch 503e_1 is turned on. As a result, the above-described positive-side full-scale reference potential VRP is applied to the terminal O, that is, to the left end of the capacitor 506_1. Therefore, the potential of the storage node SN becomes − (Ain−VR / 2) [V] due to charge redistribution.

  On the other hand, when the first determination result is DO = 0, the control unit 501 controls the switch group 505_1, the switch 503d_1 is turned off, and the switch 503f_1 is turned on. As a result, the negative-side full-scale reference potential VRN is applied to the terminal O, that is, the left end of the capacitor 506_1. Therefore, the potential of the storage node SN becomes − (Ain + VR / 2) [V] due to charge redistribution.

Similarly, the potential of the storage node SN is compared with the reference voltage VC at the time when the yth determination rising clock, which is the yth determination rising clock (y is a natural number of 2 to (n-1)), is input. The switch group 505 — y is controlled according to the determination result.
Then, the potential of the storage node SN is compared with the reference voltage VC at the time when the (n−1) th determination rising clock is input, and the switch group 505_ (n−1) is controlled according to the result. At the time when the n determination rising clock is input, the potential of the storage node SN and the reference voltage VC are compared.
The gradual comparison operation in the comparator 504 as described above completes the 1-n bit successive comparison operation, and the output register 502 outputs n-bit output data Vout.

  FIG. 6A shows the transition of the determination target signal when the potential VSN = − (10.8 / 16) × VR of the storage node SN is sampled as an example. Since − (10.8 / 16) × VR <VC in the first determination rising clock, as shown in FIG. 6C, D1 = 1 is output. As a result, the switch group 505_1 is controlled, and the potential of the storage node SN becomes VSN = − (10.8 / 16) × VR + VR / 2 = − (2.8 / 16) × VR.

  Next, in the second determination rising clock in FIG. 6B (the timing of “2nd Judge” in FIG. 6A), − (2.8 / 16) × VR <VC is satisfied, so that FIG. ), D2 = 1 is output. As a result, the switch group 505_2 is controlled, and the potential of the storage node SN becomes VSN = − (2.8 / 16) × VR + VR / 4 = (1.2 / 16) × VR.

Thereafter, the same processing is repeated up to (n−1) times, and when Dn is determined by the nth determination rising clock and the n-bit successive approximation operation is completed, the output register 502 is based on the stored D1 to Dn. Output n-bit output data Vout.
FIG. 6D is a diagram illustrating an example of Vout output based on the determination results D1 to D6 of the upper 6 bits. As shown in FIG. 6C, the determination result of the upper 6 bits is D1 = “1”, D2 = “1”, D3 = “0”, D4 = “1”, D5 = “0”, D6 = “1”. As shown in FIG. 6D, the output register 502 arranges these in order from the upper bits and outputs the upper 6 bits “110101” of Vout. Here, the output register 502 is configured by, for example, a shift register.

Further, it is well known that the power consumption of the operational amplifier is proportional to the output amplitude. In the ΔΣ AD converter, the signal amplitude input to the quantizer (the signal amplitude of the input node of the quantizer 102 in FIG. 3) is intentionally set. Often, a smaller approach is taken.
FIG. 7 is a circuit configuration diagram of the successive approximation A / D converter when the input signal amplitude is compressed to 1 / k (k> 1) in another general successive approximation A / D converter. In FIG. 7, VRP ′ = VC + (1 / k) · (VRP−VC) and VRP ′ = VC− (1 / k) · (VC−VRN).

FIG. 7 has the same circuit configuration as FIG. 5, wherein the reference potential VRP is the reference potential VRP ′ and the reference potential VRN is the reference potential VRN ′. Since the reference potential is compressed 1 / k times that of FIG. 5, A / D conversion in which the input signal amplitude is 1 / k times can be realized with the same circuit configuration.
Next, the circuit operation when the number of bits is 6 (n = 6) and k = 2 will be described with reference to FIGS.

8A to 8D show the transition of the voltage to be determined for a certain input in the successive approximation A / D converter of FIG. 7, the value of the trigger clock, the determination output signal of the comparator, and the determination result of the upper 6 bits. It is a figure which illustrates the output based on.
Here, FIG. 8A is a diagram showing an example of plotting the voltage of the inverted polarity of the potential of the storage node SN, which is the determination target voltage, where the vertical axis represents voltage and the horizontal axis represents time. The vertical axis in FIGS. 8A to 8C is expressed by being compressed 1/2 times the vertical axis in FIGS. 6A to 6C.

FIG. 8B is a diagram illustrating an example of a change in the trigger clock CLK output from the control unit 501, and illustrates determination timings at regular intervals of the comparator 504. Further, FIG. 8C is a diagram illustrating an example of the value of the determination output signal DO of the comparator 504.
Further, in FIGS. 8A to 8D, VRP-VC = VC-VRN = VR is taken as an example, and Ain = (10.8 / 16) × (1/2) VR is input under this condition. The case where the voltage Ain is sampled is shown. Ain in FIGS. 8A to 8D is compressed to ½ of Ain in FIGS. 6A to 6D. Since the reference potential is compressed 1 / k times that of FIGS. 6A to 6D, the input signal amplitude is 1 / k times that of FIGS. 6A to 6D. / D conversion can be realized.

  As described above, in the above-described delta-sigma modulator 200, the signal amplitude input to the quantizer 102 is reduced to reduce power consumption, and the quantizer 102 is set to SAR to suppress increase of the quantizer. When implemented with -ADC, the reference voltage of the SAR-ADC also lowered the signal amplitude input to the quantizer 102 in the same manner as the reduction rate.

Japanese Patent Laid-Open No. 11-027145 JP 2012-023540 A

“A Low-Power 1.92 MHz CT ΔΣ Modulator With 5-bit Successful Quantizer” (IEEE 2009 Custom Integrated Circuits (CICC))

  However, in the delta-sigma modulator 200 described above, the signal amplitude input to the quantizer 102 is decreased to reduce power consumption, and the quantizer 102 is set to SAR-ADC to suppress the increase of the quantizer. In this case, the reference voltage of the SAR-ADC also needs to reduce the signal amplitude input to the quantizer 102 in the same manner as the reduction rate. Therefore, a circuit that generates a new voltage value with a reduction rate is provided. There is a problem that it is necessary in excess and an increase in circuit area and power consumption cannot be avoided.

  The present invention has been made in view of such a problem, and an object of the present invention is to provide a quantizer for reducing power consumption in a delta-sigma modulator without increasing circuit area and power consumption. Provided is a multi-bit delta sigma modulator that can realize a quantizer by a successive approximation A / D converter in order to reduce the amplitude of a signal input to the signal and suppress an increase in the quantizer There is.

  The present invention has been made to achieve such an object, and the invention according to claim 1 is directed to a predetermined condition when the first and second reference potentials and the reference potential are set to predetermined values. A charge comparison type successive approximation A / D converter (102) for converting an analog input signal represented by a potential satisfying the above into an n-bit (n is a natural number of 3 or more) digital output signal, A first capacitor (806_1) having one end connected in common and an electrostatic capacity set to a reference capacity, and a second capacity set to a weight obtained by weighting the reference capacity stepwise by the reciprocal of a power of 2 Thru (n-1) capacitors (806_2,..., 806_n-1) and n capacitors (806_1,..., 806_1,. .., 806_ , And the first to (n−1) th capacitors (806_1,..., 806_n−1), respectively, and the first to (n−1) th capacitors and the analog signal The first to (n-1) th switch groups (505_1,... 505_ (n-1)) for switching the connection between the input portion and the node of a predetermined potential, and the holding potential of the n capacitors. The comparator (504) that compares the input potential based on the first reference potential and the second reference potential and outputs a determination signal according to the comparison result, and the comparison determination operation is sequentially executed in order from a predetermined bit. As described above, a control unit (501) for controlling the switching operation of the first to (n-1) th switch groups and the comparison determination operation of the comparator is provided.

  According to a second aspect of the present invention, in the first aspect of the present invention, when the first and second reference potentials are set to VRP and VRN, and the reference potential is set to VC, VRP -VC = VC-VRN = A digital output of an analog input signal (1 / k) × VR × Ain (k is a natural number of 2 or more) represented by a potential VR satisfying VR (n is a natural number of 3 or more). It converts into a signal, It is characterized by the above-mentioned.

Further, the invention according to claim 3 is the invention according to claim 1 or 2, wherein the capacitors (806_1,..., 806_n) are connected in common at one end on the output side, and have a capacitance. A first capacitor set to a reference capacity (1 / k) × C, and a capacity (1 / k) obtained by weighting the reference capacity (1 / k) × C stepwise with an inverse of a power of 2 × C / 2,... (1 / k) × C / 2 ^(2nd to (n−1) th capacitors set to ⁽ⁿ⁻²⁾ and a combined capacitance of 2C (1 / K) × C / 2 ⁽ⁿ⁻²⁾ + ((k−1) / k) × 2C and the n-th capacitor set to a capacitance.

  The invention according to claim 4 is a multi-bit delta-sigma modulator (200) for obtaining a digital signal from an analog signal, the analog integrator (101) to which the analog signal is input, and the analog integrator The successive approximation A / D converter (102) of claim 1 as a multi-bit quantizer connected to (101) and outputting the digital signal, and the successive approximation A / D converter (102). And a DA converter (103) connected to the DA converter (103), and an adder (104) connected to the analog integrator (101). To do.

  According to the present invention, without increasing the circuit area and power consumption, in the delta-sigma modulator, the signal amplitude input to the quantizer is reduced in order to reduce power consumption, and the number of quantizers is increased. A multi-bit delta-sigma modulator that can realize the quantizer by SAR-ADC to suppress it can be realized.

It is a circuit block diagram for demonstrating Example 1 of the successive approximation A / D converter based on this invention. (A) to (d) show the transition of the voltage to be determined for a certain input in the successive approximation A / D converter according to the present invention, the value of the trigger clock, the determination output signal of the comparator, and the determination result of the upper 6 bits. It is a figure which illustrates the output based on. It is a circuit block diagram of the conventional multibit delta-sigma modulator. It is a figure which shows the example of a setting of the some threshold value of the conventional multibit quantizer. It is a circuit block diagram of a general successive approximation type A / D converter. (A) to (d) are based on a transition of a voltage to be determined for a certain input in a general successive approximation A / D converter, a value of a trigger clock, a determination output signal of a comparator, and a determination result of upper 6 bits. It is a figure which illustrates an output. FIG. 5 is a circuit configuration diagram of a successive approximation A / D converter when an input signal amplitude is compressed to 1 / k (k> 1) in another general successive approximation A / D converter. (A) to (d) are based on the transition of the voltage to be determined for a certain input in the successive approximation A / D converter of FIG. 7, the value of the trigger clock, the determination output signal of the comparator, and the determination result of the upper 6 bits. It is a figure which illustrates an output.

  Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit configuration diagram for explaining a first embodiment of a successive approximation A / D converter according to the present invention. In addition, the same code | symbol is attached | subjected to the component which has the same function as FIG.5 and FIG.7.
The successive approximation A / D converter 102 according to the first embodiment outputs an analog input signal represented by a potential that satisfies a predetermined condition when the first and second reference potentials and the reference potential are set to predetermined values. It is a charge comparison type successive approximation A / D converter that converts a digital output signal of bits (n is a natural number of 3 or more).

  The n capacitors 806_1,..., 806_n are connected in common at one end on the output side, and the first capacitor 806_1 whose capacitance is set to the reference capacitance, and this reference capacitance is a power of two. The second to (n−1) th capacitors 806_2,..., 806_n−1 set to capacities that are weighted stepwise by the reciprocal of the value, and the nth nth set that the combined capacitance is set to a predetermined capacitance value And a capacitor 806_n.

Further, the first to (n−1) th switch groups 505_1,..., 505_ (n−1) include the first to (n−1) th capacitors 806_1,. The first to (n-1) th capacitors, the analog signal input unit, and the node of a predetermined potential are connected to each other.
The comparator 504 compares the input potential based on the holding potential of the n capacitors with the first and second reference potentials and outputs a determination signal corresponding to the comparison result.

In addition, the control unit 501 performs the switching operations of the first to (n−1) th switch groups 505_1,..., 505_ (n−1) and the switching determination operations so that the comparison determination operation is sequentially performed from a predetermined bit. The comparison judgment operation of the comparator 504 is controlled.
Further, in the successive approximation A / D converter according to the first embodiment, when the first and second reference potentials are set to VRP and VRN and the reference potential is set to VC, VRP−VC = VC− An analog input signal (1 / k) × VR × Ain (k is a natural number of 2 or more) represented by a potential VR that satisfies VRN = VR is converted into a digital output signal of n bits (n is a natural number of 3 or more). It is.

In addition, the capacitors (806_1,..., 806_n) are connected in common at one end on the output side, and each of the capacitances is set to a reference capacitance (1 / k) × C. Capacitance (1 / k) × C / 2,..., (1 / k) × C / 2 ⁽ⁿ⁻² ) in which the reference capacity (1 / k) × C is weighted stepwise by the reciprocal of the power of ^{2 ) To} (1 / k) × C / 2 ⁽ⁿ⁻²⁾ + ((k−1) / k) so that the combined capacitance is 2C. It consists of the nth capacitor set to the capacity | capacitance which is * 2C.

That is, as shown in FIG. 1, the successive approximation A / D converter 102 according to the first embodiment has one capacitance value set to a predetermined reference capacitance (1 / k) × C. A capacitor 806_1 is provided. Here, k is an integer of 2 or more.
In addition, each capacitance (1 / k) × C / 2,..., (1 / k) × C obtained by stepwise weighting the above-described reference capacitance (1 / k) × C by the reciprocal of the power of 2 / 2 ^(n-2) capacitors 806_2,..., 806_ (n-1), each set to have (n-2), are provided.

Further, (1 / k) × C / 2 ⁽ⁿ⁻²⁾ is set to (1 / k) × C / 2 ⁽ⁿ⁻²⁾ so that the total capacitance of the capacitors 806_1,..., 806_n is 2C. One capacitor 806 — n set as described above is provided.
The capacitor array 806 is configured by the plurality of capacitors 806_1 to 806_n described above, and the holding voltage in the corresponding capacitor among the capacitors in the capacitor array 806 is selectively applied in order, and an analog input signal is described as described below. A successive comparison between Ain and the reference voltage is performed.

Further, the right ends of the capacitors 806_1 to 806_ (n−1) and the capacitor 806_n are connected to a storage node (SN in FIG. 1) that can store charges.
The left ends of the capacitors 806_1 to 806_ (n-1) are connected to the terminals O of the switch groups 505_1, 505_2, ..., 505_ (n-1), respectively.
The switch groups 505_1, 505_2,..., 505_ (n−1) have a common terminal O for each switch group and separate terminals C, P, and N corresponding thereto. When the switch 503d_k (k is a natural number of 1 to (n-1)) is turned on by the switching signal CTRL, the terminal C and the terminal O are short-circuited.

Further, when the switch 503e_k is turned on, the terminal P and the terminal O are short-circuited, and when the switch 503f_k is turned on, the terminal N and the terminal O are short-circuited. Two or more of the switches 503d_k, 503e_k, and 503f_k are not turned on at the same time.
The terminals C of the switch groups 505_1 to 505_ (n−1) and the left end of the capacitor 506_n are connected to the switch 503b and the switch 503c. When the switch 503c is turned on, the terminal C of the switches 505_1 to 505_ (n−1) and the left end of the capacitor 806_n are connected to the input node (Ain in FIG. 1).

When the switch 503b is turned on, the terminals C of the switches 505_1 to 505_ (n−1) and the left end of the capacitor 806_n are connected to a potential point of an analog common voltage VC which is a reference potential described later.
The terminals P of the switch groups 505_1 to 505_ (n−1) are connected to the potential point of the full-scale reference potential VRP on the positive side with respect to the analog common voltage VC, and the terminals of the switch groups 505_1 to 505_ (n−1). N is connected to the potential point of the full-scale reference potential VRN on the negative electrode side with respect to VC.

  The right ends of the capacitors 806_1 to 806_ (n−1) and the right end of the capacitor 806_n are connected to the switch 503a and the inverting input terminal of the comparator 504 via the storage node SN. When the switch 503a is turned on, the storage node SN is connected to the potential point of VC. The output DO of the comparator 504 is input to the control unit 501 and the output register 502.

The control unit 501 includes a combinational circuit (logic circuit) or the like, and outputs a control signal CTRL that controls switching of the switch groups 505_1 to 505_ (n−1) and the switches 503a to 503c.
That is, the control unit 501 generates the control signal CTRL based on the determination signal DO and sequentially switches the switch groups 505_1 to 505_ (n−1), and the internal voltage corresponding to the analog input voltage Ain (in this embodiment, storage A control signal CTRL that obtains the potential of the node SN is generated and output.

In addition, the trigger clock CLK generated by the control unit 501 is supplied to the comparator 504. The comparator 504 determines the magnitude of the potential of the storage node SN and the input node voltage VC (reference potential) in synchronization with the trigger clock CLK, and outputs DO = H (1) if SN <VC. If> VC, DO = L (0) is output.
Further, the trigger clock CLK from the control unit 501 is supplied to the output register 502, and the determination signal DO is supplied from the comparator 504 to the output register 502.

The output register 502 holds DN = 1 (N: N is a natural number of “1 to n”) when the determination signal DO = 1 from the comparator 504 is synchronized with the trigger clock CLK, and the determination signal DO = When 0, DN = 0 is held.
Then, after receiving the determination signals D1 to Dn which are n output values from the comparator 504, the output register 502 outputs the held D1 to Dn as the digital output signal Vout as described above. It is configured.

Next, the circuit operation when the number of bits is 6 (n = 6) will be described with reference to FIGS.
2 (a) to 2 (d) show the transition of the voltage to be determined for a certain input, the value of the trigger clock and the determination output signal of the comparator, and the determination of the upper 6 bits in the successive approximation A / D converter according to the present invention. It is a figure which illustrates the output based on a result.

  Here, FIG. 2A is a diagram illustrating an example in which the voltage of the polarity of the storage node SN that is the voltage to be determined is plotted, with the vertical axis representing voltage and the horizontal axis representing time. FIG. 2B is a diagram illustrating an example of a change in the trigger clock CLK output from the control unit 501, and represents determination timings at regular intervals of the comparator 504. Further, FIG. 2C is a diagram illustrating an example of the value of the determination output signal DO of the comparator 504.

Further, in FIGS. 2A to 2D, VRP-VC = VC-VRN = VR and k = 2 are taken as an example, and under this condition, Ain = (10.8 / 16) × 1/2 × The case where the input voltage Ain of VR is sampled is shown.
As an initial state, when the voltages of the capacitors 806_1 to 806_n follow the analog input voltage Ain, the switches 503a and 503c are turned on and the switch 503b is turned off. In addition, the switch group switches 503d_1 to 503d_ (n−1) are turned on, and the switches 503e_1 to 503e_ (n−1) and the switches 503f_1 to 503f_ (n−1) are turned off.

  At the time when the analog input voltage Ain is sampled (discretized) by the capacitors 806_1 to 806_n, the switch 503a is turned off by the control signal CTRL from the control unit 501, and the switch 503c is turned off immediately. Thereafter, when the switch 503b is turned on, the polarity of the sampled Ain is inverted and appears as -Ain [V] in the storage node SN. Here, the switch 503b and the switch 503c have a non-overlapping relationship that does not turn on at the same time.

  When the charge redistribution is sufficiently performed after the switching of the switches 503a, 503b, and 503c as described above and the parasitic capacitance is ignored for convenience, at the time when the potential of the storage node SN sufficiently converges to −Ain, FIG. The first determination rising clock in (b) (the timing of “1st Judge” in FIG. 2A) is input to the comparator 504. In response to the input of the first determination rising clock, the comparator 504 compares the potential of the storage node SN with the reference voltage VC.

This comparison in the comparator 504 is directly a comparison between the potential of the storage node SN and the reference voltage VC. However, as can be easily understood from the above-described phenomenon, the potential of the storage node SN is substantially uniquely determined. It can be regarded as a comparison between -Ain (and hence Ain) and the reference voltage VC.
Therefore, the comparator 504 outputs DO = 1 when -Ain <VC, that is, Ain> VC, and the first determination is DO = 0 when -Ain> VC, ie, Ain <VC. Output as a result.

  When the first determination result in the above is DO = 1, the control unit 501 controls the switch group 505_1, the switch 503d_1 is turned off, and the switch 503e_1 is turned on. As a result, the positive-side full-scale reference potential VRP described above is applied to the terminal O, that is, to the left end of the capacitor 806_1. Therefore, the potential of the storage node SN becomes − (Ain− (VR / 2) × (1/2)) [V] by charge redistribution.

  On the other hand, when the first determination result is DO = 0, the control unit 501 controls the switch group 505_1, the switch 503d_1 is turned off, and the switch 503f_1 is turned on. As a result, the negative-side full-scale reference potential VRN is applied to the terminal O, that is, the left end of the capacitor 506_1. Therefore, the potential of the storage node SN becomes − (Ain + (VR / 2) × (1/2)) [V] by charge redistribution.

Similarly, the potential of the storage node SN is compared with the reference voltage VC at the time when the yth determination rising clock, which is the yth determination rising clock (y is a natural number of 2 to (n-1)), is input. The switch group 505 — y is controlled according to the determination result.
Then, the potential of the storage node SN is compared with the reference voltage VC at the time when the (n−1) th determination rising clock is input, and the switch group 505_ (n−1) is controlled according to the result. At the time when the n determination rising clock is input, the potential of the storage node SN and the reference voltage VC are compared.

The gradual comparison operation in the comparator 504 as described above completes the 1-n bit successive comparison operation, and the output register 502 outputs n-bit output data Vout.
FIG. 2A shows the transition of the signal to be determined when the potential VSN of the storage node SN = − (10.8 / 16) × (1/2) × VR is sampled as an example. . Since − (10.8 / 16) × (1/2) × VR <VC in the first determination rising clock, as shown in FIG. 2C, D1 = 1 is output. As a result, the switch group 505_1 is controlled, and the potential of the storage node SN is VSN = − (10.8 / 16) × (1/2) × VR + (1/2) × (VR / 2) = − (2 .8 / 16) × (1/2) × VR.

  Next, in the second determination rising clock in FIG. 2B (the timing of “2nd Judge” in FIG. 2A), − (2.8 / 16) × (1/2) × VR <VC. Therefore, D2 = 1 is output as shown in FIG. As a result, the switch group 505_2 is controlled, and the potential of the storage node SN is VSN = − (2.8 / 16) × (1/2) × VR + (1/2) × VR / 4 = (1.2 / 16) × (1/2) × VR.

Thereafter, the same processing is repeated up to (n−1) times, and when Dn is determined by the nth determination rising clock and the n-bit successive approximation operation is completed, the output register 502 is based on the stored D1 to Dn. Output n-bit output data Vout.
FIG. 2D is a diagram illustrating an example of Vout output based on the determination results D1 to D6 of the upper 6 bits. As shown in FIG. 2C, the determination result of the upper 6 bits is D1 = “1”, D2 = “1”, D3 = “0”, D4 = “1”, D5 = “0”, D6 = “1”. As shown in FIG. 2D, the output register 502 arranges these in order from the upper bits, and outputs the upper 6 bits “110101” of Vout. Here, the output register 502 is configured by a shift register, for example.

  As described above, in the SAR-ADC in which the input signal amplitude is multiplied by 1 / k, the SAR-ADC that does not require the new reference voltages VRP ′ and VRN ′ can be provided by changing the weight of the capacitor array. . As a result, an additional circuit for generating new reference voltages VRP ′ and VRN ′ is not required, and a highly efficient successive approximation A / D converter can be realized.

  As in the first embodiment, a multi-bit delta sigma modulator can be realized by using a successive approximation A / D converter as a quantizer in order to suppress an increase in the number of quantizers. That is, the multi-bit delta sigma modulator 200 that obtains a digital signal from an analog signal is an analog integrator 101 to which the analog signal is input, and a multi-bit quantizer that is connected to the analog integrator 101 and outputs a digital signal. The successive approximation A / D converter 102 of the first embodiment described above, the DA converter 103 connected to the successive approximation A / D converter 102, and the analog converter connected to the DA converter 103. And an adder 104 connected to the device 101.

  As described above, according to the present invention, without increasing the circuit area and power consumption, in the delta-sigma modulator, the signal amplitude input to the quantizer is reduced in order to reduce power consumption. Therefore, it is possible to realize a multi-bit delta sigma modulator that can realize the quantizer by SAR-ADC in order to suppress the increase of the quantizer.

501 Control unit 502 Output register 503a, 503b, 503c Switch 503d_1, 503e_1, 503f_1, ..., 503d_n-1, 503e_n-1, 503f_n-1 Switch 504 Comparator (comparator)
505_1,..., 505_ (n-1) Switch group 806 Capacitor array 806_1,.

Claims (4)

When the first and second reference potentials and reference potentials are set to predetermined values, an analog input signal represented by a potential satisfying a predetermined condition is converted into a digital output signal of n bits (n is a natural number of 3 or more). A charge comparison type successive approximation A / D converter,
A first capacitor in which one end on the output side is connected in common and the capacitance is set to a reference capacitance, and a second capacitor is set to a capacitance that is weighted stepwise by the reciprocal of a power of 2 Thirty (n-1) capacitors and n capacitors, the combined capacitance of which is set to a predetermined capacitance value,
The first to (n−1) th capacitors are connected to the other ends of the capacitors, respectively, and the first to (n−1) th capacitors, the analog signal input section, and the node of a predetermined potential are switched. 1st to (n-1) th switch groups;
A comparator that compares an input potential based on a holding potential of the n capacitors with the first and second reference potentials and outputs a determination signal according to the comparison result;
A control unit that controls the switching operation of the first to (n-1) th switch groups and the comparison determination operation of the comparator so that the comparison determination operation is sequentially performed in order from a predetermined bit. A successive approximation A / D converter characterized by the above.   When the first and second reference potentials are set to VRP and VRN and the reference potential is set to VC, an analog input signal represented by a potential VR that satisfies VRP−VC = VC−VRN = VR ( 2. The successive approximation type A / 2 according to claim 1, wherein 1 / k) × VR × Ain (k is a natural number of 2 or more) is converted into a digital output signal of n bits (n is a natural number of 3 or more). D converter. The capacitor has a first capacitor in which one end of the output side is commonly connected, and a capacitance is set to a reference capacitance (1 / k) × C, and the reference capacitance (1 / k) × C , (1−k) × C / 2..., (1 / k) × C / 2 ⁽ⁿ⁻²⁾ , which are weighted stepwise by the reciprocal of the power of 2. The capacitor of (n-1) and the capacitance of (1 / k) * C / 2 ^(n-2) + ((k-1) / k) * 2C were set so that the combined capacity was 2C. The successive approximation A / D converter according to claim 1, wherein the successive approximation A / D converter is formed of an n-th capacitor.   A multi-bit delta-sigma modulator for obtaining a digital signal from an analog signal, the analog integrator receiving the analog signal, and a multi-bit quantizer connected to the analog integrator and outputting the digital signal The successive approximation A / D converter according to claim 1, a DA converter connected to the successive approximation A / D converter, and connected to the DA converter and connected to the analog integrator. And a multi-bit delta-sigma modulator.

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