CN113328748B - Analog-to-digital conversion circuit - Google Patents
Analog-to-digital conversion circuit Download PDFInfo
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- CN113328748B CN113328748B CN202110488536.2A CN202110488536A CN113328748B CN 113328748 B CN113328748 B CN 113328748B CN 202110488536 A CN202110488536 A CN 202110488536A CN 113328748 B CN113328748 B CN 113328748B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The application provides an analog-to-digital conversion circuit, and relates to the technical field of circuits. Comprising the following steps: the system comprises a pipeline analog-digital converter formed by N stages of analog-digital converters, N-1 detection circuits, N-1 calibration circuits and N-1 first calibration voltage generation circuits; if i is an integer smaller than N, the digital end of the ith analog-to-digital converter is electrically connected with the first detection input end of a detection circuit; the digital end of the (i+1) th stage analog-to-digital converter is electrically connected with the second detection input end of a detection circuit; a first detection output end of the detection circuit is electrically connected with a first calibration input end of a calibration circuit; the first calibration output end of a calibration circuit is electrically connected with the digital end of a first calibration voltage generation circuit; the analog end of the first calibration voltage generation circuit is electrically connected with the first input end of the comparator in the ith stage of analog-to-digital converter. The number of the calibration circuits is reduced, the calibration offset voltage is tracked in real time, and the processing speed of the analog-to-digital converter is improved.
Description
Technical Field
The application relates to the technical field of circuits, in particular to an analog-to-digital conversion circuit.
Background
The pipeline analog-to-digital converter is an analog-to-digital conversion structure, has the advantages of high speed and high precision, and is widely applied to 5G (5 th generation mobile networks, fifth generation mobile communication technology) and next generation high-speed and high-capacity communication systems. Because of the asymmetry of the manufacturing process, offset voltage can be introduced, and the problem of inaccurate conversion result can occur, the offset voltage reduction has important significance for the analog-digital converter of the equipment assembly line.
In the related art, a correction circuit is provided for each device in the pipeline analog-to-digital converter, for example, a correction circuit is provided for each analog-to-digital converter in the pipeline analog-to-digital converter, and calibration is achieved by shorting the input ports of the comparators in the analog-to-digital converters.
However, in the related art, a correction circuit needs to be provided for each device, so that more correction circuits are needed, extra time is needed for shorting, and the processing speed of the pipeline analog-digital converter is reduced.
Disclosure of Invention
The application aims to overcome the defects in the prior art, and provides an analog-to-digital conversion circuit so as to solve the problems that in the related art, a correction circuit is required to be arranged for each device, more correction circuits are required, extra time is required for short-circuiting, and the processing speed of a pipeline analog-to-digital converter is reduced.
In order to achieve the above purpose, the technical scheme adopted by the embodiment of the application is as follows:
in a first aspect, an embodiment of the present application provides an analog-to-digital conversion circuit, including: the system comprises a pipeline analog-digital converter formed by N stages of analog-digital converters, N-1 detection circuits, N-1 calibration circuits and N-1 first calibration voltage generation circuits; n is an integer greater than or equal to 2;
if i is an integer smaller than N, the digital end of the ith analog-to-digital converter is electrically connected with the first detection input end of a detection circuit to output the ith digital code; the digital end of the (i+1) -th level analog-to-digital converter is electrically connected with the second detection input end of the one detection circuit to output an (i+1) -th digital code, so that the one detection circuit outputs an (i) -th voltage symbol detection value based on the (i+1) -th digital code and the (i+1) -th digital code; the first detection output end of the detection circuit is electrically connected with the first calibration input end of a calibration circuit, so that the calibration circuit outputs an ith voltage calibration code based on the ith voltage symbol detection value;
the first calibration output end of the one calibration circuit is electrically connected with the digital end of the one first calibration voltage generation circuit, so that the one first calibration voltage generation circuit outputs an ith calibration voltage signal based on the ith voltage calibration code; the analog end of the first calibration voltage generating circuit is electrically connected with the first input end of the comparator in the ith analog-to-digital converter, so that the comparator in the ith analog-to-digital converter outputs an ith target digital code according to the ith calibration voltage signal and the corresponding input analog signal.
Optionally, the analog-to-digital conversion circuit further includes: a second calibration voltage generation circuit;
the second detection output end of the (N-1) -th detection circuit is electrically connected with the second calibration input end of the (N-1) -th calibration circuit, so that the (N-1) -th detection circuit outputs an (N) -th voltage detection value based on the (N) -th digital code output by the (N) -th analog-to-digital converter;
a second calibration output end of the N-1 th calibration circuit is electrically connected with a digital end of the second calibration voltage generation circuit, so that the N-1 th calibration circuit outputs an N-th voltage calibration code based on the N-th voltage detection value, and the second calibration voltage generation circuit outputs an N-th calibration voltage signal based on the N-th voltage calibration code;
the analog end of the second calibration voltage generating circuit is electrically connected with one input end of the comparator in the N-th stage analog-to-digital converter, so that the comparator in the N-th stage analog-to-digital converter generates and outputs an N-th target digital code based on the N-th calibration voltage signal and the corresponding input analog signal.
Optionally, the first calibration voltage generating circuit and the second calibration voltage generating circuit are calibration voltage generating circuits with the same structure, and the calibration voltage generating circuit includes: the first switch array, M first resistors, M-1 second resistors and a third resistor; wherein M is equal to the number of bits of the voltage calibration code;
the first ends of the M-1 second resistors which are sequentially connected in series are grounded through the third resistor, and the second ends of the M-1 second resistors which are sequentially connected in series are analog ends of the calibration voltage generating circuit;
the input end of the first switch array is a digital end of the calibration voltage generation circuit, and the power end of the first switch array is electrically connected with a preset reference voltage; the M output ends of the first switch array are respectively and electrically connected with one ends of M first resistors, and two ends of each second resistor in the M-1 second resistors are respectively and electrically connected with the other ends of the two first resistors.
Optionally, the resistance of the first resistor is twice the resistance of the second resistor.
Optionally, the analog-to-digital conversion circuit further includes: n-1 amplifiers;
the residual output end of the ith analog-to-digital converter is also electrically connected with the input end of an amplifier, and the output end of the amplifier is also electrically connected with the analog end of the (i+1) th analog-to-digital converter.
Optionally, each stage of the analog-to-digital converter includes: the second input end of the comparator is electrically connected with the analog end of each stage of analog-to-digital converter, and the output end of the comparator is the digital end of each stage of analog-to-digital converter;
the output end of the comparator is also electrically connected with the digital end of the digital-to-analog converter, and the analog end of the digital-to-analog converter is also electrically connected with the analog end of each stage of analog-to-digital converter and the residual output end of each stage of analog-to-digital converter.
Optionally, the digital-to-analog converter includes: a second switch array, a capacitor array; the input end of the second switch array is the digital end of the digital-to-analog converter;
the output ends of the second switch array are respectively and electrically connected with one end of each capacitor in the capacitor array, and the other end of each capacitor in the capacitor array is an analog end of the digital-to-analog converter.
Optionally, each calibration circuit further has a trigger terminal; each calibration circuit is specifically configured to output a voltage calibration code according to the received voltage detection value when the trigger signal received by the trigger terminal is valid.
Optionally, each calibration circuit further has a restart end, and each calibration circuit is further configured to reset the output voltage calibration code to a preset code value when detecting that a restart signal input by the restart end is valid; and outputting a voltage calibration code according to the received voltage detection value when the restarting signal is detected to be invalid and the triggering signal is detected to be valid.
Optionally, each calibration circuit further has an enable end, and each calibration circuit is specifically configured to output a voltage calibration code according to the received voltage detection value when the restart signal is invalid and the trigger signal is valid, and the enable signal input by the enable end is valid.
The beneficial effects of the application are as follows: an embodiment of the present application provides an analog-to-digital conversion circuit, including: the system comprises a pipeline analog-digital converter formed by N stages of analog-digital converters, N-1 detection circuits, N-1 calibration circuits and N-1 first calibration voltage generation circuits; n is an integer greater than or equal to 2; if i is an integer smaller than N, the digital end of the ith analog-to-digital converter is electrically connected with the first detection input end of a detection circuit to output the ith digital code; the digital end of the (i+1) -th level analog-to-digital converter is electrically connected with the second detection input end of a detection circuit to output the (i+1) -th digital code, so that the detection circuit outputs the (i) th voltage symbol detection value based on the (i+1) -th digital code and the (i+1) -th digital code; a first detection output end of the detection circuit is electrically connected with a first calibration input end of a calibration circuit, so that the calibration circuit outputs an ith voltage calibration code based on an ith voltage symbol detection value; a first calibration output terminal of a calibration circuit is electrically connected to a digital terminal of a first calibration voltage generation circuit, so that the first calibration voltage generation circuit outputs an ith calibration voltage signal based on an ith voltage calibration code; the analog end of a first calibration voltage generating circuit is electrically connected with the first input end of the comparator in the ith analog-to-digital converter so that the comparator in the ith analog-to-digital converter outputs an ith target digital code according to the ith calibration voltage signal and the corresponding input analog signal. Only N-1 detection circuits, N-1 calibration circuits and N-1 first calibration voltage generation circuits are needed, so that the calibration of the pipeline analog-digital converter consisting of the N-stage analog-digital converters can be realized, and the number of required offset calibration circuits is reduced. And the ith voltage symbol detection value is generated based on the ith digital code and the (i+1) th digital code, the ith voltage calibration code can be determined based on the ith voltage symbol detection value, the ith calibration voltage signal used for calibration is determined in real time based on the ith voltage calibration code, no extra time is needed for short circuit, the processing speed of the pipeline analog-to-digital converter is improved, and offset voltage generated by a circuit can be tracked and calibrated in real time.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic structural diagram of an analog-to-digital conversion circuit according to an embodiment of the present application;
fig. 2 is a schematic structural diagram of an analog-to-digital conversion circuit according to an embodiment of the present application;
fig. 3 is a schematic structural diagram of a calibration voltage generating circuit according to an embodiment of the present application;
fig. 4 is a schematic structural diagram of an analog-to-digital conversion circuit according to an embodiment of the present application;
fig. 5 is a schematic structural diagram of an analog-to-digital converter according to an embodiment of the present application;
fig. 6 is a schematic structural diagram of a comparator in an analog-to-digital converter according to an embodiment of the present application;
fig. 7 is a schematic structural diagram of an analog-to-digital conversion circuit according to an embodiment of the present application.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present application more apparent, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments of the present application.
Thus, the following detailed description of the embodiments of the application, as presented in the figures, is not intended to limit the scope of the application, as claimed, but is merely representative of selected embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
In the description of the present application, it should be noted that, if the terms "upper", "lower", and the like indicate an azimuth or a positional relationship based on the azimuth or the positional relationship shown in the drawings, or an azimuth or the positional relationship conventionally put in use of the product of the application, it is merely for convenience of describing the present application and simplifying the description, and it is not indicated or implied that the apparatus or element referred to must have a specific azimuth, be configured and operated in a specific azimuth, and thus should not be construed as limiting the present application.
Furthermore, the terms first, second and the like in the description and in the claims and in the above-described figures, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the application described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
It should be noted that the features of the embodiments of the present application may be combined with each other without conflict.
Fig. 1 is a schematic structural diagram of an analog-to-digital conversion circuit according to an embodiment of the present application, as shown in fig. 1, the analog-to-digital conversion circuit may include: a pipeline analog-digital converter 101 formed by N stages of analog-digital converters, N-1 detection circuits 102, N-1 calibration circuits 103 and N-1 first calibration voltage generation circuits 104; n is an integer greater than or equal to 2.
Where i is an integer less than N, i may be an integer greater than 0 and less than or equal to N-1. The i-th stage analog-to-digital converter 101 may be any one of the N-stage analog-to-digital converters other than the N-th stage analog-to-digital converter 101.
The digital end of the ith analog-to-digital converter 101 is electrically connected with a first detection input end of a detection circuit 102 to output an ith digital code; the digital end of the (i+1) -th analog-to-digital converter 101 is electrically connected to the second detection input end of the detection circuit 102 to output the (i+1) -th digital code, so that the detection circuit 102 outputs the (i) -th voltage symbol detection value based on the (i+1) -th digital code and the (i+1) -th digital code; a first detection output of a detection circuit 102 is electrically connected to a first calibration input of a calibration circuit 103, such that the calibration circuit 103 outputs an i-th voltage calibration code based on the i-th voltage symbol detection value.
In some embodiments, the analog voltage is input to the i-th stage analog-to-digital converter 101, the i-th stage analog-to-digital converter 101 may convert the input analog voltage, and the digital end of the i-th stage analog-to-digital converter 101 may output the i-th digital code; the i+1-th analog-to-digital converter 101 is input with the residual voltage, the i+1-th analog-to-digital converter 101 may convert the input residual voltage, and the digital terminal of the i+1-th analog-to-digital converter 101 may output the i+1-th digital code. The margin voltage may be an analog voltage remaining unprocessed by the i-th stage analog-to-digital converter 101.
Correspondingly, a detection circuit 102 electrically connected to the i-th analog-to-digital converter 101 and the i+1-th analog-to-digital converter 101 can obtain the i-th digital code and the i+1-th digital code; determining an ith voltage symbol detection value according to the ith digital code and the (i+1) th digital code, and inputting the ith voltage symbol detection value to a first calibration input end of the calibration circuit 103; the calibration circuit 103 may acquire the i-th voltage symbol detection value and output the i-th voltage calibration code according to the i-th voltage symbol detection value.
It should be noted that, a series of combinational logic circuits may be included in one detection circuit 102, and one detection circuit 102 may detect the polarity of the offset voltage according to the magnitude relation of the preset bit values in the ith digital code and the (i+1) th digital code, so as to determine the sign detection value of the ith voltage. When the offset voltage is determined to be positive, the i-th voltage symbol detection value may be 1; when it is determined that the offset voltage is negative, the i-th voltage sign detection value may be 0.
In addition, the calibration circuit 103 generates and outputs an i-th voltage calibration code, which may be a multi-bit binary code, based on the i-th voltage symbol detection value. When the number of bits of the ith voltage calibration code is larger, the step size of the calibration voltage is smaller, the calibration precision is higher, but the hardware consumption of the circuit is also increased, and the convergence time of the calibration is also prolonged; on the contrary, when the number of bits of the ith voltage calibration code is small, the calibration step length is large, the precision is low, the hardware consumption is small, the convergence time is short, and the bit number design of the ith voltage calibration code can be determined according to the overall performance and the requirements of the circuit.
A first calibration output terminal of a calibration circuit 103 is electrically connected to a digital terminal of a first calibration voltage generation circuit 104, so that the first calibration voltage generation circuit 104 outputs an ith calibration voltage signal based on the ith voltage calibration code; an analog terminal of the first calibration voltage generating circuit 104 is electrically connected to a first input terminal of the comparator in the ith analog-to-digital converter 101, so that the comparator in the ith analog-to-digital converter 101 outputs the ith target digital code according to the ith calibration voltage signal and the corresponding input analog signal. The ith calibration voltage signal may be correspondingly increased or decreased by one voltage step every time the ith voltage calibration code is increased or decreased by "1".
In some embodiments, the first calibration output of one calibration circuit 103 may input the i-th voltage calibration code to the digital terminal of one first calibration voltage generation circuit 104 that is electrically connected; the first calibration voltage generation circuit 104 may acquire the ith voltage calibration code and output the ith calibration voltage signal according to the ith voltage calibration code. The ith calibration voltage signal may be an analog voltage.
In the embodiment of the application, the ith calibration voltage signal and the analog signal are input into the comparator in the ith analog-to-digital converter 101, and the ith calibration voltage signal can balance the offset voltage generated by the comparator in the ith analog-to-digital converter 101, so that the ith target digital code of the converted output is more accurate, and the influence of the offset voltage on the equipment pipeline analog-to-digital converter is reduced.
In addition, the ith calibration voltage signal may calibrate offset voltages generated by the ith analog-to-digital converter 101 and the (i+1) th analog-to-digital converter 101, so that a relative offset voltage value of both the ith analog-to-digital converter 101 and the (i+1) th analog-to-digital converter 101 may be 0.
It should be noted that, an offset calibration circuit may include a detection circuit 102, a calibration circuit 103, and a first calibration voltage generation circuit 104.
Alternatively, the analog voltage input to the i-th stage analog-to-digital converter 101 may be denoted as Vi, the analog voltage input to the i+1-th stage analog-to-digital converter 101 may be denoted as Vresi, and the analog voltage output from the i+1-th stage analog-to-digital converter 101 may be denoted as vresi+1. The ith digital code may be denoted as Di, the (i+1) th digital code may be denoted as di+1, the ith voltage symbol detection value may be denoted as Deci, the ith voltage calibration code may be denoted as Dcali, and the ith calibration voltage signal may be denoted as Vcali.
In summary, an embodiment of the present application provides an analog-to-digital conversion circuit, including: the system comprises a pipeline analog-digital converter formed by N stages of analog-digital converters, N-1 detection circuits, N-1 calibration circuits and N-1 first calibration voltage generation circuits; n is an integer greater than or equal to 2; if i is an integer smaller than N, the digital end of the ith analog-to-digital converter is electrically connected with the first detection input end of a detection circuit to output the ith digital code; the digital end of the (i+1) -th level analog-to-digital converter is electrically connected with the second detection input end of a detection circuit to output the (i+1) -th digital code, so that the detection circuit outputs the (i) th voltage symbol detection value based on the (i+1) -th digital code and the (i+1) -th digital code; a first detection output end of the detection circuit is electrically connected with a first calibration input end of a calibration circuit, so that the calibration circuit outputs an ith voltage calibration code based on an ith voltage symbol detection value; a first calibration output terminal of a calibration circuit is electrically connected to a digital terminal of a first calibration voltage generation circuit, so that the first calibration voltage generation circuit outputs an ith calibration voltage signal based on an ith voltage calibration code; the analog end of a first calibration voltage generating circuit is electrically connected with the first input end of the comparator in the ith analog-to-digital converter so that the comparator in the ith analog-to-digital converter outputs an ith target digital code according to the ith calibration voltage signal and the corresponding input analog signal. Only N-1 detection circuits, N-1 calibration circuits and N-1 first calibration voltage generation circuits are needed, so that the calibration of the pipeline analog-digital converter consisting of the N-stage analog-digital converters can be realized, and the number of required offset calibration circuits is reduced. And the ith voltage symbol detection value is generated based on the ith digital code and the (i+1) th digital code, the ith voltage calibration code can be determined based on the ith voltage symbol detection value, the ith calibration voltage signal used for calibration is determined in real time based on the ith voltage calibration code, no extra time is needed for short circuit, the processing speed of the pipeline analog-to-digital converter is improved, and offset voltage generated by a circuit can be tracked and calibrated in real time.
In addition, the analog-to-digital conversion circuit provided by the embodiment of the application can enable the digital code obtained by conversion to be more accurate in the normal working process of the pipeline analog-to-digital converter.
Optionally, fig. 2 is a schematic structural diagram of an analog-to-digital conversion circuit according to an embodiment of the present application, where, as shown in fig. 2, the analog-to-digital conversion circuit further includes: a second calibration voltage generation circuit 105;
the second detection output end of the (N-1) -th detection circuit 102 is electrically connected to the second calibration input end of the (N-1) -th calibration circuit 103, so that the (N-1) -th detection circuit 102 outputs an (N) -th voltage detection value based on the (N) -th digital code output by the (N) -th analog-to-digital converter 101;
the second calibration output terminal of the N-1 th calibration circuit 103 is electrically connected to the digital terminal of the second calibration voltage generation circuit 105, so that the N-1 th calibration circuit 103 outputs an nth voltage calibration code based on the nth voltage detection value, so that the second calibration voltage generation circuit 105 outputs an nth calibration voltage signal based on the nth voltage calibration code;
the analog terminal of the second calibration voltage generating circuit 105 is electrically connected to one input terminal of the comparator in the nth stage analog-to-digital converter 101, so that the comparator in the nth stage analog-to-digital converter 101 generates and outputs the nth target digital code based on the nth calibration voltage signal and the corresponding input analog signal.
The nth stage analog-to-digital converter 101 may be the last analog-to-digital converter in the pipeline analog-to-digital converter. The last offset calibration circuit may include a detection circuit 102, a calibration circuit 103, a first calibration voltage generation circuit 104, and a second calibration voltage generation circuit 105.
In some embodiments, the N-1 th detection circuit 102 may determine the N-1 th voltage detection value based on the N-1 th digital code output from the N-1 th analog-to-digital converter 101 and the N-th digital code output from the N-th analog-to-digital converter 101; the (N-1) -th calibration circuit 103 may output an (N-1) -th voltage calibration code based on the (N-1) -th voltage detection value; the first calibration voltage generation circuit 104 electrically connected to the N-1 th calibration circuit 103 outputs an N-1 th calibration voltage signal according to the N-1 th voltage calibration code, and the N-1 th calibration voltage signal can be used to calibrate offset voltages generated by the N-1 th analog-to-digital converter 101 and the comparator of the N-th analog-to-digital converter 101.
In addition, the N-1 calibration circuit 103 outputs an nth voltage calibration code based on the nth voltage detection value, and the second calibration voltage generation circuit 105 outputs an nth calibration voltage signal based on the nth voltage calibration code, where the nth calibration voltage signal may also be used to calibrate an offset voltage generated by the comparator of the nth stage analog-to-digital converter 101, which may enable calibration of the offset voltage generated by the nth stage analog-to-digital converter 101 to be more accurate, and further enable the nth target digital code output by the nth stage analog-to-digital converter 101 to be more accurate, and may enable the offset voltage of the overall output code of the pipeline analog-to-digital converter to be calibrated to be 0.
Alternatively, the analog voltage input to the N-1 th analog-to-digital converter 101 may be denoted as Vn-1, and the analog voltage input to the N-th analog-to-digital converter 101 may be denoted as Vresn-1. The N-1 th digital code may be denoted as Dn-1 and the N-th digital code may be denoted as Dn; the nth-1 voltage detection value may be denoted as Decn-1, and the nth voltage detection value may be denoted as Decn; the N-1 th voltage calibration code may be denoted as Dcaln-1 and the N-th voltage calibration code may be denoted as Dcaln; the N-1 th calibration voltage signal may be denoted as Vcain-1 and the N-th calibration voltage signal may be denoted as Vcain.
Optionally, fig. 3 is a schematic structural diagram of a calibration voltage generating circuit according to an embodiment of the present application, where the first calibration voltage generating circuit 104 and the second calibration voltage generating circuit 105 may be calibration voltage generating circuits with the same structure, and as shown in fig. 3, the calibration voltage generating circuit includes: a first switch array 107, M first resistors R1, M-1 second resistors R2, and a third resistor R3; where M is equal to the number of bits of the voltage calibration code, the number of the third resistors R3 may be 2, as an option.
The first ends of the M-1 second resistors R2 which are sequentially connected in series are grounded through the third resistor R3, and the second ends of the M-1 second resistors R2 which are sequentially connected in series are analog ends of the calibration voltage generating circuit. The voltage calibration code input by the first switch array 107 may be denoted as Dcal.
The input end of the first switch array 107 is a digital end of the calibration voltage generating circuit, and the power end of the first switch array 107 is electrically connected with a preset reference voltage; the M output ends of the first switch array 107 are respectively and electrically connected with one end of M first resistors R1, and two ends of each second resistor R2 in the M-1 second resistors R2 are respectively and electrically connected with the other ends of two first resistors R1. Optionally, two ends of each second resistor R2 of the M-1 second resistors R2 are respectively electrically connected to the other ends of two adjacent first resistors R1.
The preset reference voltage may include: VRP (high level voltage), VRN (low level voltage).
In addition, the digital end of the calibration voltage generation circuit may output an ith voltage calibration code, which may be a multi-bit binary code. One end of each first resistor R1 is respectively controlled by the ith voltage calibration code to be connected to a reference voltage VRP or VRN, the leftmost first resistor R1 is controlled by the highest weight bit of the ith voltage calibration code, and the rightmost first resistor R1 is controlled by the lowest weight bit of the ith voltage calibration code. Wherein, when a weight bit of the ith voltage calibration code is 1, the first resistor R1 controlled by the weight bit is connected to the reference voltage VRP; when a weight bit of the ith voltage calibration code is 0, the first resistor R1 controlled by the weight bit is connected to the reference voltage VRN.
It should be noted that, each time the i-th voltage calibration code is increased or decreased by "1", the i-th calibration voltage signal may be correspondingly increased or decreased by one voltage step.
Wherein the voltage step size can be expressed as:wherein, VRP, VRN are reference voltages, n represents the number of bits of the ith voltage calibration code, which may be the same as the number of the first resistors R1, i.e., n may be equal to M.
Alternatively, the resistance of the first resistor R1 may be twice the resistance of the second resistor R2, i.e. r1=2r2.
Optionally, fig. 4 is a schematic structural diagram of an analog-to-digital conversion circuit according to an embodiment of the present application, as shown in fig. 4, where the analog-to-digital conversion circuit may further include: n-1 amplifiers 106;
the amplifier 106 may be a residual voltage amplifier, the residual output end of the i-th stage analog-to-digital converter 101 is further electrically connected to the input end of one amplifier 106, and the output end of one amplifier 106 is further electrically connected to the analog end of the i+1-th stage analog-to-digital converter 101.
It should be noted that, in the related art, when the analog-to-digital conversion circuit further includes the amplifier 106, a correction circuit is also required for each amplifier 106. In the embodiment of the application, based on the N-1 detection circuits 102, the N-1 calibration circuits 103 and the N-1 first calibration voltage generation circuits 104, the offset voltages of the N analog-to-digital converters and the N-1 amplifiers 106 can be adjusted, so that the number of required correction circuits is further reduced.
In addition, the ith calibration voltage signal may calibrate the offset voltage generated by the amplifier 106 between the ith analog-to-digital converter 101 and the (i+1) th analog-to-digital converter 101, so that the relative offset voltage value of the ith analog-to-digital converter 101, the (i+1) th analog-to-digital converter 101 and the (i+1) th analog-to-digital converter 101) amplifier 106 is 0.
Alternatively, the analog voltage output by the i-th stage analog-to-digital converter 101 may be denoted as Vresi, and the amplifier 106 amplifies the Vresi to output an analog voltage Vrai, which may be used as an input of the i+1-th stage analog-to-digital converter 101.
Optionally, fig. 5 is a schematic structural diagram of an analog-to-digital converter according to an embodiment of the present application, as shown in fig. 5, each stage of analog-to-digital converter includes: the second input end of the comparator 110 is electrically connected with the analog end of each stage of analog-to-digital converter, and the output end of the comparator 110 is the digital end of each stage of analog-to-digital converter;
the output end of the comparator 110 is further electrically connected to a digital end of the digital-to-analog converter, an analog end of the digital-to-analog converter is further electrically connected to an analog end of each stage of the analog-to-digital converter, and a margin output end of each stage of the analog-to-digital converter.
Alternatively, the analog-to-digital converter 101 in the embodiment of the present application may be a successive approximation type analog-to-digital converter.
Fig. 6 is a schematic diagram of a structure of a comparator in an analog-to-digital converter according to an embodiment of the present application, as shown in fig. 6, a first input 1101 of a comparator 110 may be a non-inverting input, an ith calibration voltage signal may be input into the comparator 110 through the first input 1101, and an analog signal may be input into the comparator 110 through a second input 1102 of the comparator 110, so as to implement superposition of the ith calibration voltage signal and the analog signal. In addition, the comparator 110 may further include a ground 1104 and an output 1103.
It should be noted that, in the embodiment shown in fig. 6, the comparator is a single-ended circuit schematic diagram, and in the actual design, the analog-to-digital converter may have a fully differential circuit structure, that is, the analog-to-digital converter includes a forward signal port and a reverse signal port, and the voltage signals applied by the two ports have the characteristics of equal voltage values and opposite directions, so in the fully differential circuit structure, the comparator 110 may include two positive input ends of the first input end 1101 and the second input end 1102, and a negative input end corresponding to the signals, and may no longer include the ground terminal 1104.
Optionally, as shown in fig. 5, the digital-to-analog converter may further include: a second switch array 108, a capacitor array 109; wherein the input end of the second switch array 108 is the digital end of the digital-to-analog converter;
the output ends of the second switch array 108 are respectively electrically connected to one end of each capacitor in the capacitor array 109, and the other end of each capacitor in the capacitor array 109 is an analog end of the digital-to-analog converter.
Optionally, as shown in fig. 4, each calibration circuit 103 also has a trigger terminal; each calibration circuit 103 is specifically configured to output a voltage calibration code according to the received voltage detection value when the trigger signal received by the trigger terminal is valid.
Wherein the trigger signal may be denoted as TRIG.
In one possible implementation, the calibration circuit 103 adjusts the ith voltage calibration code based on the ith voltage symbol detected value for each rising edge of the trigger signal. Subtracting "1" from the i-th voltage calibration code when the i-th voltage symbol detection value is 1; when the i-th voltage symbol detection value is 0, the i-th voltage calibration code is added with '1'; wherein "1" represents the minimum weight bit of the ith voltage calibration code.
It should be noted that, when the ith voltage calibration code reaches the upper boundary, i.e. "111 … …", the next rising edge of the trigger signal comes, and when the detection value of the ith voltage symbol is 0, the output ith voltage calibration code remains unchanged; when the i-th voltage symbol detection value is 1, the i-th voltage calibration code is subjected to a minus 1 operation. If the ith voltage calibration code reaches the lower boundary, i.e. "000 … … 0", but the next trigger signal rising edge comes, when the ith voltage symbol detection value is 1, the output code remains unchanged; when the i-th voltage symbol detection value is 0, the i-th voltage calibration code is added with 1.
Optionally, as shown in fig. 4, each calibration circuit 103 further has a restart end, and each calibration circuit 103 is further configured to reset the output voltage calibration code to a preset code value when detecting that a restart signal input by the restart end is valid; and outputting a voltage calibration code according to the received voltage detection value when the restarting signal is detected to be invalid and the triggering signal is detected to be valid.
Wherein the reset signal may be denoted RST, which may also be referred to as reset signal.
In the embodiment of the application, when the restart signal is 0, the restart signal is valid; when the restart signal is 1, the restart signal is not valid. When the restarting signal is 0, resetting the output voltage calibration code to a preset code value of '100 … … 0', wherein the first bit of the preset code value is the highest weight bit, and can be used for controlling the highest bit capacitor in the calibration voltage generation circuit; when the restart signal is 1, the restart signal does not affect the circuit, the calibration circuit 103 is controlled by other signals, and the calibration circuit 103 can be controlled by a trigger signal.
Optionally, as shown in fig. 4, each calibration circuit 103 further has an enable terminal, and each calibration circuit 103 is specifically configured to output a voltage calibration code according to the received voltage detection value when the restart signal is inactive, the trigger signal is active, and the enable signal input by the enable terminal is active.
Wherein, the enable signal can be represented by EN, and when the enable signal is 0, the enable signal is inactive; when the enable signal is 1, the enable signal is active.
When rst=1 and en=0, the calibration circuit 103 keeps the output of the current voltage calibration code unchanged, and the TRIG is disabled; when rst=1, en=1, the TRIG functions, and the calibration circuit 103 operates normally.
In the following, a pipeline analog-to-digital converter including two stages of analog-to-digital converters is taken as an example for illustration, fig. 7 is a schematic structural diagram of an analog-to-digital conversion circuit according to an embodiment of the present application, and as shown in fig. 7, the pipeline analog-to-digital converter may include: a first stage analog-to-digital converter 101, an amplifier 106, and a second stage analog-to-digital converter 101. Accordingly, the offset calibration circuit includes a detection circuit 102, a calibration circuit 103, a first calibration voltage generation circuit 104, and a second calibration voltage generation circuit 105.
The input analog voltage information Vin is first sampled by the first-stage analog-to-digital converter 101, and then quantized by a comparator of the first-stage analog-to-digital converter 101, so as to obtain a first-stage digital code (D1), and simultaneously generate a first-stage residual voltage (Vres 1). The comparator introduces an offset voltage (Vos 1) due to the offset. Vos1 will be contained in D1 and Vres1.
In addition, when the conversion of the first-stage analog-to-digital converter is completed, vres1 is transferred to the amplifier 106, and the amplifier 106 amplifies Vres1 by G times and outputs the voltage Vra. The amplification of the amplifier 106 is not related to calibration, and the amplification of the amplifier 106 may be set according to the power consumption and accuracy of the first-stage analog-to-digital converter 101, the amplifier 106, and the second-stage analog-to-digital converter 101. During amplification, the amplifier 106 may also introduce offset voltage (Vosra) due to transistor mismatch, etc., which may be superimposed in Vra and passed to the next analog-to-digital converter.
In an embodiment of the present application, the second-stage analog-to-digital converter 101 may sample Vra, and then the comparator in the second-stage analog-to-digital converter 101 quantizes to obtain the second-stage digital code (D2). The comparator of the second stage analog-to-digital converter 101 introduces offset voltage (Vos 2) and is also included in D2. During the amplification process of the amplifier 106, vres1 needs to be held by the first-stage analog-to-digital converter 101, and the first-stage analog-to-digital converter 101 is in a stationary state; after the amplification is completed, the first-stage analog-to-digital converter 101 performs sampling and conversion for the next cycle, and the second-stage analog-to-digital converter 101 simultaneously performs conversion for Vra.
Note that, assuming that the amplification factor of the inter-stage amplifier 106 is G, the total offset voltage Vosin may be:wherein, the first voltage detection value generated according to D1 and D2 is determined for polarity of Vosin, and the first voltage detection value output by the detection circuit 102 may be denoted as Dec1; the second voltage detection value generated according to D2 is determined by the polarity of Vos2, and the second voltage detection value output by the detection circuit 102 may be denoted as Dec2. The calibration circuit 103 outputs a first voltage calibration code (Dcal 1) according to Dec1 and a second voltage calibration code (Dcal 2) according to Dec2.
In addition, for the analog-to-digital conversion circuit shown in fig. 7, the first calibration voltage signal of the first stage analog-to-digital converter 101 may be denoted as Vcal1, and the second stage analog-to-digital converter 101The second calibration voltage signal may be denoted as Vcal2, and after calibration, the total input offset voltage of the analog-to-digital converter 101 may be denoted as:after several calibration procedures Vcal2 will eventually completely cancel Vos2, vcal1 will +.>And the offset is completely counteracted, so that the offset calibration function is realized.
In summary, in the analog-to-digital conversion circuit provided by the embodiment of the application, only the N-1 detection circuits, the N-1 calibration circuits and the N-1 first calibration voltage generation circuits are required to be arranged, so that the calibration of the pipeline analog-to-digital converter formed by the N-stage analog-to-digital converter can be realized, and the number of required offset calibration circuits is reduced. And the ith voltage symbol detection value is generated based on the ith digital code and the (i+1) th digital code, the ith voltage calibration code can be determined based on the ith voltage symbol detection value, and the ith calibration voltage signal used for calibration is determined in real time based on the ith voltage calibration code, so that additional time is not needed for short-circuiting, and the processing speed of the pipeline analog-to-digital converter is improved. Furthermore, a correction circuit is not required to be arranged for each amplifier in the analog-to-digital conversion circuit, so that the number of required offset calibration circuits is reduced.
The embodiment of the application also provides electronic equipment, which can comprise the analog-to-digital conversion circuit.
The above is only a preferred embodiment of the present application, and is not intended to limit the present application, but various modifications and variations can be made to the present application by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the protection scope of the present application.
Claims (10)
1. An analog-to-digital conversion circuit, comprising: the system comprises a pipeline analog-digital converter formed by N stages of analog-digital converters, N-1 detection circuits, N-1 calibration circuits and N-1 first calibration voltage generation circuits; n is an integer greater than or equal to 2;
if i is an integer smaller than N, the digital end of the ith analog-to-digital converter is electrically connected with the first detection input end of a detection circuit to output the ith digital code; the digital end of the (i+1) -th level analog-to-digital converter is electrically connected with the second detection input end of the one detection circuit to output an (i+1) -th digital code, so that the one detection circuit outputs an (i) -th voltage symbol detection value based on the (i+1) -th digital code and the (i+1) -th digital code; the first detection output end of the detection circuit is electrically connected with the first calibration input end of a calibration circuit, so that the calibration circuit outputs an ith voltage calibration code based on the ith voltage symbol detection value;
the first calibration output end of the one calibration circuit is electrically connected with the digital end of the one first calibration voltage generation circuit, so that the one first calibration voltage generation circuit outputs an ith calibration voltage signal based on the ith voltage calibration code; the analog end of the first calibration voltage generating circuit is electrically connected with the first input end of the comparator in the ith analog-to-digital converter, so that the comparator in the ith analog-to-digital converter outputs an ith target digital code according to the ith calibration voltage signal and the corresponding input analog signal.
2. The analog-to-digital conversion circuit of claim 1, further comprising: a second calibration voltage generation circuit;
the second detection output end of the (N-1) -th detection circuit is electrically connected with the second calibration input end of the (N-1) -th calibration circuit, so that the (N-1) -th detection circuit outputs an (N) -th voltage detection value based on the (N) -th digital code output by the (N) -th analog-to-digital converter;
a second calibration output end of the N-1 th calibration circuit is electrically connected with a digital end of the second calibration voltage generation circuit, so that the N-1 th calibration circuit outputs an N-th voltage calibration code based on the N-th voltage detection value, and the second calibration voltage generation circuit outputs an N-th calibration voltage signal based on the N-th voltage calibration code;
the analog end of the second calibration voltage generating circuit is electrically connected with one input end of the comparator in the N-th stage analog-to-digital converter, so that the comparator in the N-th stage analog-to-digital converter generates and outputs an N-th target digital code based on the N-th calibration voltage signal and the corresponding input analog signal.
3. The analog-to-digital conversion circuit according to claim 2, wherein the first calibration voltage generation circuit and the second calibration voltage generation circuit are calibration voltage generation circuits of the same structure, the calibration voltage generation circuit comprising: the first switch array, M first resistors, M-1 second resistors and a third resistor; wherein M is equal to the number of bits of the voltage calibration code;
the first ends of the M-1 second resistors which are sequentially connected in series are grounded through the third resistor, and the second ends of the M-1 second resistors which are sequentially connected in series are analog ends of the calibration voltage generating circuit;
the input end of the first switch array is a digital end of the calibration voltage generation circuit, and the power end of the first switch array is electrically connected with a preset reference voltage; the M output ends of the first switch array are respectively and electrically connected with one ends of M first resistors, and two ends of each second resistor in the M-1 second resistors are respectively and electrically connected with the other ends of the two first resistors.
4. The analog-to-digital conversion circuit of claim 3, wherein a resistance of the first resistor is twice a resistance of the second resistor.
5. The analog-to-digital conversion circuit of claim 1, further comprising: n-1 amplifiers;
the residual output end of the ith analog-to-digital converter is also electrically connected with the input end of an amplifier, and the output end of the amplifier is also electrically connected with the analog end of the (i+1) th analog-to-digital converter.
6. The analog-to-digital conversion circuit of claim 5, wherein each stage of analog-to-digital converter comprises: the second input end of the comparator is electrically connected with the analog end of each stage of analog-to-digital converter, and the output end of the comparator is the digital end of each stage of analog-to-digital converter;
the output end of the comparator is also electrically connected with the digital end of the digital-to-analog converter, and the analog end of the digital-to-analog converter is also electrically connected with the analog end of each stage of analog-to-digital converter and the residual output end of each stage of analog-to-digital converter.
7. The analog-to-digital conversion circuit of claim 6, wherein the digital-to-analog converter comprises: a second switch array, a capacitor array; the input end of the second switch array is the digital end of the digital-to-analog converter;
the output ends of the second switch array are respectively and electrically connected with one end of each capacitor in the capacitor array, and the other end of each capacitor in the capacitor array is an analog end of the digital-to-analog converter.
8. The analog-to-digital conversion circuit of claim 1, wherein each calibration circuit further has a trigger terminal; each calibration circuit is specifically configured to output a voltage calibration code according to the received voltage detection value when the trigger signal received by the trigger terminal is valid.
9. The analog-to-digital conversion circuit of claim 8, wherein each calibration circuit further has a restart terminal, and wherein each calibration circuit is further configured to reset the output voltage calibration code to a preset code value when a restart signal input from the restart terminal is detected to be valid; and outputting a voltage calibration code according to the received voltage detection value when the restarting signal is detected to be invalid and the triggering signal is detected to be valid.
10. The analog-to-digital conversion circuit of claim 8, wherein each calibration circuit further has an enable terminal, and wherein each calibration circuit is specifically configured to output a voltage calibration code according to the received voltage detection value when the restart signal is inactive and the trigger signal is active and the enable signal input from the enable terminal is active.
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