CN217363058U - Analog-digital converter circuit, analog-digital converter, and electronic apparatus - Google Patents

Abstract

The present application provides an analog-to-digital converter circuit, an analog-to-digital converter, and an electronic device, the analog-to-digital converter circuit, including: the full-parallel ADC is used for accessing an analog signal to be converted and quantizing the analog signal; the first-stage SAR ADC is connected with an analog signal, the control end of the highest-order capacitor of the first-stage SAR ADC is connected with the full-parallel ADC, and a residual error signal generated based on the analog signal and a signal quantized by the first-stage SAR ADC is quantized; the second-stage SAR ADC quantizes the accessed quantized signal again; the intermediate capacitor amplifier is arranged between the first-stage SARADC and the second-stage SARADC, comprises a first capacitor and a first operational amplifier which are connected in parallel, and a first switch which is connected with the first capacitor in series, wherein the first capacitor is used as a redundant bit capacitor of the second-stage SARADC, and the output result of the second-stage SARADC is calibrated. By the application of the ADC, the ADC with higher physical digit can be realized, and the conversion accuracy of the analog-digital converter circuit can be improved.

Description

Analog-digital converter circuit, analog-digital converter, and electronic apparatus

Technical Field

The present application relates to analog-to-digital converters, and more particularly to an analog-to-digital converter circuit, an analog-to-digital converter, and an electronic device.

Background

An analog-to-digital converter (ADC) is a key means for acquiring information in nature, and is capable of converting an analog signal into a digital signal. As an important medium for acquiring information, ADCs are widely used in the fields of wireless communication, industrial measurement, image recognition, and the like. With the further development of science and technology, the efficient acquisition of information in various fields is required more and more, and the requirements of high-speed and high-precision ADCs are increased continuously.

The ADC is of many kinds, mainly including: Sigma-Delta (Sigma-Delta modulation) type, integral type, SAR (Successive Approximation) type, Pipeline type, flash (full parallel) type, and the like, and also an excellent Pipeline SAR ADC (Pipeline-primary and secondary Approximation type analog-to-digital converter) compatible with the Pipeline ADC and the SAR ADC is produced due to the high conversion rate of the Pipeline ADC and the low power consumption of the SAR ADC.

Most of the existing Pipeline SAR ADC architectures include two SAR ADCs and an intermediate capacitive amplifier arranged between the two SAR ADCs, however, the ADC architectures often have several defects, firstly, the Pipeline SAR is difficult to implement 13-15bit ADCs on physical bits; secondly, the output swing of the intermediate-stage operational amplifier is the difference between two reference voltages (vrefp1 and vrefn1) of the prior-stage sar adc, and the voltage difference is large, so that the voltage margin is greatly consumed, and the power consumption requirement of the operational amplifier is improved.

Disclosure of Invention

The application provides an analog-to-digital converter circuit, an analog-to-digital converter and an electronic device, which can realize an ADC with a higher physical digit number and can improve the conversion accuracy of the analog-to-digital converter circuit.

An embodiment of a first aspect of the present application provides an analog-to-digital converter circuit, including:

the full-parallel ADC is used for accessing an analog signal to be converted and quantizing the analog signal to obtain a first quantized signal;

the first-stage SAR ADC is connected with the analog signal, the control end of the highest-order capacitor of the first-stage SAR ADC is connected with the full-parallel ADC, a residual error signal generated based on the analog signal and the first quantized signal is quantized, and a second quantized signal is obtained;

the second-stage SAR ADC quantizes the accessed quantized signal again to obtain a third quantized signal;

the middle capacitor amplifier is arranged between the first-stage SAR ADC and the second-stage SAR ADC, comprises a first capacitor and a first operational amplifier which are connected in parallel, and a first switch which is connected with the first capacitor in series, wherein the first capacitor is used as a redundant bit capacitor of the second-stage SAR ADC, and the output result of the second-stage SAR ADC is calibrated.

In some embodiments of the present application, the first operational amplifier includes an amplifier module and a voltage adjustment module, the voltage adjustment module including a MOS array for adjusting a gain-bandwidth product of the first operational amplifier.

In some embodiments of the present application, the voltage adjustment module includes a plurality of MOS arrays, and source and drain electrodes of the plurality of MOS arrays are connected end to end, and the gain-bandwidth product of the first operational amplifier is adjusted by changing the number of MOS arrays in a working state.

In some embodiments of the present application, the first operational amplifier has a power supply rejection ratio greater than or equal to a specified value.

In some embodiments of the present application, the first switch controls the first capacitor to be connected to the first stage sar adc or the reference voltage supply terminal, respectively; when the first capacitor is connected with the reference voltage power supply end, the first capacitor is used as a redundant bit capacitor of the second-stage SARADC, and the output result of the second-stage SARADC is calibrated; and when the first capacitor is connected with the first-stage SARADC, the first capacitor is used for amplifying the second quantized signal by a specified multiple.

In some embodiments of the present application, the apparatus further includes a resistor array disposed between the fully parallel ADC and the first stage SAR ADC for adjusting a voltage of the first quantized signal.

In some embodiments of the present application, the resistor array includes a plurality of resistors connected in series, and an on-off switch is disposed between any two resistors.

In some embodiments of the present application, the fully parallel ADC is an ADC with 4 bits of physical digits, the first stage SAR ADC is an ADC with 4 bits of physical digits, the second stage SAR ADC is an ADC with 6 bits or more of physical digits, and the amplification factor of the intermediate capacitive amplifier is 8 times.

Embodiments of a second aspect of the present application provide an analog-to-digital converter comprising the analog-to-digital converter circuit of the first aspect.

Embodiments of a third aspect of the present application provide an electronic device comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, and further comprising a digital logic circuit comprising an analog-to-digital converter as described in the second aspect.

The technical scheme provided in the embodiment of the application at least has the following technical effects or advantages:

the analog-digital converter circuit provided by the embodiment of the application comprises a flash ADC, a three-level architecture ADC (which can be called Pipeline SAR ADC, Pipeline-primary and secondary approximation type analog-digital converter) of a first-level SARADC and a second-level SARADC, wherein the flash ADC and the first-level SARADC are both connected to an analog signal to be converted, and the analog signal is directly converted through the flash ADC to generate a first quantized signal; quantizing a residual signal of the analog signal and the first quantized signal by a first-stage SARADC to obtain a second quantized signal; and then, quantizing the second quantized signal again through the second-level SARADC to obtain a final third quantized signal. Therefore, through the Pipeline SAR ADC with the three-level framework, three ADCs are processed in parallel, data conversion with more physical bits can be realized, and the working efficiency of the analog-digital converter circuit is improved. And the two latter SAR ADCs quantize the residual difference signals, so that the whole quantization result is corrected, and the conversion precision of the analog-digital converter circuit can be improved. And the first capacitor of the middle capacitor amplifier is utilized to realize the calibration of the redundant bit of the second-stage SAR ADC, and one bit is added on the basis of the original SAR bit number, so that the error of the second-stage SAR ADC can be calibrated, particularly the establishment error of the SAR, and the second-stage SAR ADC can modify the output result corresponding to each capacitor according to the output result of the comparator, thereby further improving the accuracy of the analog-digital converter circuit.

Drawings

Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the application. Also, like reference numerals are used to refer to like parts throughout the drawings.

In the drawings:

fig. 1 shows a schematic structural diagram of an analog-to-digital converter circuit provided in an embodiment of the present application;

FIG. 2 is a schematic diagram showing an enlarged structure of a resistor array in an embodiment of the present application;

FIG. 3 is a schematic diagram showing a first operational amplifier in the embodiment of the present application;

FIG. 4a shows a schematic diagram of a binary conversion process of a conventional SAR ADC;

FIG. 4b shows a schematic diagram of the binary conversion process of the SAR ADC under the influence of mechanical and build errors of the comparator;

FIG. 4c is a schematic diagram illustrating the binary conversion process of the SAR ADC with redundancy bit calibration in the embodiment of the present application;

fig. 5a shows a schematic diagram of the intermediate capacitor amplifier in the amplification operation mode in the first switch closed state in the embodiment of the present application;

FIG. 5b is a schematic diagram of the middle capacitor amplifier in the calibration operation mode in the first switch off state according to the embodiment of the present application;

fig. 6 shows a schematic flow chart of an analog-to-digital conversion method provided in an embodiment of the present application.

Detailed Description

Exemplary embodiments of the present application will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

It is to be noted that, unless otherwise specified, technical or scientific terms used herein shall have the ordinary meaning as understood by those skilled in the art to which this application belongs.

An analog-digital converter circuit, an analog-digital converter, and an electronic apparatus according to embodiments of the present application are described below with reference to the drawings.

Referring to fig. 1, an analog-to-digital converter circuit provided in the present embodiment is shown in fig. 1, and the circuit includes: the system comprises a full parallel ADC (flash ADC, also called a flicker analog-to-digital converter), a first-stage SARADC (successive approximation analog-to-digital converter), an intermediate capacitor amplifier and a second-stage SARADC.

The input end of the full-parallel ADC is connected with an analog signal to be converted, and the analog signal is quantized to obtain a first quantized signal. The first-stage SARADC is connected with the analog signal, the control end of the highest-order capacitor of the first-stage SARADC is connected with the full-parallel ADC, the residual error signal generated based on the analog signal and the first quantization signal is quantized, and a second quantization signal is obtained. And the second-stage SARADC quantizes the accessed quantized signal again to obtain a third quantized signal. And the intermediate capacitor amplifier is arranged between the first-stage SARADC and the second-stage SARADC and is used for amplifying the second quantized signal by a specified multiple and inputting the amplified quantized signal into the second-stage SARADC.

Specifically, the flash ADC may be a 4-bit physical bit ADC, the first stage sar ADC may be a 4-bit physical bit ADC, and the second stage sar ADC may be a 6-bit physical bit ADC. Thus, due to the arrangement of the 4-bit flash ADC, the number of bits that the ADC circuit can convert can be increased to 13 bits, and the number of bits of the second-stage sar ADC can be increased as needed, so as to realize higher physical bits, such as 15 bits, 16 bits, 18 bits, and the like. The designated multiple of the intermediate capacitor amplifier to the second quantized signal may be a multiple of 4, and may be specifically set according to the actual situation. The final output result of the analog-to-digital converter circuit is the sum of the output results of the flash ADC, the first-stage sar ADC and the second-stage sar ADC.

In another embodiment of this embodiment, as shown in fig. 1, the ADC circuit may further include a resistor array disposed between the flash ADC and the first stage sar ADC for adjusting a voltage of the first quantization signal. Therefore, after the flash ADC is subjected to analog-to-digital conversion, the output voltage of the resistor array is controlled by the output first quantization signal, and the output voltage can control the highest-order capacitor of the first-stage SARADC.

Specifically, as shown in fig. 2, the resistor array may include a plurality of resistors connected in series, and an on-off switch is disposed between any two resistors, and the on-off switch in the resistor array is controlled to control the resistance value of the resistor array by a given reference voltage Vref and a flash ADC output signal, so as to implement voltage control on the highest-order capacitor of the first-stage sar ADC, and thus a desired voltage may be provided for the highest-order capacitor of the first-stage sar ADC as needed to generate a corresponding residual error signal.

It should be noted that, in this embodiment, specific circuit structures of the flash ADC, the first-stage sar ADC and the second-stage sar ADC are not specifically limited, as long as the respective functions can be performed.

The analog-to-digital converter circuit provided by the embodiment comprises a flash ADC, a first-stage SAR ADC and a third-stage architecture ADC (which can be called as Pipeline-primary-secondary approximation type analog-to-digital converter) of the second-stage SAR ADC, wherein both the flash ADC and the first-stage SAR ADC are connected to an analog signal to be converted, and the flash ADC directly converts the analog signal to generate a first quantization signal; quantizing the analog signal and the residual signal of the first quantized signal by a first-stage SARADC to obtain a second quantized signal; and then, quantizing the second quantized signal again through the second-level SARADC to obtain a final third quantized signal. Therefore, through the Pipeline SAR ADC with the three-level framework, three ADCs are processed in parallel, data conversion with more physical bits can be realized, and the working efficiency of the analog-digital converter circuit is improved. And the two latter SAR ADCs quantize the residual difference signals, so that the whole quantization result is corrected, and the conversion precision of the analog-digital converter circuit can be improved.

In this embodiment, the structure and function of the first-stage SAR ADC, the second-stage SAR ADC, and the intermediate capacitor amplifier are further described by taking the implementation of the 13-bit Pipeline SAR ADC as an example.

As shown in fig. 1, the first stage SAR ADC includes a comparator, a logic control circuit, and a plurality of capacitors arranged according to binary weighting, and a common terminal (a terminal connected to the middle horizontal line in fig. 1) of all the capacitors is connected to the comparator and the logic control circuit, respectively, and receives an analog signal to be converted and a logic control signal thereof. The voltage control end of the lowest-order capacitor is connected with a reference voltage (Vcm1), the voltage control end of the highest-order capacitor (the lowest order capacitor is 32 times of the lowest order capacitor) is connected with the output end of the flash ADC, the supply voltage of the highest-order capacitor is controlled by the flash ADC (and the resistor array), the voltage control ends of other capacitors are free ends, and the connected reference voltage (Vrefp1-Vrefn1) can be selected according to logic control signals.

The structure of the second-stage SAR ADC is similar to that of the first-stage SAR ADC, and the second-stage SAR ADC also comprises a comparator, a logic control circuit and a plurality of capacitors (the number of the capacitors is different) which are arranged according to binary weighting, and the common end (the end connected with the middle horizontal line in fig. 1) of all the capacitors is respectively connected with the comparator and the logic control circuit and receives the second quantization signal and the logic control signal thereof. The voltage control terminal of the lowest-order capacitor is still connected with the reference voltage (Vcm2), and the voltage control terminals of other capacitors (including the highest-order capacitor) are free terminals, so that the connected reference voltages (Vrefp2-Vrefn2) can be selected according to logic control signals.

The intermediate capacitor amplifier may include a first capacitor and a first operational amplifier connected in parallel, and the first operational amplifier has a high power supply rejection ratio greater than or equal to a specified value to further improve the conversion accuracy of the analog-to-digital converter.

The input and the output of the power supply are regarded as independent signal sources, and the ripple ratio of the input and the output is the power supply rejection ratio, which is also called the power supply ripple rejection ratio (unit is dB). For a high-quality analog-to-digital converter, it is generally required that when a power supply voltage used for a switching circuit and an operational amplifier varies, the influence on the output voltage is extremely small, and the ratio of the percentage of the full-scale voltage variation to the percentage of the power supply voltage variation is generally referred to as a power supply rejection ratio. The larger the power supply rejection ratio is, the smaller the influence of the power supply on the output signal is, and the corresponding unit gain bandwidth is higher.

Since the intermediate capacitor amplifier of the present embodiment uses an operational amplifier with a high power supply rejection ratio, and the corresponding unit gain bandwidth is high, the amplification factor of the intermediate capacitor amplifier may be set to a smaller factor. For example, in the prior art, the operational amplifier is configured to be 16 times, and the amplification factor can be set to be 8 times in the embodiment. Therefore, the reference voltage and the output voltage of the first-stage SAR ADC are correspondingly reduced, the input voltage and the reference voltage of the second-stage SAR ADC are correspondingly reduced, namely, the voltage margin is reduced, and therefore the power consumption of the whole operational amplifier of the analog-digital converter circuit can be reduced.

For example, the amplification factor of the intermediate capacitor amplifier of the conventional pipeline SAR ADC is 16 times, the output swing amplitude is Vrefp1 '-Vrefn 1', and the amplification factor of the intermediate capacitor amplifier of the present embodiment is changed from 16 times to 8 times, so that the output swings Vrefp1-Vrefn1 thereof are changed to 0.5 times Vrefp1 '-Vrefn 1'. Meanwhile, the first capacitance is changed from 4 times capacitance to 8 times capacitance, and the output swing amplitude Vrefp2-Vrefn2 of the second-stage SAR ADC is also changed to 0.5 times Vrefp2 '-Vrefn 2' (the output swing of the second-stage SAR ADC of the conventional pipeline SAR ADC).

It should be noted that, in this embodiment, specific values of the high power supply rejection ratio of the first operational amplifier are not specifically limited, and those skilled in the art can set the values according to actual needs as long as the power supply rejection ratio is higher than that of a conventional operational amplifier.

As shown in fig. 3, the first operational amplifier may include an amplifier module and a voltage adjustment module, where the voltage adjustment module includes a MOS array for adjusting a gain-bandwidth product of the first operational amplifier. The MOS array can comprise a plurality of MOS arrays, such as MOS array 1-MOS array 5 in FIG. 3, and the bandwidth of the first operational amplifier can be adjusted more finely. The first operational amplifier is provided with an MOS array, and a gain-bandwidth product (GBW, which refers to the product of one amplifier bandwidth and the corresponding gain) of the first operational amplifier can be configured according to the design environment of the ADC through the MOS array. Moreover, when the GBW of the first operational amplifier is configured, not only the bandwidth of the first operational amplifier itself needs to be adjusted, but also the MOS array (the MOS array 5 in fig. 3) in the voltage adjustment module is synchronously increased along with the current of the first operational amplifier, so that the voltage adjustment module always works in the optimal region, and then the overall power consumption and the working efficiency of the first operational amplifier, the conversion accuracy and the like are further reduced.

Specifically, as shown in fig. 3, the connection manner between the MOS arrays may be set according to needs, and the present embodiment is not particularly limited. For example, the gain-bandwidth product of the first operational amplifier can be adjusted by changing the number of MOS arrays in operation, with the source and drain of different MOS arrays connected end to end.

It should be noted that the structure of the first operational amplifier is only an example of the present embodiment, and the present embodiment is not limited thereto, and may further include more MOS transistors and other electronic devices.

In a specific embodiment of this embodiment, the intermediate capacitor amplifier further includes a first switch, the first switch is connected in series with the first capacitor, and the first capacitor is controlled to be connected to the first-stage sar adc or the reference voltage power supply terminal, respectively; when the first capacitor is connected with the reference voltage power supply end, the first capacitor is used as a redundant bit capacitor of the second-stage SARADC, and redundant bit calibration is carried out on the output result of the second-stage SARADC.

In the application process of the ADC, the establishment of the analog-to-digital conversion function after each electronic component is started requires a process and a certain time, that is, the ADC establishment process, and an error may occur in a certain link in the establishment process, for example, an error comparison result may be generated because the processing time is not timely and some data are not compared, which may be called an establishment error. Meanwhile, the comparator itself has a certain mechanical error. Thus, the pipeline SAR ADC may generate certain errors in the application process.

As shown in fig. 4a-4c (the ordinate represents voltage, the abscissa represents time, B0-B3 represent 4 bits, respectively, and the pillars can represent voltage values, the broken line in the figure is a curve of the signal intensity variation acquired by the ADC, the rising of the broken line corresponds to a value of B0-B3 being 1, and the falling or non-varying of the broken line corresponds to a value of B0-B3 being 0), fig. 4a (in the figure) is a binary conversion process of the conventional sar ADC, and the output result of the sar ADC is Dout 8B 3+ 4B 2+ 2B 1+ 1B 0 8 0+ 8B 860 + 4. Fig. 4B shows that due to the mechanical error and the build error of the comparator, the output will generate an erroneous comparison result, resulting in the output result of sar adc being Dout 8B 3+ 4B 2+ 2B 1+ 1B 0 8 + 4B 0+ 2+ 1+ 3, i.e. the conversion result of sar adc output error. In fig. 4c, the redundant alignment of the B2 'bit is achieved, so that the output returns to the normal comparison result, and the output result of the sar adc is Dout 8B 3+ 4B 2+4 (B2' -0.5) + 2B 1+ 1B 0 8 + 0+4 (1-0.5) 2+ 1.

As shown in fig. 5a, when the first switch is closed to connect the first capacitor to the first stage SAR ADC, the first capacitor is only used as a capacitor of the intermediate capacitor amplifier, and the operating mode of the intermediate capacitor amplifier is an amplification mode, and the intermediate capacitor amplifier can amplify a second quantized signal (for example, 8 times) output by the first stage SAR ADC, and the amplified signal is used as a quantized signal of the second stage SAR ADC. As shown in fig. 5b, when the first switch is turned off, the first capacitor is connected to the reference voltage supply terminal, and at this time, the first capacitor can be used as a redundant bit capacitor of the second SAR ADC, and can perform redundant bit calibration on an output result of the second SAR ADC, so that the first capacitor of the intermediate capacitor amplifier can be used to calibrate the redundant bit of the second SAR ADC, and one bit is added on the basis of the original SAR bit number to calibrate an error of the second SAR ADC, especially a building error of the SAR, so that the second SAR ADC can modify output results corresponding to the capacitors according to the output result of the data comparator, thereby further improving the accuracy of the analog-to-digital converter circuit. In addition, through the arrangement of the first switch, the first capacitor can play a role in the two working modules, namely the recycling of the capacitor, and a redundant capacitor does not need to be specially arranged, so that the overall development cost is reduced.

Based on the same concept of the analog-to-digital converter circuit, the present embodiment further provides an analog-to-digital conversion method, as shown in fig. 6, including the following steps:

step S1, quantizing the analog signal to be converted through the full parallel ADC, and inputting a first quantized signal obtained by quantization into the first-stage SAR ADC;

step S2, quantizing a residual signal generated based on the analog signal and the first quantized signal through a first-stage SAR ADC, and inputting a second quantized signal obtained by quantization into a middle capacitor amplifier;

step S3, amplifying the second quantized signal by a specified multiple through the middle capacitor amplifier, and inputting the amplified quantized signal into the second-stage SAR ADC;

and step S4, quantizing the amplified quantized signal again through the second-stage SAR ADC to obtain a third quantized signal.

The method can be applied to the analog-digital converter circuit described above, and can also be applied to other circuits as long as the analog-digital conversion method can be implemented.

In the analog-digital conversion method provided by this embodiment, both the flash ADC and the first-stage sar ADC are connected to an analog signal to be converted, and the analog signal is directly converted by the flash ADC to generate a first quantized signal; quantizing a residual signal of the analog signal and the first quantized signal by a first-stage SARADC to obtain a second quantized signal; and then, quantizing the second quantized signal again through the second-level SARADC to obtain a final third quantized signal. Therefore, three ADCs are processed in parallel through the Pipeline SAR ADC with the three-level architecture, data conversion of more physical bits can be achieved, and the working efficiency of the analog-digital converter circuit is improved. And the two latter SAR ADCs quantize the residual difference signals, so that the whole quantization result is corrected, and the conversion precision of the analog-digital converter circuit can be improved.

Based on the same concept of the analog-to-digital converter circuit, the present embodiment further provides an analog-to-digital converter including the analog-to-digital converter circuit of any of the above embodiments.

The adc provided by this embodiment is based on the same concept of the adc circuits, and therefore can at least achieve the beneficial effects that the adc circuits can achieve, which is not described herein again.

Based on the same concept of the analog-to-digital converter circuit, the embodiment further provides an electronic device, which includes a memory, a processor, and a computer program stored in the memory and executable on the processor, and further includes a digital logic circuit, and the digital logic circuit includes the analog-to-digital converter as described above. Specifically, the electronic device may be a Micro Control Unit (MCU) including the above-described analog-digital converter, or a chip formed with the micro control unit, and the above-described wireless charging system, motor control system (or control device of only the system) and the like using the chip.

The electronic device provided in this embodiment is based on the same concept of the analog-to-digital converter circuit, so that at least the beneficial effects that the analog-to-digital converter circuit can achieve can be achieved, and are not described herein again.

It should be noted that the above-mentioned embodiments illustrate rather than limit the application, and that those skilled in the art will be able to design alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The application may be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In the unit claims enumerating several means, several of these means may be embodied by one and the same item of hardware. The usage of the words first, second and third, etcetera do not indicate any ordering. These words may be interpreted as names.

The above description is only for the preferred embodiments of the present application, but the scope of the present application is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present application should be covered within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims (10)

1. An analog-to-digital converter circuit, comprising:

the full-parallel ADC is used for accessing an analog signal to be converted and quantizing the analog signal to obtain a first quantized signal;

the first-stage SARADC is connected with the analog signal, the control end of the highest-order capacitor of the first-stage SARADC is connected with the full-parallel ADC, a residual difference signal generated based on the analog signal and the first quantized signal is quantized, and a second quantized signal is obtained;

the second-stage SARADC quantizes the accessed quantized signal again to obtain a third quantized signal;

the intermediate capacitor amplifier is arranged between the first-stage SARADC and the second-stage SARADC, comprises a first capacitor and a first operational amplifier which are connected in parallel, and a first switch which is connected with the first capacitor in series, wherein the first capacitor is used as a redundant bit capacitor of the second-stage SARADC, and is used for calibrating an output result of the second-stage SARADC.

2. The circuit of claim 1, wherein the first operational amplifier comprises an amplifier module and a voltage adjustment module, wherein the voltage adjustment module comprises a MOS array configured to adjust a gain-bandwidth product of the first operational amplifier.

3. The circuit of claim 2, wherein the voltage adjustment module comprises a plurality of MOS arrays, and source and drain electrodes of the plurality of MOS arrays are connected end to end, and the gain-bandwidth product of the first operational amplifier is adjusted by changing the number of MOS arrays in an operating state.

4. The circuit of claim 1, wherein the first operational amplifier has a power supply rejection ratio greater than or equal to a specified value.

5. The circuit of claim 2, wherein the first switch controls the first capacitor to be connected to the first stage sar adc or a reference voltage supply terminal, respectively; when the first capacitor is connected with the reference voltage power supply end, the first capacitor is used as a redundant bit capacitor of the second-stage SARADC, and the output result of the second-stage SARADC is calibrated; and when the first capacitor is connected with the first-stage SARADC, the first capacitor is used for amplifying the second quantized signal by a specified multiple.

6. The circuit of claim 1, further comprising a resistor array disposed between the fully parallel ADC and the first stage SARADC for regulating a voltage of the first quantized signal.

7. The circuit of claim 6, wherein the resistor array comprises a plurality of resistors connected in series, and an on-off switch is disposed between any two resistors.

8. The circuit of claim 1, wherein the fully parallel ADC is a 4-bit physical bit ADC, the first stage sar ADC is a 4-bit physical bit ADC, the second stage sar ADC is a 6-bit or greater physical bit ADC, and the intermediate capacitive amplifier has a magnification of 8.

9. An analog-to-digital converter comprising an analog-to-digital converter circuit according to any of claims 1 to 8.

10. An electronic device comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, further comprising a digital logic circuit comprising the analog-to-digital converter of claim 9.

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