CN113328748A - Analog-to-digital conversion circuit - Google Patents
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Abstract
The invention provides an analog-to-digital conversion circuit, and relates to the technical field of circuits. The method comprises the following steps: the device comprises a pipeline analog-to-digital converter consisting of N stages of analog-to-digital converters, N-1 detection circuits, N-1 calibration circuits and N-1 first calibration voltage generation circuits; if i is an integer less than N, the digital end of the ith-stage analog-to-digital converter is electrically connected with a first detection input end of a detection circuit; the digital end of the (i + 1) th-level analog-to-digital converter is electrically connected with a second detection input end of a detection circuit; the first detection output end of one detection circuit is electrically connected with the first calibration input end of one calibration circuit; the first calibration output end of a calibration circuit is electrically connected with the digital end of a first calibration voltage generation circuit; the analog end of the first calibration voltage generation circuit is electrically connected with the first input end of the comparator in the ith stage analog-to-digital converter. The number of calibration circuits is reduced, the offset voltage is tracked and calibrated in real time, and the processing speed of the analog-to-digital converter is improved.
Description
Technical Field
The invention relates to the technical field of circuits, in particular to an analog-to-digital conversion circuit.
Background
The pipeline analog-to-digital converter is an analog-to-digital conversion structure, has the advantages of high speed and high precision, and is widely applied to 5G (5th generation mobile communication technology) and next-generation high-speed and high-capacity communication systems. Due to the asymmetry of the manufacturing process, offset voltage can be introduced, and the problem of inaccurate conversion result can occur, so that the reduction of the offset voltage has great significance for the equipment pipeline analog-to-digital converter.
In the related art, a correction circuit is provided for each device in the pipeline analog-to-digital converter, for example, a correction circuit is provided for each analog-to-digital converter in the pipeline analog-to-digital converter, and calibration is achieved by shorting an input port of a comparator in the analog-to-digital converter.
However, in the related art, each device needs to be provided with one correction circuit, and the number of correction circuits is large, which requires extra time for short-circuit, and reduces the processing speed of the pipeline analog-to-digital converter.
Disclosure of Invention
The present invention is directed to provide an analog-to-digital conversion circuit, so as to solve the problems in the related art that a correction circuit needs to be provided for each device, the number of required correction circuits is large, additional time is required for short-circuiting, and the processing speed of a pipeline analog-to-digital converter is reduced.
In order to achieve the above purpose, the embodiment of the present invention adopts the following technical solutions:
in a first aspect, an embodiment of the present invention provides an analog-to-digital conversion circuit, including: the device comprises a pipeline analog-to-digital converter consisting of N stages of analog-to-digital converters, N-1 detection circuits, N-1 calibration circuits and N-1 first calibration voltage generation circuits; n is an integer greater than or equal to 2;
if i is an integer smaller than N, the digital end of the ith-stage analog-to-digital converter is electrically connected with a first detection input end of a detection circuit to output an ith digital code; the digital end of the (i + 1) th-stage analog-to-digital converter is electrically connected with the second detection input end of the detection circuit to output an (i + 1) th digital code, so that the detection circuit outputs an (i) th voltage symbol detection value based on the (i + 1) th digital code and the (i + 1) th digital code; the first detection output end of the detection circuit is electrically connected with the first calibration input end of a calibration circuit, so that the calibration circuit outputs an ith voltage calibration code based on the ith voltage symbol detection value;
the first calibration output end of the calibration circuit is electrically connected with the digital end of a first calibration voltage generation circuit, so that the first calibration voltage generation circuit outputs an ith calibration voltage signal based on the ith voltage calibration code; the analog end of the first calibration voltage generation circuit is electrically connected with the first input end of the comparator in the ith-stage analog-to-digital converter, so that the comparator in the ith-stage analog-to-digital converter outputs the ith target digital code according to the ith calibration voltage signal and the corresponding input analog signal.
Optionally, the analog-to-digital conversion circuit further includes: a second calibration voltage generating circuit;
the second detection output end of the (N-1) th detection circuit is electrically connected with the second calibration input end of the (N-1) th calibration circuit, so that the (N-1) th detection circuit outputs an Nth voltage detection value based on the Nth digital code output by the Nth-stage analog-to-digital converter;
a second calibration output terminal of the (N-1) th calibration circuit is electrically connected to a digital terminal of the second calibration voltage generation circuit to cause the (N-1) th calibration circuit to output an Nth voltage calibration code based on the Nth voltage detection value, such that the second calibration voltage generation circuit outputs an Nth calibration voltage signal based on the Nth voltage calibration code;
the analog end of the second calibration voltage generation circuit is electrically connected with one input end of the comparator in the Nth-stage analog-to-digital converter, so that the comparator in the Nth-stage analog-to-digital converter generates and outputs the Nth target digital code based on the Nth calibration voltage signal and the corresponding input analog signal.
Optionally, the first calibration voltage generating circuit and the second calibration voltage generating circuit are calibration voltage generating circuits with the same structure, and the calibration voltage generating circuit includes: the circuit comprises a first switch array, M first resistors, M-1 second resistors and a third resistor; wherein M is equal to the number of bits of the voltage calibration code;
the first ends of the M-1 second resistors which are sequentially connected in series are grounded through the third resistor, and the second ends of the M-1 second resistors which are sequentially connected in series are analog ends of the calibration voltage generating circuit;
the input end of the first switch array is a digital end of the calibration voltage generating circuit, and a power supply end of the first switch array is electrically connected with a preset reference voltage; the M output ends of the first switch array are respectively and electrically connected with one ends of the M first resistors, and two ends of each of the M-1 second resistors are respectively and electrically connected with the other ends of the two first resistors.
Optionally, the resistance value of the first resistor is twice the resistance value of the second resistor.
Optionally, the analog-to-digital conversion circuit further includes: n-1 amplifiers;
the residual output end of the ith-level analog-to-digital converter is also electrically connected with the input end of an amplifier, and the output end of the amplifier is also electrically connected with the analog end of the (i + 1) th-level analog-to-digital converter.
Optionally, each stage of the analog-to-digital converter includes: a comparator and a digital-to-analog converter, wherein a second input end of the comparator is electrically connected with an analog end of each stage of analog-to-digital converter, and an output end of the comparator is a digital end of each stage of analog-to-digital converter;
the output end of the comparator is also electrically connected with the digital end of the digital-to-analog converter, and the analog end of the digital-to-analog converter is also electrically connected with the analog end of each stage of analog-to-digital converter and the residual output end of each stage of analog-to-digital converter.
Optionally, the digital-to-analog converter includes: a second switch array, a capacitor array; the input end of the second switch array is the digital end of the digital-to-analog converter;
and a plurality of output ends of the second switch array are respectively and electrically connected with one end of each capacitor in the capacitor array, and the other end of each capacitor in the capacitor array is an analog end of the digital-to-analog converter.
Optionally, each calibration circuit further has a trigger terminal; each calibration circuit is specifically configured to output a voltage calibration code according to a received voltage detection value when the trigger signal received by the trigger terminal is valid.
Optionally, each calibration circuit further has a restart end, and each calibration circuit is further configured to reset the output voltage calibration code to a preset code value when detecting that a restart signal input by the restart end is valid; and outputting a voltage calibration code according to the received voltage detection value when the restart signal is detected to be invalid and the trigger signal is detected to be valid.
Optionally, each calibration circuit further has an enable terminal, and each calibration circuit is specifically configured to output a voltage calibration code according to a received voltage detection value when the restart signal is invalid, the trigger signal is valid, and an enable signal input by the enable terminal is valid.
The invention has the beneficial effects that: an embodiment of the present application provides an analog-to-digital conversion circuit, including: the device comprises a pipeline analog-to-digital converter consisting of N stages of analog-to-digital converters, N-1 detection circuits, N-1 calibration circuits and N-1 first calibration voltage generation circuits; n is an integer greater than or equal to 2; if i is an integer smaller than N, the digital end of the ith-stage analog-to-digital converter is electrically connected with a first detection input end of a detection circuit to output an ith digital code; the digital end of the (i + 1) th-level analog-to-digital converter is electrically connected with the second detection input end of a detection circuit to output an (i + 1) th digital code, so that the detection circuit outputs an ith voltage symbol detection value based on the (i + 1) th digital code and the (i + 1) th digital code; a first detection output end of the detection circuit is electrically connected with a first calibration input end of the calibration circuit, so that the calibration circuit outputs an ith voltage calibration code based on an ith voltage symbol detection value; a first calibration output terminal of a calibration circuit is electrically connected with a digital terminal of a first calibration voltage generation circuit, so that the first calibration voltage generation circuit outputs an ith calibration voltage signal based on an ith voltage calibration code; an analog end of the first calibration voltage generation circuit is electrically connected with a first input end of a comparator in the ith-stage analog-to-digital converter, so that the comparator in the ith-stage analog-to-digital converter outputs an ith target digital code according to an ith calibration voltage signal and a corresponding input analog signal. The calibration of the pipeline analog-to-digital converter formed by the N-level analog-to-digital converters can be realized only by arranging N-1 detection circuits, N-1 calibration circuits and N-1 first calibration voltage generation circuits, and the number of required offset calibration circuits is reduced. And moreover, an ith voltage symbol detection value is generated based on the ith digital code and the (i + 1) th digital code, an ith voltage calibration code can be determined based on the ith voltage symbol detection value, an ith calibration voltage signal for calibration is determined in real time based on the ith voltage calibration code, short circuit is not needed to be carried out in extra time, the processing speed of the pipeline analog-to-digital converter is improved, and offset voltage generated by the circuit can be tracked and calibrated in real time.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.
Fig. 1 is a schematic structural diagram of an analog-to-digital conversion circuit according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of an analog-to-digital conversion circuit according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a calibration voltage generating circuit according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of an analog-to-digital conversion circuit according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of an analog-to-digital converter according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of a comparator in an analog-to-digital converter according to an embodiment of the present invention;
fig. 7 is a schematic structural diagram of an analog-to-digital conversion circuit according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention.
Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it should be noted that if the terms "upper", "lower", etc. are used for indicating the orientation or positional relationship based on the orientation or positional relationship shown in the drawings or the orientation or positional relationship which is usually arranged when the product of the application is used, the description is only for convenience of describing the application and simplifying the description, but the indication or suggestion that the referred device or element must have a specific orientation, be constructed in a specific orientation and operation, and thus, cannot be understood as the limitation of the application.
Furthermore, the terms "first," "second," and the like in the description and in the claims, as well as in the drawings, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the invention described herein are capable of operation in sequences other than those illustrated or described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
It should be noted that the features of the embodiments of the present application may be combined with each other without conflict.
Fig. 1 is a schematic structural diagram of an analog-to-digital conversion circuit according to an embodiment of the present invention, as shown in fig. 1, the analog-to-digital conversion circuit may include: a pipeline analog-to-digital converter 101 consisting of N stages of analog-to-digital converters, N-1 detection circuits 102, N-1 calibration circuits 103 and N-1 first calibration voltage generation circuits 104; n is an integer greater than or equal to 2.
If i is an integer less than N, i can be an integer greater than 0 and less than or equal to N-1. The ith-stage analog-to-digital converter 101 may be any one of the N-stage analog-to-digital converters except for the nth-stage analog-to-digital converter 101.
The digital end of the ith-stage analog-to-digital converter 101 is electrically connected with a first detection input end of a detection circuit 102 to output an ith digital code; the digital end of the (i + 1) th stage analog-to-digital converter 101 is electrically connected with the second detection input end of a detection circuit 102 to output an (i + 1) th digital code, so that the detection circuit 102 outputs an (i) th voltage symbol detection value based on the (i + 1) th digital code and the (i + 1) th digital code; a first detection output terminal of a detection circuit 102 is electrically connected to a first calibration input terminal of a calibration circuit 103, so that the calibration circuit 103 outputs an ith voltage calibration code based on an ith voltage symbol detection value.
In some embodiments, an analog voltage is input to the ith stage analog-to-digital converter 101, the ith stage analog-to-digital converter 101 may convert the input analog voltage, and the digital terminal of the ith stage analog-to-digital converter 101 may output an ith digital code; the residue voltage is input to the (i + 1) th stage analog-to-digital converter 101, the (i + 1) th stage analog-to-digital converter 101 may convert the input residue voltage, and the (i + 1) th digital code may be output from the digital terminal of the (i + 1) th stage analog-to-digital converter 101. The residual voltage may be an unprocessed analog voltage remaining in the ith stage adc 101.
Correspondingly, a detection circuit 102 electrically connected to the ith-stage analog-to-digital converter 101 and the (i + 1) th-stage analog-to-digital converter 101 can acquire the ith digital code and the (i + 1) th digital code; determining an ith voltage symbol detection value according to the ith digital code and the (i + 1) th digital code, and inputting the ith voltage symbol detection value to a first calibration input end of the calibration circuit 103; the calibration circuit 103 may obtain an ith voltage symbol detection value and output an ith voltage calibration code based on the ith voltage symbol detection value.
It should be noted that, a detection circuit 102 may include a series of combinational logic circuits, and a detection circuit 102 may detect the polarity of the offset voltage according to the magnitude relationship between the preset bit values in the ith digital code and the (i + 1) th digital code to determine the detection value of the ith voltage symbol. When the offset voltage is determined to be positive, the ith voltage sign detection value can be 1; when it is determined that the offset voltage is negative, the ith voltage sign detection value may be 0.
In addition, the calibration circuit 103 generates and outputs an ith voltage calibration code, which may be a multi-bit binary code, based on the ith voltage symbol detection value. When the number of bits of the ith voltage calibration code is more, the step length of the calibration voltage is smaller, the calibration precision is higher, but the hardware consumption of the circuit is increased, and the convergence time of the calibration is prolonged; on the contrary, when the number of bits of the ith voltage calibration code is less, the calibration step is large, the precision is low, the hardware consumption is low, and the convergence time is short.
A first calibration output terminal of the calibration circuit 103 is electrically connected to a digital terminal of a first calibration voltage generating circuit 104, so that the first calibration voltage generating circuit 104 outputs an ith calibration voltage signal based on the ith voltage calibration code; an analog terminal of the first calibration voltage generation circuit 104 is electrically connected to a first input terminal of a comparator in the ith stage adc 101, so that the comparator in the ith stage adc 101 outputs an ith target digital code according to the ith calibration voltage signal and a corresponding input analog signal. Wherein, for each increment or decrement of "1" in the ith voltage calibration code, the ith calibration voltage signal may be correspondingly increased or decreased by one voltage step.
In some embodiments, the first calibration output terminal of one calibration circuit 103 may input the ith voltage calibration code to the digital terminal of one first calibration voltage generation circuit 104 electrically connected; the first calibration voltage generation circuit 104 may obtain an ith voltage calibration code and output an ith calibration voltage signal according to the ith voltage calibration code. Wherein, the ith calibration voltage signal may be an analog voltage.
In the embodiment of the present application, the ith calibration voltage signal and the analog signal are both input to the comparator in the ith stage analog-to-digital converter 101, and the ith calibration voltage signal can equalize the offset voltage generated by the comparator in the ith stage analog-to-digital converter 101, so that the ith target digital code output by conversion is more accurate, and the influence of the offset voltage on the device pipeline analog-to-digital converter is reduced.
In addition, the ith calibration voltage signal may calibrate offset voltages generated by the ith-stage adc 101 and the (i + 1) th-stage adc 101, so that the relative offset voltage values of the ith-stage adc 101 and the (i + 1) th-stage adc 101 may be 0.
It should be noted that an offset calibration circuit may include a detection circuit 102, a calibration circuit 103, and a first calibration voltage generation circuit 104.
Alternatively, the analog voltage input by the i-th stage analog-to-digital converter 101 may be denoted by Vi, the analog voltage input by the i + 1-th stage analog-to-digital converter 101 may be denoted by Vresi, and the analog voltage output by the i + 1-th stage analog-to-digital converter 101 may be denoted by Vresi + 1. The ith digital code may be represented as Di, the ith +1 digital code may be represented as Di +1, the ith voltage symbol detection value may be represented as Deci, the ith voltage calibration code may be represented as Dcali, and the ith calibration voltage signal may be represented as Vcali.
In summary, an embodiment of the present application provides an analog-to-digital conversion circuit, including: the device comprises a pipeline analog-to-digital converter consisting of N stages of analog-to-digital converters, N-1 detection circuits, N-1 calibration circuits and N-1 first calibration voltage generation circuits; n is an integer greater than or equal to 2; if i is an integer smaller than N, the digital end of the ith-stage analog-to-digital converter is electrically connected with a first detection input end of a detection circuit to output an ith digital code; the digital end of the (i + 1) th-level analog-to-digital converter is electrically connected with the second detection input end of a detection circuit to output an (i + 1) th digital code, so that the detection circuit outputs an ith voltage symbol detection value based on the (i + 1) th digital code and the (i + 1) th digital code; a first detection output end of the detection circuit is electrically connected with a first calibration input end of the calibration circuit, so that the calibration circuit outputs an ith voltage calibration code based on an ith voltage symbol detection value; a first calibration output terminal of a calibration circuit is electrically connected with a digital terminal of a first calibration voltage generation circuit, so that the first calibration voltage generation circuit outputs an ith calibration voltage signal based on an ith voltage calibration code; an analog end of the first calibration voltage generation circuit is electrically connected with a first input end of a comparator in the ith-stage analog-to-digital converter, so that the comparator in the ith-stage analog-to-digital converter outputs an ith target digital code according to an ith calibration voltage signal and a corresponding input analog signal. The calibration of the pipeline analog-to-digital converter formed by the N-level analog-to-digital converters can be realized only by arranging N-1 detection circuits, N-1 calibration circuits and N-1 first calibration voltage generation circuits, and the number of required offset calibration circuits is reduced. And moreover, an ith voltage symbol detection value is generated based on the ith digital code and the (i + 1) th digital code, an ith voltage calibration code can be determined based on the ith voltage symbol detection value, an ith calibration voltage signal for calibration is determined in real time based on the ith voltage calibration code, short circuit is not needed to be carried out in extra time, the processing speed of the pipeline analog-to-digital converter is improved, and offset voltage generated by the circuit can be tracked and calibrated in real time.
Moreover, the analog-to-digital conversion circuit provided by the embodiment of the application can enable the digital code obtained by conversion to be more accurate in the normal working process of the pipeline analog-to-digital converter.
Optionally, fig. 2 is a schematic structural diagram of an analog-to-digital conversion circuit according to an embodiment of the present invention, and as shown in fig. 2, the analog-to-digital conversion circuit further includes: a second calibration voltage generating circuit 105;
the second detection output terminal of the (N-1) th detection circuit 102 is electrically connected to the second calibration input terminal of the (N-1) th calibration circuit 103, so that the (N-1) th detection circuit 102 outputs an N-th voltage detection value based on the N-th digital code output by the N-th stage analog-to-digital converter 101;
a second calibration output terminal of the (N-1) th calibration circuit 103 is electrically connected to a digital terminal of the second calibration voltage generation circuit 105 to cause the (N-1) th calibration circuit 103 to output an Nth voltage calibration code based on the Nth voltage detection value, so that the second calibration voltage generation circuit 105 outputs an Nth calibration voltage signal based on the Nth voltage calibration code;
an analog end of the second calibration voltage generation circuit 105 is electrically connected to one input end of a comparator in the nth stage analog-to-digital converter 101, so that the comparator in the nth stage analog-to-digital converter 101 generates and outputs an nth target digital code based on the nth calibration voltage signal and a corresponding input analog signal.
The nth stage adc 101 may be the last adc in the pipeline adc. The last offset calibration circuit may include a detection circuit 102, a calibration circuit 103, a first calibration voltage generation circuit 104, and a second calibration voltage generation circuit 105.
In some embodiments, the (N-1) th detection circuit 102 may determine the (N-1) th voltage detection value according to the (N-1) th digital code output by the (N-1) th stage analog-to-digital converter 101 and the (N) th digital code output by the (N-1) th stage analog-to-digital converter 101; the (N-1) th calibration circuit 103 may output an (N-1) th voltage calibration code based on the (N-1) th voltage detection value; the first calibration voltage generating circuit 104 electrically connected to the (N-1) th calibration circuit 103 outputs an (N-1) th calibration voltage signal according to the (N-1) th voltage calibration code, wherein the (N-1) th calibration voltage signal can be used for calibrating offset voltages generated by the comparators of the (N-1) th stage analog-to-digital converter 101 and the (N-1) th stage analog-to-digital converter 101.
In addition, the nth voltage calibration code is output by the nth-1 calibration circuit 103 based on the nth voltage detection value, the nth calibration voltage signal is output by the second calibration voltage generation circuit 105 based on the nth voltage calibration code, and the nth calibration voltage signal can also be used for calibrating offset voltage generated by a comparator of the nth stage analog-to-digital converter 101, so that calibration of the offset voltage generated by the nth stage analog-to-digital converter 101 can be more accurate, the nth target digital code output by the nth stage analog-to-digital converter 101 can be more accurate, and the offset voltage of the whole output code of the pipeline analog-to-digital converter can be calibrated to be 0.
Alternatively, the analog voltage input to the nth-1 stage adc 101 may be denoted as Vn-1, and the analog voltage input to the nth stage adc 101 may be denoted as Vresn-1. The N-1 number code can be represented as Dn-1, and the N number code can be represented as Dn; the nth-1 voltage detection value may be represented as Decn-1, and the nth voltage detection value may be represented as Decn; the Nth-1 voltage calibration code may be denoted as Dcaln-1 and the Nth voltage calibration code may be denoted as Dcaln; the nth-1 calibration voltage signal may be denoted as Vcaln-1 and the nth calibration voltage signal may be denoted as Vcaln.
Optionally, fig. 3 is a schematic structural diagram of a calibration voltage generating circuit according to an embodiment of the present invention, where the first calibration voltage generating circuit 104 and the second calibration voltage generating circuit 105 may be calibration voltage generating circuits with the same structure, and as shown in fig. 3, the calibration voltage generating circuit includes: a first switch array 107, M first resistors R1, M-1 second resistors R2, and a third resistor R3; where M is equal to the number of bits of the voltage calibration code, the number of the third resistors R3 may be 2.
The first ends of the M-1 second resistors R2 which are sequentially connected in series are grounded through the third resistor R3, and the second ends of the M-1 second resistors which are sequentially connected in series are analog ends of the calibration voltage generating circuit. The voltage calibration code input to the first switch array 107 may be denoted Dcal.
The input end of the first switch array 107 is a digital end of the calibration voltage generating circuit, and the power supply end of the first switch array 107 is electrically connected with a preset reference voltage; the M output terminals of the first switch array 107 are electrically connected to one ends of the M first resistors R1, respectively, and two ends of each second resistor R2 of the M-1 second resistors R2 are electrically connected to the other ends of the two first resistors R1, respectively. Optionally, two ends of each second resistor R2 of the M-1 second resistors R2 are electrically connected to the other ends of two adjacent first resistors R1, respectively.
Wherein, the presetting of the reference voltage may include: VRP (high level voltage), VRN (low level voltage).
In addition, the digital terminal of the calibration voltage generation circuit may output an ith voltage calibration code, and the ith voltage calibration code may be a multi-bit binary code. One end of each first resistor R1 is controlled to be connected to the reference voltage VRP or VRN respectively by the ith voltage calibration code, the leftmost first resistor R1 is controlled by the highest weight bit of the ith voltage calibration code, and the rightmost first resistor R1 is controlled by the lowest weight bit of the ith voltage calibration code. When a weight bit of the ith voltage calibration code is 1, a first resistor R1 controlled by the weight bit is connected to the reference voltage VRP; when a weight bit of the ith voltage calibration code is 0, the first resistor R1 controlled by the weight bit is connected to the reference voltage VRN.
It should be noted that, for each increment or decrement of "1" in the ith voltage calibration code, the ith calibration voltage signal may be correspondingly increased or decreased by one voltage step.
Wherein, the voltage step can be expressed as:
where VRP, VRN are reference voltages, n represents the number of bits of the ith voltage calibration code, and the number of bits of the ith voltage calibration code may be the same as the number of the first resistors R1, i.e., n may be equal to M.
Alternatively, the resistance of the first resistor R1 may be twice the resistance of the second resistor R2, i.e., R1 — 2 × R2.
Optionally, fig. 4 is a schematic structural diagram of an analog-to-digital conversion circuit provided in an embodiment of the present invention, and as shown in fig. 4, the analog-to-digital conversion circuit may further include: n-1 amplifiers 106;
the amplifier 106 may be a margin voltage amplifier, the margin output terminal of the ith-stage analog-to-digital converter 101 is further electrically connected to an input terminal of one amplifier 106, and an output terminal of one amplifier 106 is further electrically connected to the analog terminal of the (i + 1) th-stage analog-to-digital converter 101.
It should be noted that, in the related art, when the analog-to-digital conversion circuit further includes the amplifier 106, a correction circuit is also required to be provided for each amplifier 106. In the embodiment of the present application, the offset voltages of the N analog-to-digital converters and the N-1 amplifiers 106 can be adjusted based on the N-1 detection circuits 102, the N-1 calibration circuits 103, and the N-1 first calibration voltage generation circuits 104, so that the number of required correction circuits is further reduced.
In addition, the ith calibration voltage signal can also calibrate the offset voltage generated by the amplifier 106 between the ith-stage adc 101 and the (i + 1) th-stage adc 101, so that the relative offset voltage values of the amplifier 106 between the ith-stage adc 101, the (i + 1) th-stage adc 101, the ith-stage adc 101 and the (i + 1) th-stage adc 101 are 0.
Alternatively, the analog voltage output by the i-th stage analog-to-digital converter 101 may be denoted as Vresi, and the amplifier 106 amplifies Vresi to output an analog voltage Vrai, where the Vrai may be used as an input of the i + 1-th stage analog-to-digital converter 101.
Optionally, fig. 5 is a schematic structural diagram of an analog-to-digital converter according to an embodiment of the present invention, and as shown in fig. 5, each stage of the analog-to-digital converter includes: the second input end of the comparator 110 is electrically connected with the analog end of each stage of analog-to-digital converter, and the output end of the comparator 110 is the digital end of each stage of analog-to-digital converter;
the output terminal of the comparator 110 is further electrically connected to the digital terminal of the digital-to-analog converter, and the analog terminal of the digital-to-analog converter is further electrically connected to the analog terminal of each stage of the analog-to-digital converter and the remaining output terminal of each stage of the analog-to-digital converter.
Optionally, the analog-to-digital converter 101 in the embodiment of the present application may be a successive approximation type analog-to-digital converter.
Fig. 6 is a schematic structural diagram of a comparator in an analog-to-digital converter according to an embodiment of the present invention, as shown in fig. 6, a first input terminal 1101 of a comparator 110 may be a non-inverting input terminal, an ith calibration voltage signal may be input into the comparator 110 through the first input terminal 1101, and an analog signal may be input into the comparator 110 through a second input terminal 1102 of the comparator 110, so as to realize the superposition of the ith calibration voltage signal and the analog signal. In addition, the comparator 110 may further include a ground terminal 1104 and an output terminal 1103.
It should be noted that, the comparator shown in fig. 6 is a schematic diagram of a single-ended circuit structure, and in an actual design, the analog-to-digital converter may adopt a fully differential circuit structure, that is, includes a forward signal port and a reverse signal port, and voltage signals applied to the two ports have characteristics of equal voltage value and opposite directions, so in the fully differential circuit structure, the comparator 110 may include two forward input ends of the first input end 1101 and the second input end 1102 and a negative input end corresponding to the positive input ends, and may not include the ground end 1104.
Optionally, as shown in fig. 5, the digital-to-analog converter may further include: a second switch array 108, a capacitor array 109; wherein, the input end of the second switch array 108 is the digital end of the digital-to-analog converter;
a plurality of output terminals of the second switch array 108 are electrically connected to one end of each capacitor in the capacitor array 109, respectively, and the other end of each capacitor in the capacitor array 109 is an analog end of the digital-to-analog converter.
Optionally, as shown in fig. 4, each calibration circuit 103 further has a trigger terminal; each calibration circuit 103 is specifically configured to output a voltage calibration code according to the received voltage detection value when the trigger signal received by the trigger terminal is valid.
Wherein the trigger signal may be denoted as TRIG.
In one possible embodiment, the calibration circuit 103 adjusts the ith voltage calibration code according to the ith voltage sign detection value every time the trigger signal has a rising edge. When the ith voltage sign detection value is 1, subtracting 1 from the ith voltage calibration code; when the symbol detection value of the ith voltage is 0, adding 1 to the ith voltage calibration code; where "1" represents the minimum weight bit of the ith voltage alignment code.
It should be noted that, when the ith voltage calibration code reaches the upper boundary, that is, "111 … … 1", and the rising edge of the next trigger signal comes, when the detected value of the ith voltage symbol is 0, the ith voltage calibration code is output and remains unchanged; when the symbol detection value of the ith voltage is 1, subtracting 1 from the ith voltage calibration code. If the ith voltage calibration code reaches the lower boundary, namely '000 … … 0', and the rising edge of the next trigger signal comes, when the detection value of the ith voltage symbol is 1, the output code is kept unchanged; when the symbol detection value of the ith voltage is 0, adding 1 to the ith voltage calibration code.
Optionally, as shown in fig. 4, each calibration circuit 103 further has a restart end, and each calibration circuit 103 is further configured to reset the output voltage calibration code to a preset code value when detecting that a restart signal input by the restart end is valid; and outputting a voltage calibration code according to the received voltage detection value when the restart signal is detected to be invalid and the trigger signal is detected to be valid.
The restart signal may be denoted as RST, and may also be referred to as a reset signal.
In the embodiment of the present application, when the restart signal is 0, the restart signal is valid; when the restart signal is 1, the restart signal is invalid. When the restart signal is 0, resetting the output voltage calibration code to a preset code value of 100 … … 0', wherein the first bit of the preset code value is the highest weight bit and can be used for controlling the highest bit capacitor in the calibration voltage generation circuit; when the restart signal is 1, the restart signal does not affect the circuit, the calibration circuit 103 is controlled by other signals, and the calibration circuit 103 may be controlled by a trigger signal.
Optionally, as shown in fig. 4, each calibration circuit 103 further has an enable terminal, and each calibration circuit 103 is specifically configured to output a voltage calibration code according to the received voltage detection value when the restart signal is invalid, the trigger signal is valid, and the enable signal input by the enable terminal is valid.
Wherein, the enable signal can be represented by EN, and when the enable signal is 0, the enable signal is invalid; when the enable signal is 1, the enable signal is active.
When RST is equal to 1 and EN is equal to 0, the calibration circuit 103 keeps the output of the current voltage calibration code unchanged, and the TRIG does not function; when RST is 1 and EN is 1, the TRIG is activated and the calibration circuit 103 operates normally.
In the following, a pipeline analog-to-digital converter including two stages of analog-to-digital converters is taken as an example for description, and fig. 7 is a schematic structural diagram of an analog-to-digital conversion circuit according to an embodiment of the present invention, as shown in fig. 7, the pipeline analog-to-digital converter may include: a first-stage analog-to-digital converter 101, an amplifier 106 and a second-stage analog-to-digital converter 101. Accordingly, the offset calibration circuit includes a detection circuit 102, a calibration circuit 103, a first calibration voltage generation circuit 104, and a second calibration voltage generation circuit 105.
The input analog voltage information Vin is first sampled by the first stage analog-to-digital converter 101, and then quantized by the comparator of the first stage analog-to-digital converter 101 to obtain the first stage digital code (D1), and at the same time, the first stage residue voltage (Vres1) is generated. The comparator introduces an offset voltage (Vos1) due to the offset. Vos1 would be contained at D1 and Vres 1.
In addition, when the first stage analog-to-digital converter conversion is completed, Vres1 is transferred to amplifier 106, and amplifier 106 outputs voltage Vra after amplifying Vres1 by G times. The amplification of the amplifier 106 is not related to calibration, and the amplification of the amplifier 106 can be set according to the power consumption and accuracy of the first stage adc 101, the amplifier 106, and the second stage adc 101. During amplification, the amplifier 106 also introduces offset voltage (Vosra) due to transistor mismatch, etc., and the Vosra is superimposed on Vra and passed to the next stage of the analog-to-digital converter.
In this embodiment, the second stage adc 101 may sample Vra, and then the comparator in the second stage adc 101 quantizes to obtain the second stage digital code (D2). The comparator of the second stage adc 101 introduces an offset voltage (Vos2), which is also included in D2. During amplification by amplifier 106, Vres1 needs to be held by first stage analog to digital converter 101, first stage analog to digital converter 101 is in a quiescent state; after amplification is completed, the first stage adc 101 performs sampling and conversion for the next cycle, and the second stage adc 101 performs conversion for Vra at the same time.
It should be noted that, assuming that the amplification factor of the inter-stage amplifier 106 is G, the total offset voltage Vosin may be:
wherein the first voltage detection value generated according to D1 and D2 is to determine the polarity of Vosin, and the first voltage detection value output by the detection circuit 102 may be denoted as Dec 1; the second voltage detection value generated by D2 is the second voltage output by the detection circuit 102, which is obtained by determining the polarity of Vos2The detection value may be denoted as Dec 2. The calibration circuit 103 outputs a first voltage calibration code (Dcal1) according to Dec1 and a second voltage calibration code (Dcal2) according to Dec 2.
In addition, for the analog-to-digital conversion circuit shown in fig. 7, the first calibration voltage signal of the first stage analog-to-digital converter 101 may be represented as Vcal1, the second calibration voltage signal of the second stage analog-to-digital converter 101 may be represented as Vcal2, and after calibration, the total input offset voltage of the analog-to-digital converter 101 may be represented as:
after several calibration procedures, Vcal2 will eventually completely cancel Vos2, and Vcal1 will
And completely offsetting, and realizing the function of maladjustment calibration.
In summary, the analog-to-digital conversion circuit provided by the embodiment of the application can calibrate the pipeline analog-to-digital converter composed of the N-level analog-to-digital converters only by setting the N-1 detection circuits, the N-1 calibration circuits and the N-1 first calibration voltage generation circuits, and the number of required offset calibration circuits is reduced. And moreover, the ith voltage symbol detection value is generated based on the ith digital code and the (i + 1) th digital code, the ith voltage calibration code can be determined based on the ith voltage symbol detection value, the ith calibration voltage signal for calibration is determined in real time based on the ith voltage calibration code, short circuit is not needed to be carried out in extra time, and the processing speed of the pipeline analog-to-digital converter is improved. Furthermore, there is no need to provide a correction circuit for each amplifier in the analog-to-digital conversion circuit, reducing the number of offset calibration circuits required.
The embodiment of the present application may further provide an electronic device, and the electronic device may include the analog-to-digital conversion circuit.
The above is only a preferred embodiment of the present invention, and is not intended to limit the present invention, and various modifications and changes will occur to those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. An analog-to-digital conversion circuit, comprising: the device comprises a pipeline analog-to-digital converter consisting of N stages of analog-to-digital converters, N-1 detection circuits, N-1 calibration circuits and N-1 first calibration voltage generation circuits; n is an integer greater than or equal to 2;
if i is an integer smaller than N, the digital end of the ith-stage analog-to-digital converter is electrically connected with a first detection input end of a detection circuit to output an ith digital code; the digital end of the (i + 1) th-stage analog-to-digital converter is electrically connected with the second detection input end of the detection circuit to output an (i + 1) th digital code, so that the detection circuit outputs an (i) th voltage symbol detection value based on the (i + 1) th digital code and the (i + 1) th digital code; the first detection output end of the detection circuit is electrically connected with the first calibration input end of a calibration circuit, so that the calibration circuit outputs an ith voltage calibration code based on the ith voltage symbol detection value;
the first calibration output end of the calibration circuit is electrically connected with the digital end of a first calibration voltage generation circuit, so that the first calibration voltage generation circuit outputs an ith calibration voltage signal based on the ith voltage calibration code; the analog end of the first calibration voltage generation circuit is electrically connected with the first input end of the comparator in the ith-stage analog-to-digital converter, so that the comparator in the ith-stage analog-to-digital converter outputs the ith target digital code according to the ith calibration voltage signal and the corresponding input analog signal.
2. The analog-to-digital conversion circuit of claim 1, further comprising: a second calibration voltage generating circuit;
the second detection output end of the (N-1) th detection circuit is electrically connected with the second calibration input end of the (N-1) th calibration circuit, so that the (N-1) th detection circuit outputs an Nth voltage detection value based on the Nth digital code output by the Nth-stage analog-to-digital converter;
a second calibration output terminal of the (N-1) th calibration circuit is electrically connected to a digital terminal of the second calibration voltage generation circuit to cause the (N-1) th calibration circuit to output an Nth voltage calibration code based on the Nth voltage detection value, such that the second calibration voltage generation circuit outputs an Nth calibration voltage signal based on the Nth voltage calibration code;
the analog end of the second calibration voltage generation circuit is electrically connected with one input end of the comparator in the Nth-stage analog-to-digital converter, so that the comparator in the Nth-stage analog-to-digital converter generates and outputs the Nth target digital code based on the Nth calibration voltage signal and the corresponding input analog signal.
3. The analog-to-digital conversion circuit according to claim 2, wherein the first calibration voltage generation circuit and the second calibration voltage generation circuit are calibration voltage generation circuits of the same structure, the calibration voltage generation circuit comprising: the circuit comprises a first switch array, M first resistors, M-1 second resistors and a third resistor; wherein M is equal to the number of bits of the voltage calibration code;
the first ends of the M-1 second resistors which are sequentially connected in series are grounded through the third resistor, and the second ends of the M-1 second resistors which are sequentially connected in series are analog ends of the calibration voltage generating circuit;
the input end of the first switch array is a digital end of the calibration voltage generating circuit, and a power supply end of the first switch array is electrically connected with a preset reference voltage; the M output ends of the first switch array are respectively and electrically connected with one ends of the M first resistors, and two ends of each of the M-1 second resistors are respectively and electrically connected with the other ends of the two first resistors.
4. The analog-to-digital conversion circuit according to claim 3, wherein the resistance value of the first resistor is twice the resistance value of the second resistor.
5. The analog-to-digital conversion circuit of claim 1, further comprising: n-1 amplifiers;
the residual output end of the ith-level analog-to-digital converter is also electrically connected with the input end of an amplifier, and the output end of the amplifier is also electrically connected with the analog end of the (i + 1) th-level analog-to-digital converter.
6. The analog-to-digital conversion circuit according to claim 5, wherein each stage of the analog-to-digital converter comprises: a comparator and a digital-to-analog converter, wherein a second input end of the comparator is electrically connected with an analog end of each stage of analog-to-digital converter, and an output end of the comparator is a digital end of each stage of analog-to-digital converter;
the output end of the comparator is also electrically connected with the digital end of the digital-to-analog converter, and the analog end of the digital-to-analog converter is also electrically connected with the analog end of each stage of analog-to-digital converter and the residual output end of each stage of analog-to-digital converter.
7. The analog-to-digital conversion circuit of claim 6, wherein the digital-to-analog converter comprises: a second switch array, a capacitor array; the input end of the second switch array is the digital end of the digital-to-analog converter;
and a plurality of output ends of the second switch array are respectively and electrically connected with one end of each capacitor in the capacitor array, and the other end of each capacitor in the capacitor array is an analog end of the digital-to-analog converter.
8. The analog-to-digital conversion circuit of claim 1, wherein each calibration circuit further has a trigger terminal; each calibration circuit is specifically configured to output a voltage calibration code according to a received voltage detection value when the trigger signal received by the trigger terminal is valid.
9. The analog-to-digital conversion circuit of claim 8, wherein each calibration circuit further has a restart end, and each calibration circuit is further configured to reset the output voltage calibration code to a preset code value when detecting that a restart signal input by the restart end is valid; and outputting a voltage calibration code according to the received voltage detection value when the restart signal is detected to be invalid and the trigger signal is detected to be valid.
10. The analog-to-digital conversion circuit of claim 8, wherein each calibration circuit further has an enable terminal, and wherein each calibration circuit is specifically configured to output a voltage calibration code according to the received voltage detection value when the restart signal is inactive, the trigger signal is active, and the enable signal input by the enable terminal is active.
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