CN112737583B - High-precision assembly line ADC and front-end calibration method - Google Patents
High-precision assembly line ADC and front-end calibration method Download PDFInfo
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Abstract
The invention discloses a high-precision pipeline ADC and a front-end calibration method, wherein a differential mode direct current input signal V is input to the pipeline ADC through an external signal source in1 Store the total number of pipelined ADCs at that timeWord output code D out1 Then fixing the input signal of the pipeline ADC to V in2 And storing the output code D of the pipeline ADC at the moment out2 D is out1 And D out2 Making a difference, obtaining the obtained delta D out With ideally the pipeline ADC input being V in1 And V in2 Time-of-flight output coded difference Δ D out_id Comparing, judging gain, and adjusting effective feedback capacitor C of MDAC module in ADC according to judgment result f_eq Thereby achieving the purpose of adjusting the gain. The process is repeated until Δ D out ＝ΔD out_id And solidifying the feedback capacitance control signal to finish foreground calibration. The invention overcomes the defects of complex traditional algorithm and low precision in the high-precision pipeline ADC, can realize algorithm logic only by storing, subtracting and comparing, has the characteristics of high efficiency, rapidness and precision, and is relatively suitable for calibrating the high-speed high-precision pipeline ADC.
Description
Technical Field
The invention belongs to the field of high-precision assembly line ADC calibration, and particularly relates to a high-precision assembly line ADC and a front-end calibration method thereof.
Background
The structure of a traditional pipeline ADC system is shown in fig. 1 (a), where an input signal is directly injected into a first pipeline sub-stage for sampling, and each pipeline sub-stage alternately performs sampling and residual amplification under the control of two-phase non-overlapping clocks. At each pipelineIn the sub-stage, when in sampling phase, the multiplying digital-to-analog converter MDAC and the auxiliary analog-to-digital converter SubADC simultaneously sample the input signal and finish sampling simultaneously, so that the condition that comparators in the multiplying digital-to-analog converter MDAC and the auxiliary analog-to-digital converter SubADC sample the same input signal point is ensured, and the auxiliary analog-to-digital converter SubADC generates a digital code D through the comparison result of the comparators i (ii) a Digital code D at residual amplified phase i Multiplied D/A converter MDAC and input signal V in And subtracting to generate a residual signal, amplifying the residual signal by a multiplying digital-to-analog converter (MDAC), sending the generated residual amplified signal to the next pipeline sub-stage to be used as an input signal of the next pipeline sub-stage, and repeating the process. A schematic diagram of a conventional multiplying digital-to-analog converter MDAC is shown in fig. 2 (a), and the input-output relationship of the conventional multiplying digital-to-analog converter MDAC is as follows:
wherein V out Is an output signal V output to the next pipeline sub-stage after residual error amplification by a multiplying digital-to-analog converter MDAC ref Is a reference voltage, C i Is a unit sampling capacitor, k is the number of bits of each pipeline sub-stage of the pipeline ADC, and stagegan is an inter-stage gain. In a low-speed low-precision pipeline ADC, a high-gain index of an operational amplifier can be realized relatively simply, so that the inter-stage gain StageGain can be approximately equal to a constant, and no gain error exists at the moment. However, as the pipeline ADC develops towards high speed and high precision, the high speed requires a large bandwidth, the high precision requires a high gain, and the high gain and high bandwidth operation is difficult to realize, so that the inter-stage gain stagegan cannot be approximated to a constant, thereby causing a gain error and affecting the performance of the pipeline ADC. In recent years, high-speed and high-precision pipeline ADCs often adopt a gain sacrificing mode to ensure that the operational amplifier bandwidth is larger, and ensure the working speed of the operational amplifier and the pipeline ADC, which cannot be considered at the same time.
Disclosure of Invention
Aiming at the defects that the gain and the speed of the operational amplifier cannot be considered in the prior art, the invention provides the high-precision pipeline ADC and the effective front-end calibration method. Two differential mode direct current voltage input signals which are output to the assembly line ADC through the external signal source are in the same section, errors caused by other factors such as capacitor mismatch can be avoided, and accuracy of a calibration algorithm is guaranteed.
The invention relates to a high-precision assembly line ADC, which adopts the technical scheme that: the device comprises a main circuit, an output code storage module, an output code subtraction module, a difference value comparison module, a feedback capacitance control module and an input voltage selection module;
the main circuit outputs a total digital output code to an output code storage module;
the output code storage module stores the total digital output codes of the main circuit;
the output code subtraction module performs subtraction operation on the total digital output codes stored by the output code storage module and outputs the obtained result to the difference comparison module;
the difference comparison module compares the output result of the output coding subtraction module with an ideal total digital output coding difference set in the difference comparison module in advance and outputs the obtained difference comparison result to the feedback capacitance control module;
the feedback capacitance control module generates a control signal according to an output result of the difference comparison module to control the feedback capacitance in the main circuit;
the input voltage selection module receives the output result of the difference comparison module, if the output result is that gain error exists, calibration is continued, and the input voltage selection module also generates enable signals of the output code storage module, the output code subtraction module, the difference comparison module and the feedback capacitance control module to control the advance of calibrationIf the comparison result shows that the gain error does not exist, the calibration is ended, and the external input signal V is used in And accessing the pipeline ADC, and enabling the pipeline ADC to work normally.
Furthermore, the main circuit comprises a plurality of pipeline sub-stages, a flash memory type ADC at the last stage, a delay in-phase module and a redundancy calibration module;
wherein, a plurality of pipeline substages are connected in sequence, the input end of the next pipeline substage is connected with the analog output end of the previous pipeline substage, and the input end of the first pipeline substage is connected with an input signal V in The analog output end of the last pipeline sub-stage is connected with the flash memory type ADC of the last stage;
the input end of the delay in-phase module is respectively connected with the digital output end of each pipeline sub-stage and the flash memory type ADC of the last stage; the input end of the redundancy calibration module is connected with the output end of the delay in-phase module;
the delay in-phase module receives the output codes of the sub-stages of each production line and the output codes of the flash memory type ADC of the last stage, and outputs the output codes to the redundancy calibration module; the redundancy calibration module calibrates the received output code and outputs a pipeline ADC total digital output code D out 。
Furthermore, each pipeline sub-stage is composed of a multiplying digital-to-analog converter MDAC module and an auxiliary analog-to-digital converter SubADC module which receive the input signal V simultaneously in And the auxiliary analog-to-digital converter SubADC module controls the multiplication digital-to-analog converter MDAC module to generate analog output and transmit the analog output to the next pipeline sub-stage, and the auxiliary analog-to-digital converter SubADC module generates digital output and transmits the digital output to the delay in-phase module.
The high-precision pipeline ADC front-end calibration method comprises the following steps:
step 1: a differential mode direct current voltage input signal V is transmitted to the assembly line ADC through an external signal source in1 Obtaining the total digital output code D of the pipeline ADC out1 The output code is stored in an output code storage module;
step 2: is transmitted to the assembly line through an external signal sourceADC differential mode DC voltage input signal V in2 Obtaining a total digital output code D of the pipeline ADC out2 The output code is stored in an output code storage module;
two direct current differential mode voltage input signals V in1 And V in2 In the same section of the transmission curve, and V in1 Greater than V in2 。
And step 3: calculating current V through manual theoretical calculation according to transmission curves of all levels and a redundancy addition calibration algorithm in1 And V in2 Ideal total digital output code D corresponding to the pipeline ADC when respectively input out1_id And D out2_id Outputting the ideal total number of digits to code D out1_id And D out2_id Make a difference, i.e. D out1_id -D out2_id ＝ΔD out_id To obtain the difference value Delta D of two total digital output codes of the pipeline ADC under the ideal condition out_id And stored in the difference comparison module;
and 4, step 4: the output coding subtraction module stores the pipeline ADC obtained in the step 1 and the step 2 in two digital outputs D in the output coding storage module out1 And D out2 By subtraction, i.e. D out1 -D out2 ＝ΔD out Obtaining a difference result Delta D out I.e. in practice the pipeline ADCs input V separately in1 And V in2 Outputting the coded difference value by total digital time;
and 5: the difference comparison module compares the delta D out And Δ D out_id For comparison, the following three cases were obtained:
if Δ D out >ΔD out_id At the moment, the actual interstage gain of the assembly line ADC is larger than the ideal interstage gain, and the feedback capacitance control module enables the effective feedback capacitance C to be larger than the ideal interstage gain according to a calculation formula of an analog domain of the actual interstage gain of the assembly line ADC f_eq Reducing the interstage gain, and then repeating the step 1, the step 2 and the step 4 until the actual interstage gain is equal to the ideal interstage gain;
if Δ D out <ΔD out_id When the pipeline ADC actually increases stage by stageThe gain is less than the ideal interstage gain, and the feedback capacitance control module enables the effective feedback capacitance C to be obtained according to the analog domain calculation formula of the actual interstage gain of the pipeline ADC f_eq Getting larger to make the interstage gain larger, and then repeating the step 1, the step 2 and the step 4 until the interstage gain is equal to the ideal interstage gain;
if Δ D out＝ ΔD out_id And at the moment, the actual interstage gain of the assembly line ADC is equal to an ideal value, the calibration is stopped, and the adjustable feedback capacitance control signal is solidified to enable the capacitance value C of the effective feedback capacitance to be equal to f_eq No longer changed.
Further, a pipelined ADC ideal interstage gain StageGain is presented herein id The calculation formula of (2) is as follows:
the pipeline ADC is used for detecting the interstage gain StageGain by a calibration circuit det The calculation formula of (2) is as follows:
because of V in1 And V in2 Is a fixed differential mode DC input signal that is set, so Δ V in Is constant, the difference Δ D between the actual total digital output codes of the pipelined ADC out Difference Δ D from the pipelined ADC theoretical total digital output encoding out_id The ratio of the magnitudes of (1) is the ratio of the inter-stage gains, i.e. if Δ D out >ΔD out_id Then, the actual interstage gain StageGain is larger than the ideal interstage gain StageGain id (ii) a If Δ D out <ΔD out_id The actual interstage gain StageGain is smaller than the ideal interstage gain StageGain id (ii) a If Δ D out ＝ΔD out_id Then, the actual interstage gain StageGain is equal to the ideal interstage gain StageGain id At this point, it is stated that the gain error has been eliminated, and the adjustable feedback capacitance control signal can be cured and endedThe foreground gain calibration method is described.
Estimating the pipeline ADC interstage gain StageGain in the analog domain ana The calculation formula is as follows:
wherein A is the open-loop gain of the operational amplifier in the pipeline ADC sampling hold circuit, C s The total sampling capacitance of the pipeline ADC sampling holding circuit in the sampling phase; beta is the closed loop feedback factor of the pipeline ADC sampling holding circuit (beta = C) f_eq /C s )，C f_eq Is an effective feedback capacitance C when the pipeline ADC sample-and-hold circuit is in an amplification phase x A capacitor C connected to the reference voltage when the pipeline ADC sample-and-hold circuit is in the amplification phase s ＝C f_eq +C x ，K＝C x /C f_eq 。
Thus, when C is decreased f_eq When the voltage is higher than the preset value, K is increased, and interstage gain is reduced; when increasing C f_eq When the time is longer, K is smaller, and the interstage gain is larger; the purpose of adjusting interstage gain is achieved, and as can be seen from the formulas (1) and (4), the calibration error mainly comes from the matching of the capacitor and the size of the open-loop gain A of the operational amplifier, and the two are not changed along with the working condition, and the calibration can be realized by a foreground calibration method.
The invention has the beneficial effects that: the invention overcomes the defects of complex traditional algorithm and low precision in a high-speed high-precision production line ADC, the algorithm logic can be realized only by storing, subtracting and comparing, and the interstage gain is obtained by taking the value of the same section as the difference, thereby avoiding the influence of other errors to a great extent; the output code storage module, the output code subtraction module, the difference value comparison module and the feedback capacitance control module can be directly integrated into a chip to be realized, and can also be realized outside the chip through an FPGA (field programmable gate array) board, so that the chip area is saved, the automatic start and automatic stop can be realized, the characteristics of high efficiency, rapidness, flexibility and accuracy are realized, and the method is relatively suitable for calibrating the high-speed high-precision assembly line ADC.
Drawings
In order that the present invention may be more readily and clearly understood, a more particular description of the invention briefly described above will be rendered by reference to specific embodiments that are illustrated in the appended drawings.
FIG. 1 (a) is an overall system architecture diagram of a conventional pipelined ADC;
FIG. 1 (b) is a diagram of the overall system architecture of the present invention;
FIG. 2 (a) is a schematic circuit diagram of a pipeline sub-stage multiplication digital-to-analog converter MDAC in a conventional pipeline ADC;
FIG. 2 (b) is a schematic diagram of the circuit structure of the pipeline sub-stage multiplication digital-to-analog converter MDAC of the present invention;
FIG. 3 is a schematic diagram of the operation of the output code storage module, the output code subtraction module, the difference comparison module, the feedback capacitance control module, and the input voltage selection module according to the present invention;
FIG. 4 (a) is an ideal transmission curve diagram of a pipeline sub-stage multiplication digital-to-analog converter MDAC;
FIG. 4 (b) is a diagram of an ideal transmission curve fitting curve of a pipeline sub-stage multiplication digital-to-analog converter MDAC;
FIG. 4 (c) is an ideal transmission curve fitting curve of a pipeline sub-stage multiplication digital-to-analog converter MDAC considering capacitance mismatch;
FIG. 5 is a flow chart of a calibration method of the present invention.
Detailed Description
As shown in fig. 1 (b), the high-precision pipeline ADC according to the present invention includes a main circuit, an output code storage module, an output code subtraction module, a difference comparison module, a feedback capacitance control module, and an input voltage selection module;
the main circuit comprises i pipeline sub-stages, a FLASH ADC (FLASH ADC) of the last stage, a delay in-phase module and a redundancy calibration module; wherein, the input end of the first pipeline substage is connected with the input signal V in The input end of the second pipeline sub-stage is connected with the analog output end of the first pipeline sub-stage, and the input signal of the second pipeline sub-stage is the output signal of the first pipeline sub-stage; third pipeline substage inputThe delay in-phase module is connected with the digital output ends of the pipeline sub-stages and the flash memory type ADC of the last stage respectively, receives the output codes of the pipeline sub-stages and the flash memory type ADC of the last stage and outputs the output codes to the redundancy calibration module; the input end of the redundancy calibration module is connected with the output end of the delay in-phase module, calibrates the received output code and outputs a digital output code D of the pipeline ADC out ；
Each sub-stage of the production line consists of a multiplying digital-to-analog converter (MDAC) module and an auxiliary analog-to-digital converter (SubADC) module which simultaneously receive an input signal V in The auxiliary analog-to-digital converter SubADC module controls the multiplication digital-to-analog converter MDAC module to generate analog output which is transmitted to the next pipeline sub-stage, and the auxiliary analog-to-digital converter SubADC module generates digital output which is transmitted to the delay in-phase module;
the output code storage module stores the total digital output codes of the main circuit;
the output code subtraction module performs subtraction operation on the total digital output codes stored by the output code storage module and outputs the obtained result to the difference value comparison module;
the difference comparison module compares the output result of the output coding subtraction module with an ideal total digital output coding difference which is set in the difference comparison module in advance, and outputs the obtained difference comparison result to the feedback capacitance control module;
the feedback capacitance control module generates a control signal according to the difference comparison result, controls a feedback capacitance in the multiplication digital-to-analog converter MDAC, and adjusts or solidifies the feedback capacitance; if the feedback capacitor is adjusted, repeating the calibration process, and if the feedback capacitor is solidified, finishing foreground calibration by the assembly line ADC and starting to normally receive the input signal;
input voltageThe selection module is controlled by the difference comparison module, receives a difference comparison result transmitted by the difference comparison module, if the comparison result shows that a gain error exists, calibration is continued, the input voltage selection module also generates enable signals of the output code storage module, the output code subtraction module, the difference comparison module and the feedback capacitance control module at the moment, the calibration is controlled to be performed, if the comparison result shows that the gain error does not exist, the calibration is finished, and an external input signal V is used in And accessing the pipeline ADC, and enabling the pipeline ADC to work normally.
According to the application, one unit capacitor of the feedback capacitors is divided into a plurality of unit capacitors according to binary weight, capacitors are added according to application conditions and are respectively controlled, and the purpose of increasing or decreasing the feedback capacitors is achieved. The circuit structure of the multiplying digital-to-analog converter MDAC is shown in fig. 2 (b).
Wherein C is x_1 ，C x_2 ，……，C x_n Is equal to C x And C is f_k ＝[(N-1)/N]*C f ，C f_k-1 ＝C f /(N*2 0 )，C f_k-2 ＝C f /(N*2 1 )，……，C f_0 ＝C f /(N*2 k-1 ) In which C is f_k-1 ，C f_k-2 ，……，C f_0 For adjustable feedback capacitance, C f The feedback capacitance of the circuit to be accessed by the traditional pipeline ADC is large.
In FIG. 2 (b), k is the binary digit of the digital code Dctr outputted by the feedback capacitance control module, and N is the adjustable feedback capacitance and the effective feedback capacitance C f_eq The proportionality coefficient can be set according to the requirement. Theoretically, the larger N is, the smaller the adjustable feedback capacitance is, the smaller the adjustment amplitude of the inter-stage gain of the circuit is, the larger k is, the better k is, the larger k is, the smaller the minimum unit of the adjustable feedback capacitance, i.e., the minimum calibration step size is, the smaller the minimum calibration step size is, the more accurate the foreground calibration algorithm is, but the smaller capacitance is difficult to accurately realize, so the compromise between the capacitance precision and the precision of the foreground calibration algorithm is required.
In FIG. 2 (b), C x_1 ，C x_2 ，……，C x_n In practice, they are controlled by three switches: respectively control C x_1 ，C x_2 ，……，C x_n One of the switches is connected with the lower electrode plate of the capacitor and the input signal V in The switch is a sampling switch which is clocked by a sampling clock
Controlling; respectively control C x_1 ，C x_2 ，……，C x_n The other switch of the switch (2) can be called as an operation switch, and one end of the operation switch is connected with a reference voltage +/-V ref One end of the input end is connected with a capacitor lower stage plate and is coded by the output code D of the Sub ADC i Control and amplification of clock with residual error
The phases are the same; finally, C x_1 ，C x_2 ，……，C x_n All connected to the same switch, here called earthing switch, one end of which is connected to C x_1 ，C x_2 ，……，C x_n The other end of the upper board is connected with a reference voltage V icm Ground switch sampled clock
The control is carried out by controlling the temperature of the air conditioner,
and
going low in phase but earlier causes the switch to open.
In FIG. 2 (b), C f_k-1 ，C f_k-2 ，……，C f_0 In fact, the three switches respectively control C f_k-1 ，C f_k-2 ，……，C f_0 One of the switches of (2) is connected to an input signal V in One end of the sampling switch is connected with a lower polar plate of a capacitor, the switch is also a sampling switch and is subjected to a sampling clock
Control, but is different from C x_1 ，C x_2 ，……，C x_n And C f_k Is that C f_k-1 ，C f_k-2 ，……，C f_0 The upper plate of the switch is connected with another switch, namely a feedback capacitance adjusting switch, and one end of the switch is connected with a terminal C f_k-1 ，C f_k-2 ，……，C f_0 The other end of the upper polar plate is connected with the upper polar plates of all other capacitors, the feedback capacitor adjusting switch is controlled by the output digital code Dctr of the feedback capacitor adjusting module, wherein the kth position of the feedback capacitor C can be adjusted f_k-1 Controlled by the kth bit of the digital code Dctr output by the feedback capacitance adjustment module, namely Dctr _ k-1, wherein the kth bit can adjust the feedback capacitance C f_k-2 Controlled by the k-1 th bit of the digital code Dctr output by the feedback capacitance adjusting module, namely Dctr _ k-2, and so on, the jth adjustable feedback capacitance C f_j Controlled by the j-1 th bit of the digital code Dctr output by the feedback capacitance adjusting module, namely Dctr _ j-1, if the feedback capacitance adjusting switch is switched off, C f_k-1 ，C f_k-2 ，……，C f_0 The upper electrode plate is suspended, does not participate in sampling of input signals, and is not connected into a loop, so that the capacitor corresponding to the disconnected feedback capacitor adjusting switch does not work in the circuit, and the feedback capacitor adjusting module adjusts the effective feedback capacitor C connected into the circuit through the feedback capacitor adjusting switch f_eq Of the value of (c); c in FIG. 2 (b) f_k-1 ，C f_k-2 ，……，C f_0 A third switch connected to the capacitor lower stage and the operational amplifier output terminal, referred to as loop switch, and receiving the residual amplified clock
And (4) controlling.
In FIG. 2 (b), the OPA is an operational amplifier, and the negative input terminals of the operational amplifier are respectively connected with the capacitors C x_1 、C x_2 、……、C x_n 、C f_k Upper polar plate, positive input end grounded GND, output end V outi And a loop switch is connected.
In the figure2 (b) in (C) f_k Controlled by three switches, two of which are the same as the sampling switch and the grounding switch and are also called the sampling switch and the grounding switch respectively, and the third switch is the same as the loop switch and is also the loop switch.
As can be seen from fig. 1 (b), the pipeline ADC main circuit will output the total digital output code to the output code storage module, and as shown in fig. 3, two storage modules are provided in the output code storage module, and the output code storage array 1 is for D out1 Storing, outputting coded memory array 1 to D out2 And storing, and outputting the stored codes to the output code subtraction module of the next stage through two output ports. The output coding storage module is provided with four main input ports, wherein CLK is a system clock; d out The port is used for directly receiving the total digital output codes of the pipeline ADC main circuit; en _ r1 and En _ r2 are enable signals to output the encoded memory array 1 and the encoded memory array 2, respectively. When En _ r1 is enabled, the storage output code storage array 1 pair D out Is stored as D out1 . If En _ r2 is enabled, then the storage output code storage array 2 is paired with D out Is stored as D out2 . En _ r1 should be at input V in1 Time enabled, en _ r2 should be at input V in2 And enabling time, ensuring that the two storage arrays store correct values, and when En _ r1 and En _ r2 are not enabled, performing latch operation on the output code storage array 1 and the output code storage array 2.
As shown in fig. 3, the output encoding subtraction module also has four main input ports, where CLK is the system clock; en _ su is an enabling port of the slave, the output coding subtraction module performs subtraction only when En _ su is enabled, and the other time is in a latch holding state, so that the influence of unnecessary values input to the rear stage on algorithm operation is avoided, and meanwhile, the rear stage can stably receive input signals; one of the other two ports is used for receiving D output by the output code storage module out1 And the other D is used for receiving the output of the output code storage module out2 When enabled and receiving the input signal, this module executes D out1 Decrease D out2 In the above-described manner, the operation of (1),and outputs the subtraction result Delta D out For use by the difference comparison module.
As shown in fig. 3, the difference comparison module has three main input ports, where CLK is the system clock; the second is an enabling end controlled by En _ cmp, when the enabling signal is not enabled, the difference comparison module executes latch operation, and when the enabling signal is enabled, the difference comparison module executes comparison operation; the other input end receives the output signal Delta D of the output coding subtraction module out The difference comparison module compares the delta D out With Δ D stored in the difference comparison module beforehand out_id Making a comparison if Δ D out Is equal to Δ D out_id If no gain error exists, D _ equ is at high level, and D _ big and D _ small are at low level; if Δ D out Greater than Δ D out_id If the inter-stage gain is larger, the D _ big is at a high level, and the D _ equ and the D _ small are at a low level; if Δ D out Less than Δ D out_id That is, if the inter-stage gain is small, D _ small is at a high level, and D _ equ and D _ big are at a low level. And three output ports of the difference comparison module respectively send D _ small, D _ equ and D _ big to the feedback capacitor control module and the input voltage selection module to control the feedback capacitor control module and the input voltage selection module.
As shown in fig. 3, the feedback capacitance control module functions like a counter, and has five main input ports, where CLK is the system clock, en _ ctr receives the enable signal, and the other three receive three input signals, D _ small, D _ equ, and D _ big. The feedback capacitance control module has k bit outputs, namely Dctr _ k-1, dctr _k-2, … … and Dctr _0, and is connected into the multiplication digital-to-analog converter MDAC to control the feedback capacitance adjusting switch. When D _ equ is at a high level and D _ big and D _ small are at a low level, no gain error exists, and the output of the feedback capacitance control module is kept unchanged at the moment; when D _ big is high level and D _ equ and D _ small are low level, the interstage gain is large, and at the moment, the effective feedback capacitor C should be reduced f_eq The feedback capacitance control module performs 1 reduction operation to reduce the original latched code by 1, corresponding to the effective feedback capacitance C f_eq Decreasing by one minimum step size; when D _ small is high level and D _ equ, D _ big are low level, the interstage gain is small, and the effective feedback power should be increasedContainer C f_eq The feedback capacitance control module adds 1 to the original latched code and adds 1 to the original code corresponding to the effective feedback capacitance C f_eq One minimum step size is increased.
As shown in fig. 3, the input voltage selection module has eight main input ports, one of which is a calibration method enable signal En _ cal, when En _ cal is not enabled, the calibration method does not work, when En _ cal is enabled, the calibration flow starts; two of the system clocks CLK, the other three of which receive three input signals D _ small, D _ equ, D _ big; the last three are connected with three input signals V in ，V in1 And V in2 。V in Is an input signal, V, to be connected when the pipeline ADC is in normal operation in1 Is the DC differential mode input voltage, V, required in step 1 in2 The required direct current differential mode input voltage in the step 2 is connected into an input voltage selection module, and the input voltage selectively connects the input voltage into a pipeline ADC main circuit, namely V inS . When the calibration method works, the input voltage selection module controls the output code storage module, the output code subtraction module, the difference value comparison module and the feedback capacitance control module respectively through enable signals En _ r1, en _ r2, en _ su, en _ cmp and En _ ctr according to the step of calibration.
FIG. 4 (a) is an ideal case of a multiplying DAC MDAC transfer curve, where- (3V) ref )/4，-(V ref )/4，(V ref )/4，(3V ref ) 4, as the discrimination points of the Sub ADC comparators, a folding curve is arranged between the discrimination points of the two comparators, corresponding to one output code D of the Sub ADC i . V of the invention in1 And V in2 Should be in the same output coding section of Sub ADC and V in1 Greater than V in2 。
Fig. 4 (b) is a transmission curve that is ideally fitted to a straight line by the multiplying dac MDAC transmission curve, and fig. 4 (c) is a transmission curve that is fitted to a straight line by the multiplying dac MDAC transmission curve in the presence of capacitance mismatch. If get V in1 And V in3 As can be seen from FIG. 4 (b), in actuality, V in1 And V in3 The corresponding total digital output code is subtracted and divided by V in1 And V in3 The transmission curve slope, i.e., the inter-stage gain, can also be determined from the difference. However, as shown in fig. 4 (c), in the case of capacitance mismatch, a linear transmission curve is fitted, and each comparator determines that an Error _ cap exists between segments, which causes an Error step Error _ cap to be included in the obtained total digital output coding difference, so that slope calculation is erroneous. At the same time, V in1 Is greater than V in2 This is to prevent negative results, facilitate calculation, and V in1 And V in2 The difference should not be too small, and quantization errors are easily caused by too small a difference.
The following describes the working flow of the high-precision pipeline ADC front-end calibration method in detail with reference to fig. 5:
and accessing the pipeline ADC into a test environment, enabling En _ cal and starting a calibration process.
In a first step, an input voltage selection module selects V in1 The input flow line ADC main circuit, output code storage module, output code subtraction module, difference comparison module, feedback capacitance control module all do not enable this moment.
Second, after several cycles, the pipeline ADC completes quantization, and outputs total digital output code D out1 To the output code storage module, the input voltage selection module enables En _ r1 at the moment, and the output code storage array 1 in the output code storage module outputs a code D to the total number of the pipeline ADC out1 Storing is performed, and other signals En _ r2, en _ su, en _ cmp, en _ ctr are not enabled at this time.
Thirdly, the input voltage selection module selects V in2 The input flow line ADC main circuit, output code storage module, output code subtraction module, difference comparison module, feedback capacitance control module all do not enable this moment.
Fourthly, after a plurality of periods, the pipeline ADC completes the quantization and outputs the total digital outputOutput code D out2 To the output code storage module, the input voltage selection module enables En _ r2 at the moment, and the output code storage array 2 in the output code storage module outputs a code D to the total number of the pipeline ADC out2 Storing is performed, and other signals En _ r1, en _ su, en _ cmp, en _ ctr are not enabled at this time.
Fifthly, the input voltage selection module selects to enable En _ su, the output code subtraction module works, and two total digital output codes D latched by the output code storage module are output out1 And D out2 Performing subtraction operation and obtaining difference result delta D out And latching, wherein other signals En _ r1, en _ r2, en _ cmp and En _ ctr are not enabled at the moment.
Sixthly, the input voltage selection module selects En _ cmp to be enabled, the difference value comparison module works, the output coding subtraction module is latched and the input subtraction result delta D is input out Difference result Delta D from the ideal case out_id Making a comparison if Δ D out Is equal to Δ D out_id If there is no gain error, D _ equ is high level, and D _ big and D _ small are low level; if Δ D out Greater than Δ D out_id If the inter-stage gain is larger, the D _ big is at a high level, and the D _ equ and the D _ small are at a low level; if Δ D out Less than Δ D out_id That is, if the inter-stage gain is small, D _ small is at a high level, and D _ equ and D _ big are at a low level. At this time, none of the other signals En _ r1, en _ r2, en _ su, en _ ctr is enabled.
And seventhly, enabling the En _ ctr by selecting the input voltage selection module, and enabling the feedback capacitance control module to work, wherein the working process is described by taking k =3 as an example. If k =3, the feedback capacitance control module outputs the three-bit codes Dctr _2, dctr _1, dctr _0, i.e., dctr. In the initial state, dctr =100, the output signals are Dctr _2=1, dctr \u1 =0, dctr \u0 =0, the feedback capacitance switch is turned on at high level, and the effective feedback capacitance C connected into the circuit at this time f_eq ＝C f_3 +C f_2 ＝[(N-1)/N]*C f +C f /(N*2 0 )＝C f The feedback capacitance of the circuit is the same as that of the traditional pipeline ADC, and other signals En _ r1, en _ r2, en _ cmp and En _ su do not cause the circuit to be switched inCan be used.
From the equation (4), if there is no gain error, the inter-stage gain is approximately equal to a constant, i.e., C s /C f However, due to uncertainty in random and systematic errors, the actual inter-stage gain may be greater than the constant C s /C f May be smaller than the constant C s /C f By comparing Δ D out Delta D of out_id The magnitude relationship determines the magnitude relationship of the inter-stage gains, which is described above and will not be described herein.
Therefore, if the signal input by the difference comparison module is D _ equ is high level and D _ big and D _ small are low level, the actual interstage gain is equal to the ideal interstage gain, and the calibration is finished; if D _ big is high level and D _ equ and D _ small are low level, the inter-stage gain is larger, the feedback capacitance control module performs a subtraction operation on Dctr to reduce 1, and finally outputs codes Dctr =011, i.e. Dctr _2=0, dctr \u1 =1 and Dctr \u0 =1, and at this time, the effective feedback capacitance C in the access circuit is switched in f_eq ＝C f_3 +C f_1 +C f_0 ＝[(N-1)/N]*C f +C f /(N*2 1 )+C f /(N*2 2 )＝[(4N-1]/4N]C f Slightly smaller than C f Mixing C with f_eq Reducing; if D _ small is high level and D _ equ and D _ big are low level, the inter-stage gain is small, the feedback capacitance control module adds 1 to Dctr, and finally the code Dctr =101 is output, namely Dctr _2=1, dctr \u1 =0 and Dctr \u0 =1, and at this time, the effective feedback capacitance C in the access circuit is accessed f_eq ＝C f_3 +C f_2 +C f_0 ＝[(N-1)/N]*C f +C f /(N*2 0 )+C f /(N*2 2 )＝[(4N+1]/4N]C f Slightly greater than C f Mixing C with f_eq And (5) adjusting the size to be larger.
Eighthly, the input voltage selection module selects to disable En _ ctr, so that the output code of the feedback capacitor control module is latched, and in the first step, detection is carried out again until D _ equ is high level and D _ big and D _ small are low level, calibration is finished, the input voltage selection module enables En _ r1, en _ r2, en _ cmp, en _ su and En _ ctr to be disabled, all signals are latched, and all signals are latchedTime C f_eq Is no longer changed, indicating that the calibration is complete.
In summary, the invention can be applied to each pipeline sub-stage of the pipeline ADC, performs gain calibration on each sub-stage of the pipeline ADC, improves the disadvantages of complex algorithm and low precision in the high-speed high-precision pipeline ADC, can realize algorithm logic only by storing, subtracting and comparing, and obtains inter-stage gain by making difference between values of the same section, thereby avoiding the influence of other errors to a great extent.
The above description is only a preferred embodiment of the present invention, and is not intended to limit the present invention, and all equivalent variations made by using the contents of the present specification and the drawings are within the protection scope of the present invention.
Claims (8)
1. A high-precision assembly line ADC is characterized by comprising a main circuit, an output code storage module, an output code subtraction module, a difference value comparison module, a feedback capacitance control module and an input voltage selection module;
the main circuit outputs a total digital output code to an output code storage module;
the output code storage module stores the total digital output codes of the main circuit;
the output code subtraction module performs subtraction operation on the total digital output codes stored by the output code storage module and outputs the obtained result to the difference value comparison module;
the difference comparison module compares the output result of the output coding subtraction module with an ideal total digital output coding difference set in the difference comparison module in advance and outputs the obtained difference comparison result to the feedback capacitance control module;
the feedback capacitance control module generates a control signal according to an output result of the difference comparison module to control the feedback capacitance in the main circuit;
the input voltage selection module receives the output result of the difference comparison module and generates enable signals of the output code storage module, the output code subtraction module, the difference comparison module and the feedback capacitance control module according to the output result so as to control the calibration or enable the pipeline ADC to work normally.
2. The high-precision pipelined ADC of claim 1, wherein the main circuit comprises a plurality of pipeline sub-stages, a last-stage flash ADC, a delay in-phase module, and a redundancy calibration module;
wherein, a plurality of pipeline substages are connected in sequence, the input end of the next pipeline substage is connected with the analog output end of the previous pipeline substage, and the input end of the first pipeline substage is connected with an input signal V in The analog output end of the last pipeline sub-stage is connected with the flash memory type ADC of the last stage;
the input end of the delay in-phase module is respectively connected with the digital output end of each pipeline sub-stage and the flash memory type ADC of the last stage; the input end of the redundancy calibration module is connected with the output end of the delay in-phase module;
the delay in-phase module receives the output codes of the sub-stages of each production line and the output codes of the flash memory type ADC of the last stage, and outputs the output codes to the redundancy calibration module; the redundancy calibration module calibrates the received output code and outputs a pipeline ADC total digital output code D out 。
3. A high precision pipeline ADC according to claim 2 wherein each pipeline sub-stage is formed by a multiplying digital to analog converter MDAC module and an auxiliary analog to digital converter subcodc module which simultaneously receive the input signal V in And the auxiliary analog-to-digital converter SubADC module controls the multiplication digital-to-analog converter MDAC module to generate analog output which is transmitted to the next pipeline sub-stage, and the auxiliary analog-to-digital converter SubADC module generates digital output which is transmitted to the delay in-phase module.
4. A method for calibrating a high precision pipelined ADC front-end according to any one of claims 1 to 3, comprising the steps of:
step 1: a differential mode direct current voltage input signal V is transmitted to the assembly line ADC through an external signal source in1 Obtaining a total digital output code D of the pipeline ADC out1 The output code is stored in an output code storage module;
and 2, step: a differential mode direct current voltage input signal V is transmitted to the assembly line ADC through an external signal source in2 Obtaining the total digital output code D of the pipeline ADC out2 The output code is stored in an output code storage module;
and step 3: according to transmission curves of all levels and a redundancy addition calibration algorithm, calculating the current V through a manual theory in1 And V in2 Ideal total digital output code D corresponding to the pipeline ADC when respectively input out1_id And D out2_id Outputting the ideal total number of digits to code D out1_id And D out2_id Make a difference, i.e. D out1_id -D out2_id ＝ΔD out_id To obtain the difference value Delta D of two total digital output codes of the pipeline ADC under the ideal condition out_id And stored in the difference comparison module;
and 4, step 4: the output coding subtraction module stores the pipeline ADC obtained in the step 1 and the step 2 in two digital outputs D in the output coding storage module out1 And D out2 By subtraction, i.e. D out1 -D out2 ＝ΔD out Obtaining a difference result Delta D out I.e. in practice the pipeline ADCs input V separately in1 And V in2 Outputting the coded difference value by total digital time;
and 5: the difference comparison module compares the delta D out And Δ D out_id For comparison, the following three cases were obtained:
if Δ D out >ΔD out_id At the moment, the actual interstage gain of the pipeline ADC is larger than the ideal interstage gain, and the feedback capacitance control module is used for controlling the actual interstage gain of the pipeline ADC according to an analog domain calculation formula of the actual interstage gain of the pipeline ADCWill make the effective feedback capacitance C f_eq Decrease, C f_eq Reducing interstage gain for an effective feedback capacitor of the pipeline ADC sample-and-hold circuit in an amplification phase, and then repeating the step 1, the step 2 and the step 4 until the actual interstage gain is equal to the ideal interstage gain;
if Δ D out <ΔD out_id At the moment, the actual interstage gain of the assembly line ADC is smaller than the ideal interstage gain, and the feedback capacitance control module enables the effective feedback capacitance C to be in accordance with a calculation formula of an analog domain of the actual interstage gain of the assembly line ADC f_eq Getting larger to make the interstage gain larger, and then repeating the step 1, the step 2 and the step 4 until the interstage gain is equal to the ideal interstage gain;
if Δ D out＝ ΔD out_id And at the moment, the actual interstage gain of the assembly line ADC is equal to an ideal value, the calibration is stopped, and the control signal of the adjustable feedback capacitor is solidified to enable the effective feedback capacitance value C f_eq No longer changed.
5. The method of claim 4, wherein the two DC differential mode voltage input signals V are used as the front-end calibration of the pipelined ADC in1 And V in2 In the same section of the transmission curve, and V in1 Greater than V in2 。
6. The method as claimed in claim 4, wherein the ideal interstage gain of the pipeline ADC is StageGain id Is calculated by the formula
7. The method as claimed in claim 4, wherein the inter-stage gain StageGain detected by the calibration circuit is used for calibrating the front end of the pipeline ADC det The calculation formula of (2) is as follows:
8. the method as claimed in claim 4, wherein the high-precision pipeline ADC front-end calibration method is characterized in that the pipeline ADC interstage gain StageGain is estimated in an analog domain ana The calculation formula is as follows:
wherein A is the open-loop gain of the operational amplifier in the pipeline ADC sampling and holding circuit, and C s The total sampling capacitance of the pipeline ADC sampling and holding circuit at a sampling phase is obtained; beta is a closed loop feedback factor of the pipeline ADC sampling and holding circuit, namely beta = C f_eq /C s ，C x A capacitor C connected to the reference voltage when the pipeline ADC sample-and-hold circuit is in the amplification phase s ＝C f_eq +C x ，K＝C x /C f_eq 。
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| CN107359878A (en) * | 2017-08-17 | 2017-11-17 | 电子科技大学 | A kind of front-end calibration method of the pipeline ADC based on minimum quantization error |
| CN110504967A (en) * | 2019-08-30 | 2019-11-26 | 电子科技大学 | A kind of interstage gain mismatch repair method of pipeline ADC |
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| CN107359878A (en) * | 2017-08-17 | 2017-11-17 | 电子科技大学 | A kind of front-end calibration method of the pipeline ADC based on minimum quantization error |
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