CN112737583B - A high-precision pipeline ADC and front-end calibration method - Google Patents

Abstract

The invention discloses a high-precision pipeline ADC and a front-end calibration method, wherein a differential mode direct current input signal V is input to the pipeline ADC through an external signal source _in1 Store the total number of pipelined ADCs at that timeWord output code D _out1 Then fixing the input signal of the pipeline ADC to V _in2 And storing the output code D of the pipeline ADC at the moment _out2 D is _out1 And D _out2 Making a difference, obtaining the obtained delta D _out With ideally the pipeline ADC input being V _in1 And V _in2 Time-of-flight output coded difference Δ D _{out_id} Comparing, judging gain, and adjusting effective feedback capacitor C of MDAC module in ADC according to judgment result _{f_eq} Thereby achieving the purpose of adjusting the gain. The process is repeated until Δ D _out ＝ΔD _{out_id} And solidifying the feedback capacitance control signal to finish foreground calibration. The invention overcomes the defects of complex traditional algorithm and low precision in the high-precision pipeline ADC, can realize algorithm logic only by storing, subtracting and comparing, has the characteristics of high efficiency, rapidness and precision, and is relatively suitable for calibrating the high-speed high-precision pipeline ADC.

Description

A high-precision pipeline ADC and front-end calibration method

technical field

The invention belongs to the field of high-precision pipeline ADC calibration, in particular to a high-precision pipeline ADC and a front-end calibration method thereof.

Background technique

The structure of the traditional pipeline ADC system is shown in Figure 1(a). The input signal is directly injected into the first pipeline sub-stage for sampling, and each pipeline sub-stage performs sampling and residual amplification alternately under the control of two-phase non-overlapping clocks. Inside each pipeline sub-stage, when sampling the phase, the multiplying digital-to-analog converter MDAC and the auxiliary analog-to-digital converter SubADC simultaneously sample the input signal and end the sampling at the same time, ensuring that the multiplying digital-to-analog converter MDAC and the auxiliary analog-to-digital converter SubADC The comparator in the sample is sampled to the same input signal point, and the auxiliary analog-to-digital converter SubADC generates a digital code D _i through the comparison result of the comparator; when the residual amplifies the phase, the digital code D _i passes through the multiplying digital-to-analog converter MDAC and the input signal. The residual signal is generated by the subtraction of V _in , and the residual signal is amplified by the multiplying digital-to-analog converter MDAC. The generated residual amplified signal is sent to the next pipeline sub-stage as the input signal of the next pipeline sub-stage. Repeat this process. process. The schematic diagram of the traditional multiplying digital-to-analog converter MDAC is shown in Figure 2(a). The input-output relationship of the traditional multiplying digital-to-analog converter MDAC is as follows:

Wherein V _out is the output signal output to the next pipeline sub-stage after residual amplification by the multiplying digital-to-analog converter MDAC, V _ref is the reference voltage, C _i is the unit sampling capacitor, k is the pipeline ADC per pipeline sub-stage The number of bits, StageGain is the gain between stages. In the low-speed and low-precision pipeline ADC, the high-gain index of the op amp can be easily realized, so that the inter-stage gain StageGain can be approximately equal to a constant, and it can be considered that there is no gain error at this time. However, with the development of pipeline ADC in the direction of high speed and high precision, high speed requires the op amp to have a large bandwidth, and high precision requires the op amp to have high gain. The gain StageGain cannot be approximated as a constant, resulting in gain errors that affect pipeline ADC performance. In recent years, high-speed and high-precision pipeline ADCs often use the method of sacrificing gain to ensure a larger operational amplifier bandwidth and ensure the operating speed of operational amplifiers and pipeline ADCs. The two cannot be balanced.

SUMMARY OF THE INVENTION

In view of the above-mentioned deficiencies in the prior art that the gain of the operational amplifier and the speed of the operational amplifier cannot be taken into account, the present invention provides a high-precision pipeline ADC and an effective front-end calibration method, which is used to calibrate the inter-stage gain of each pipeline sub-stage of the pipeline. , the total digital output code of the ADC needs to be subtracted, and the connection mode of the analog circuit inside the pipeline ADC needs to be changed according to the calculation result, so as to achieve the purpose of gain calibration. The two differential-mode DC voltage input signals input to the pipeline ADC by an external signal source are in the same section, which can avoid errors caused by other factors such as capacitance mismatch, and ensure the accuracy of the calibration algorithm.

The high-precision pipeline ADC of the present invention adopts the technical scheme as follows: comprising a main circuit, an output coding storage module, an output coding subtraction module, a difference comparison module, a feedback capacitance control module, and an input voltage selection module;

Wherein, the main body circuit outputs the total digital output code to the output code storage module;

The output code storage module stores the total digital output code of the main circuit;

The output code subtraction module performs a subtraction operation on the total digital output code stored in the output code storage module, and outputs the obtained result to the difference comparison module;

The difference comparison module compares the output result of the output code subtraction module with the ideal total digital output code difference set in the difference comparison module in advance, and outputs the obtained difference comparison result to the feedback capacitor control module;

The feedback capacitance control module generates a control signal according to the output result of the difference comparison module, and controls the feedback capacitance in the main circuit;

The input voltage selection module receives the output result of the difference comparison module. If the output result is a gain error, it will continue to calibrate. At this time, the input voltage selection module will also generate an output code storage module, an output code subtraction module, a difference comparison module, The enable signal of the feedback capacitor control module is used to control the calibration. If the comparison result is that the gain error does not exist, the calibration is ended, and the external input signal V _in is connected to the pipeline ADC, and the pipeline ADC starts to work normally.

Further, the main circuit includes several pipeline sub-stages, a flash-memory ADC at the last stage, a delayed in-phase module, and a redundant calibration module;

Among them, several pipeline sub-stages are connected in sequence, the input terminal of the latter pipeline sub-stage is connected to the analog output terminal of the previous pipeline sub-stage, the input terminal of the first pipeline sub-stage is connected to the input signal V _in , and the analog output terminal of the last pipeline sub-stage Connect to the flash ADC of the last stage;

The input end of the delay in-phase module is respectively connected to the digital output end of each pipeline sub-stage and the flash-type ADC of the last stage; the input end of the redundancy calibration module is connected to the output end of the delay in-phase module;

The delay in-phase module receives the output code of each pipeline sub-stage and the output code of the flash ADC of the last stage, and outputs it to the redundancy calibration module; the redundancy calibration module calibrates the received output code and outputs the total number of the pipeline ADC Output encoding D _out .

Further, each pipeline sub-stage is composed of a multiplying digital-to-analog converter MDAC module and an auxiliary analog-to-digital converter SubADC module, both of which receive the input signal V _in at the same time, and the auxiliary analog-to-digital converter SubADC module controls the multiplying digital-to-analog conversion. The MDAC module generates an analog output for transmission to the next pipeline sub-stage, and the auxiliary analog-to-digital converter SubADC module generates a digital output for transmission to the delayed in-phase module.

For the above-mentioned high-precision pipeline ADC front-end calibration method, the following steps are included:

Step 1: input a differential mode DC voltage input signal V _in1 to the pipeline ADC through an external signal source, obtain the total digital output code D _out1 of the pipeline ADC, and store it in the output code storage module;

Step 2: inputting a differential mode DC voltage input signal V _in2 to the pipeline ADC through an external signal source to obtain the total digital output code D _out2 of the pipeline ADC, and store it in the output code storage module;

The two DC differential mode voltage input signals V _in1 and V _in2 are in the same segment of the transfer curve, and V _in1 is greater than V _in2 .

Step 3: Calculate the ideal total digital output codes D _{out1_id} and D _{out2_id} when V _in1 and V _in2 are respectively input to the pipeline ADC through manual theoretical calculation according to the transmission curves of all levels and the redundancy addition calibration algorithm, and set the The difference between the ideal total digital output codes D _{out1_id} and D _{out2_id} , that is, D _{out1_id} -D _{out2_id} =ΔD _{out_id} , obtains the difference ΔD _{out_id} between the two total digital output codes of the pipeline ADC under ideal conditions, and stores it in the difference value in the compare module;

Step 4: The output coding subtraction module performs a subtraction operation on the two digital outputs D _out1 and D _out2 stored in the output coding storage module by the pipeline ADC obtained in steps 1 and 2, that is, D _out1 -D _out2 =ΔD _out , The difference result ΔD _out is obtained, that is, the total digital output code difference value when the pipeline ADC inputs V _in1 and V _in2 respectively under actual conditions;

Step 5: The difference comparison module compares ΔD _out and ΔD _{out_id} , and obtains the following three cases:

If ΔD _out >ΔD _{out_id} , the actual inter-stage gain of the pipeline ADC is greater than the ideal inter-stage gain, and according to the analog domain calculation formula of the actual inter-stage gain of the pipeline ADC, the feedback capacitance control module will make the effective feedback capacitance C _{f_eq} smaller , make the inter-stage gain smaller, and then repeat steps 1, 2 and 4 until the actual inter-stage gain is equal to the ideal inter-stage gain;

If ΔD _out <ΔD _{out_id} , the actual inter-stage gain of the pipeline ADC is smaller than the ideal inter-stage gain, and according to the analog domain calculation formula of the actual inter-stage gain of the pipeline ADC, the feedback capacitance control module will increase the effective feedback capacitance C _{f_eq} , make the inter-stage gain larger, and then repeat steps 1, 2 and 4 until the inter-stage gain is equal to the ideal inter-stage gain;

If ΔD _{out =} ΔD _{out_id} , the actual inter-stage gain of the pipeline ADC is equal to the ideal value, the calibration is stopped, and the adjustable feedback capacitor control signal is cured, so that the effective feedback capacitor value C _{f_eq} does not change.

Further, the calculation formula of the ideal inter-stage gain StageGain _id of the pipeline ADC is proposed here:

The calculation formula of the inter-stage gain StageGain _det detected by the calibration circuit of the pipeline ADC is:

Because V _in1 and V _in2 are set fixed differential mode DC input signals, ΔV _in is a constant, so the difference ΔD _out between the actual total digital output codes of the pipeline ADC and the theoretical total digital output of the pipeline ADC The ratio of the difference between codes ΔD _{out_id} is the ratio of the inter-stage gain, that is, if ΔD _out >ΔD _{out_id} , it means that the actual inter-stage gain StageGain is greater than the ideal inter-stage gain StageGain _id ; if ΔD _out <ΔD _{out_id} , it means that The actual inter-stage gain StageGain is less than the ideal inter-stage gain StageGain _id ; if ΔD _out = ΔD _{out_id} , it means that the actual inter-stage gain StageGain is equal to the ideal inter-stage gain StageGain _id , which means that the gain error has been eliminated, and the adjustable feedback capacitor can be cured. control signal and end the foreground gain calibration method.

The calculation formula of StageGain _ana to estimate the inter-stage gain of the pipeline ADC in the analog domain is:

Wherein A is the open-loop gain of the operational amplifier in the sampling and holding circuit of the pipeline ADC, C _s is the total sampling capacitance when the sampling and holding circuit of the pipeline ADC is in the sampling phase; β is the closed-loop feedback factor of the sampling and holding circuit of the pipeline ADC (β =C _{f_eq} /C _s ), C _{f_eq} is the effective feedback capacitance when the pipeline ADC sample and hold circuit is in the amplification phase, C _x is the capacitance connected to the reference voltage when the pipeline ADC sample and hold circuit is in the amplification phase, C _s = C _{f_eq} +C _x , K=C _x /C _{f_eq} .

It can be seen from this that when C _{f_eq} is reduced, K becomes larger and the inter-stage gain decreases; when C _{f_eq} is increased, K becomes smaller and the inter-stage gain becomes larger; the purpose of adjusting the inter-stage gain is achieved, and by formula It can be seen from equation (1) and equation (4) that the calibration error mainly comes from the matching of capacitors and the size of the open-loop gain A of the op amp, both of which do not change with the working conditions, and can be calibrated by the method of foreground calibration.

The beneficial effects of the present invention are as follows: the present invention improves the shortcomings of complex and low-precision traditional algorithms in high-speed and high-precision pipeline ADCs, and only needs to store, subtract, add and compare to realize the algorithm logic, and the algorithm logic can be realized by taking values in the same section. The inter-stage gain is obtained in a poor way, which can largely avoid the influence of other errors; the output coding storage module, the output coding subtraction module, the difference comparison module, and the feedback capacitance control module of the present invention can be directly integrated into the chip for realization, and also It can be implemented off-chip through an FPGA board, saving chip area, and can automatically start and stop automatically. It is efficient, fast, flexible and accurate, and is more suitable for high-speed and high-precision pipeline ADC calibration.

Description of drawings

In order to make the content of the present invention easier to understand clearly, the present invention will be described in further detail below according to specific embodiments and in conjunction with the accompanying drawings.

Figure 1(a) is the overall system structure diagram of the traditional pipeline ADC;

Fig. 1 (b) is the overall system structure diagram of the present invention;

Figure 2 (a) is a schematic diagram of the circuit structure of the pipeline sub-stage multiplying digital-to-analog converter MDAC in the traditional pipeline ADC;

Fig. 2 (b) is the circuit structure schematic diagram of pipeline sub-stage multiplying digital-to-analog converter MDAC in the present invention;

3 is a schematic diagram of the work flow of an output code storage module, an output code subtraction module, a difference comparison module, a feedback capacitance control module and an input voltage selection module in the present invention;

Figure 4(a) is a schematic diagram of the ideal transfer curve of the pipeline sub-stage multiplying digital-to-analog converter MDAC;

Figure 4(b) is a schematic diagram of the fitting curve of the ideal transfer curve of the pipeline sub-stage multiplying digital-to-analog converter MDAC;

Figure 4(c) is a fitting curve of the ideal transfer curve of the pipeline sub-stage multiplying digital-to-analog converter MDAC considering capacitance mismatch;

FIG. 5 is a flow chart of the calibration method of the present invention.

Detailed ways

As shown in Figure 1(b), a high-precision pipeline ADC according to the present invention includes a main circuit, an output code storage module, an output code subtraction module, a difference comparison module, a feedback capacitor control module, and an input voltage selection module. ;

The main circuit includes i pipeline sub-stages, a flash ADC (FLASH ADC) at the last stage, a delay in-phase module, and a redundant calibration module; wherein, the input terminal of the first pipeline sub-stage is connected to the input signal V _in , and the first pipeline sub-stage is connected to the input signal V in . The input terminal of the second pipeline sub-stage is connected to the analog output terminal of the first pipeline sub-stage, the input signal of the second pipeline sub-stage is the output signal of the first pipeline sub-stage; the input terminal of the third pipeline sub-stage is connected to the analog output terminal of the second pipeline sub-stage, The input signal of the third pipeline sub-stage is the output signal of the second pipeline sub-stage, and so on until the i-th sub-stage. The input terminals of the MCU are respectively connected to the digital output terminals of each pipeline sub-stage and the flash-type ADC of the last stage, receive the output code of each pipeline sub-stage and the output code of the flash-type ADC of the last stage, and output to the redundancy calibration module; The input end of the redundant calibration module is connected to the output end of the delay in-phase module, the received output code is calibrated and the total digital output code D _out of the pipeline ADC is output;

Each of the pipeline sub-stages is composed of a multiplying digital-to-analog converter MDAC module and an auxiliary analog-to-digital converter SubADC module, both of which receive the input signal V _in at the same time, and the auxiliary analog-to-digital converter SubADC module controls the multiplying digital-to-analog converter. The MDAC module generates an analog output and transmits it to the next pipeline sub-stage, and the auxiliary analog-to-digital converter SubADC module generates a digital output and transmits it to the delay in-phase module;

The output code storage module stores the total digital output code of the main circuit;

The output code subtraction module performs a subtraction operation on the total digital output code stored in the output code storage module, and outputs the obtained result to the difference comparison module;

The difference comparison module compares the output result of the output code subtraction module with the ideal total digital output code difference set in the difference comparison module in advance, and outputs the obtained difference comparison result to the feedback capacitor control module;

The feedback capacitance control module generates a control signal according to the difference comparison result, controls the feedback capacitance in the multiplying digital-to-analog converter MDAC, and adjusts or solidifies the feedback capacitance; if the feedback capacitance is adjusted, repeat the calibration process. After the feedback capacitor is cured, the pipeline ADC ends the foreground calibration and starts to receive the input signal normally;

The input voltage selection module is controlled by the difference comparison module, and receives the difference comparison result transmitted by the difference comparison module. If the comparison result is that there is a gain error, the calibration is continued. At this time, the input voltage selection module will also generate the output code storage module, Output the enable signal of the coding subtraction module, the difference comparison module, and the feedback capacitance control module to control the calibration. If the comparison result is that the gain error does not exist, the calibration is ended, and the external input signal V _in is connected to the pipeline ADC, The pipelined ADC starts to work normally.

In this application, one of the unit capacitors of the feedback capacitor is divided into several units according to the binary weight, and the capacitors are added according to the application situation, and they are controlled separately to achieve the purpose of increasing or decreasing the feedback capacitor. The circuit structure of the multiplying digital-to-analog converter MDAC is shown in FIG. 2(b).

Wherein the sum of capacitance values of C _{x_1} , C _{x_2} , ..., C _{x_n} is equal to C _x , and C _{f_k} =[(N-1)/N]*C _f , C _{f_k-1} =C _f /(N*2 ⁰ ), C _{f_k-2} =C _f /(N*2 ¹ ),..., C _{f_0} =C _f /(N*2 ^k-1 ), where C _{f_k-1} , C _{f_k-2} ,..., C _{f_0} is the adjustable feedback capacitance, and C _f is the size of the feedback capacitance that the traditional pipeline ADC should be connected to the circuit.

In Figure 2(b), k is the binary digit of the digital code Dctr output by the feedback capacitance control module, and N is the proportional coefficient between the adjustable feedback capacitance and the effective feedback capacitance C _{f_eq} , which can be set according to requirements. Theoretically speaking, the larger the N is, the smaller the adjustable feedback capacitance will be, and the adjustment range of the gain between the circuit stages will be smaller, and the larger the value of k, the better. The larger the value of k, the smaller the adjustable feedback capacitance. The unit, that is, the smaller the minimum calibration step size, the smaller the minimum calibration step size, the more accurate the foreground calibration algorithm is, but the smaller capacitance is more difficult to achieve accurately, so it is necessary to make a compromise between the capacitance accuracy and the accuracy of the foreground calibration algorithm .

控制；分别控制C_{x_1}，C_{x_2}，……，C_{x_n}的开关其中的另一个开关可称为运算开关，运算开关一端接参考电压±V_ref，一端接电容下级板，受Sub ADC的输出编码D_i控制，且与残差放大时钟

同相；最后，C_{x_1}，C_{x_2}，……，C_{x_n}的上极板都接到同一个开关上，这个开关在这里称为接地开关，接地开关的一端接C_{x_1}，C_{x_2}，……，C_{x_n}的上级板，另一端接参考电压V_icm，接地开关受采样时钟

控制，

与

同相但更早进入低电平使开关断开。In Figure 2(b), C _{x_1} , C _{x_2} , ..., C _{x_n} are actually controlled by three switches: one end of the switches that control C _{x_1} , C _{x_2} , ..., C _{x_n} respectively It is connected to the lower plate of the capacitor, and one end is connected to the input signal V _in . This switch is the sampling switch, and the sampling switch is affected by the sampling clock.

Control; control the switches of C _{x_1} , C _{x_2} , ..., C _{x_n} respectively. Another switch among them can be called an operation switch. One end of the operation switch is connected to the reference voltage ±V _ref , and the other end is connected to the lower-level board of the capacitor, and is encoded by the output of the Sub ADC. D _i control, and with the residual amplification clock

In the same phase; finally, the upper plates of C _{x_1} , C _{x_2} , ..., C _{x_n} are all connected to the same switch, this switch is called the grounding switch here, and one end of the grounding switch is connected to C _{x_1} , C _{x_2} , ..., The upper-level board of C _{x_n} , the other end is connected to the reference voltage V _icm , the grounding switch is subject to the sampling clock

control,

and

In-phase but going low earlier turns the switch off.

控制，但不同于C_{x_1}，C_{x_2}，……，C_{x_n}和C_{f_k}的是，C_{f_k-1}，C_{f_k-2}，……，C_{f_0}的上极板还要接了另一个开关，即反馈电容调整开关，这个开关一端接C_{f_k-1}，C_{f_k-2}，……，C_{f_0}的上极板，另一端接到其他所有电容的上极板，反馈电容调整开关受到反馈电容调整模块输出输出数字码Dctr的控制，其中第k位可调反馈电容C_{f_k-1}受反馈电容调整模块输出数字码Dctr的第k位控制，即Dctr_k-1，其中第k位可调反馈电容C_{f_k-2}受反馈电容调整模块输出数字码Dctr的第k-1位控制，即Dctr_k-2，以此类推，第j个可调反馈电容C_{f_j}受反馈电容调整模块输出数字码Dctr的第j-1位控制，即Dctr_j-1，若反馈电容调整开关断开，则C_{f_k-1}，C_{f_k-2}，……，C_{f_0}的上极板悬空，不参与输入信号的采样，也不接入环路，所以此时断开的反馈电容调整开关所对应的电容在电路中是不起作用的，反馈电容调整模块就是通过反馈电容调整开关来调整接入电路的有效反馈电容C_{f_eq}的值的；图2(b)中C_{f_k-1}，C_{f_k-2}，……，C_{f_0}所接的第三个开关，一端接到电容下级板，一端接到运放输出端，这个开关在这里称为环路开关，受到残差放大时钟

的控制。In Fig. 2(b), C _{f_k-1} , C _{f_k-2} , ..., C _{f_0} are actually controlled by three switches, respectively controlling C _{f_k-1} , C _{f_k-2} , ..., C _{f_0} One of the switches is connected to the input signal V _in , and the other end is connected to the lower plate of the capacitor. This switch is also a sampling switch and is affected by the sampling clock.

Control, but different from C _{x_1} , C _{x_2} , ..., C _{x_n} and C _{f_k} is that the upper plate of C _{f_k-1} , C _{f_k-2} , ..., C _{f_0} is connected to another switch, namely Feedback capacitor adjustment switch, one end of this switch is connected to the upper plate of C _{f_k-1} , C _{f_k-2} , ..., C _{f_0} , and the other end is connected to the upper plate of all other capacitors. The feedback capacitance adjustment switch is subject to the feedback capacitance adjustment module The control of the output digital code Dctr, in which the k-th adjustable feedback capacitor C _{f_k-1} is controlled by the k-th bit of the output digital code Dctr of the feedback capacitance adjustment module, namely Dctr_k-1, where the k-th adjustable feedback capacitor C _{f_k -2} is controlled by the k-1 bit of the digital code Dctr output by the feedback capacitance adjustment module, namely Dctr_k-2, and so on, the jth adjustable feedback capacitance C _{f_j} is controlled by the jth of the digital code Dctr output by the feedback capacitance adjustment module 1-bit control, namely Dctr_j-1, if the feedback capacitance adjustment switch is turned off, then the upper plate of C _{f_k-1} , C _{f_k-2} , ..., C _{f_0} is left floating, does not participate in the sampling of the input signal, nor is it connected loop, so the capacitance corresponding to the disconnected feedback capacitance adjustment switch does not work in the circuit. The feedback capacitance adjustment module adjusts the value of the effective feedback capacitance C _{f_eq} of the access circuit through the feedback capacitance adjustment switch. ; The third switch connected to C _{f_k-1} , C _{f_k-2} , ..., C _{f_0} in Figure 2(b), one end is connected to the capacitor lower-level board, and the other end is connected to the output of the op amp, this switch is called here is a loop switch and is subject to a residual amplified clock

control.

In Figure 2(b), the OPA is an operational amplifier. The negative input terminal of the operational amplifier is connected to the upper plate of the capacitors C _{x_1} , C _{x_2} , ..., C _{x_n} , and C _{f_k} respectively. The positive input terminal is grounded to GND, and the output terminal V _{outi is} connected to the loop switch.

In Figure 2(b), C _{f_k} is controlled by three switches, two of which are the same as the sampling switch and the grounding switch, so they are also called the sampling switch and the grounding switch respectively, and the third switch is the same as the loop switch, so it is also loop switch.

As can be seen from Figure 1(b), the main circuit of the pipeline ADC will output the total digital output code to the output code storage module. As shown in Figure 3, there are two storage modules inside the output code storage module, and one pair of output code storage arrays D _out1 is stored, the output code storage array 1 stores D _out2 , and then the stored code is simultaneously output to the output code subtraction module of the next level through two output ports. The output code storage module has four main input ports, among which CLK is the system clock; the D _out port is used to directly receive the total digital output code of the main circuit of the pipeline ADC; En_r1 and En_r2 are the output code storage array 1 and the output code storage array 2 respectively the enable signal. When En_r1 is enabled, the storage output code storage array 1 stores D _out , which is D _out1 . If En_r2 is enabled, the storage output code storage array 2 stores D _out , that is, D _out2 . En_r1 should be enabled when V _in1 is input, and En_r2 should be enabled when V _in2 is input to ensure that both memory arrays store the correct values. When neither En_r1 nor En_r2 is enabled, the output code memory array 1 and the output code memory array 2 Perform a latch operation.

As shown in Figure 3, the output coding subtraction module also has four main input ports, of which CLK is the system clock; En_su is its enable port. Only when En_su is enabled, the output coding subtraction module performs the subtraction operation, and at other times It is in the latch hold state to avoid inputting unnecessary values to the post-stage to affect the operation of the algorithm, and at the same time to ensure that the post-stage can receive the input signal stably; one of the other two ports is used to receive the D _out1 output from the output code storage module. , and the other is used to receive D _out2 from the output coding storage module. After enabling and receiving the input signal, this module performs the operation of subtracting D _out1 from D _out2 , and outputs the subtraction result ΔD _out for the difference comparison module.

As shown in Figure 3, the difference comparison module has three main input ports, of which CLK is the system clock; the second is the enable terminal, which is controlled by En_cmp. When the enable signal is not enabled, the difference comparison module performs a latch operation , when the enable signal is enabled, the difference comparison module performs the comparison operation; the other input terminal receives the output signal ΔD _out of the output coding subtraction module, and the difference comparison module compares ΔD _out with the ΔD _{out_id} stored in the difference comparison module in advance For comparison, if ΔD _out is equal to ΔD _{out_id} , that is, there is no gain error, then D_equ is high, and D_big and D_small are low; if ΔD _out is greater than ΔD _{out_id} , that is, the inter-stage gain is too large, then D_big is high. If ΔD _out is smaller than ΔD _{out_id} , that is, the inter-stage gain is small, D_small is high, and D_equ and D_big are low. The three output ports of the difference comparison module respectively send D_small, D_equ and D_big to the feedback capacitor control module and the input voltage selection module to control them.

As shown in Figure 3, the function of the feedback capacitor control module is similar to that of the counter. It has five main input ports, of which CLK is the system clock, En_ctr receives the enable signal, and the other three receive three input signals of D_small, D_equ, and D_big. The feedback capacitance control module has a total of k-bit outputs, namely Dctr_k-1, Dctr_k-2, ..., Dctr_0, which are connected to the multiplying digital-to-analog converter MDAC to control the feedback capacitance adjustment switch. When D_equ is high and D_big and D_small are low, there is no gain error, and the output of the feedback capacitor control module remains unchanged; when D_big is high and D_equ and D_small are low, the gain bias between stages At this time, the effective feedback capacitance C _{f_eq} should be reduced, and the feedback capacitance control module performs a decrement operation, decrementing the original latched code by 1, corresponding to the effective feedback capacitance C _{f_eq} reducing a minimum step size; when D_small is high When D_equ and D_big are low level, the inter-stage gain is small. At this time, the effective feedback capacitor C _{f_eq} should be increased, and the feedback capacitor control module will add 1 to the original latched code by 1, corresponding to the effective feedback capacitor. C _{f_eq is} increased by a minimum step size.

As shown in Figure 3, the input voltage selection module has eight main input ports, one of which is the calibration method enable signal En_cal. When En_cal is not enabled, the calibration method does not work. When En_cal is enabled, the calibration process starts. ; Two of them are system clock CLK, and the other three receive three input signals of D_small, D_equ and D_big; the last three receive three input signals V _in , V _in1 and V _in2 . V _in is the input signal that should be connected to the pipeline ADC when it is working normally, V _in1 is the DC differential mode input voltage required in step 1, V _in2 is the DC differential mode input voltage required in step 2, and they are connected to the input voltage together Select the module, the input voltage is selectively connected to the main circuit of the pipeline ADC, namely V _inS . When the calibration method is working, the input voltage selection module, according to the steps of calibration, uses the enable signals En_r1, En_r2, En_su, En_cmp, and En_ctr to respectively select the output code storage module, the output code subtraction module, the difference comparison module, and the feedback capacitor. control module.

Figure 4(a) is the ideal case, the MDAC transfer curve of the multiplying digital-to-analog converter, where -(3V _ref )/4, -(V _ref )/4, (V _ref )/4, (3V _ref )/4, is the discrimination point of the Sub ADC comparator, and between the two comparator discrimination points is a folded curve corresponding to an output code Di of the Sub _ADC . According to the present invention, V _in1 and V _in2 should be in the same output coding section of the Sub ADC and V _in1 is greater than V _in2 .

Figure 4(b) is the ideal case where the MDAC transfer curve of the multiplying digital-to-analog converter is fitted to a straight line. Synthesize a straight transmission curve. If V _in1 and V _in3 are taken, it can be seen from Figure 4(b) that in fact, the difference between the total digital output codes corresponding to V _in1 and V _in3 is divided by the difference between V _in1 and V _in3 , and the transmission can also be calculated. The slope of the curve, which is the interstage gain. However, the problem is shown in Figure 4(c). In the case of capacitance mismatch, the transmission curve is fitted to a straight line, and there is an error Error_cap between each comparator discriminating sections, which will make the obtained The total digital output code difference contains an error step Error_cap, which makes the slope calculation error. Therefore, the two DC common-mode input voltages of the present invention need to be taken in the same output code section of the Sub ADC to avoid the influence of other errors on the results. . At the same time, V _in1 should be larger than V _in2 , this is to prevent negative numbers in the result and facilitate calculation, and the difference between V _in1 and V _in2 should not be too small, which may easily bring about quantization errors.

The following describes the workflow of the high-precision pipeline ADC front-end calibration method in detail with reference to FIG. 5 :

Connect the pipeline ADC to the test environment, enable En_cal, and the calibration process starts.

In the first step, the input voltage selection module chooses to input V _in1 into the main circuit of the pipeline ADC. At this time, the output coding storage module, the output coding subtraction module, the difference comparison module, and the feedback capacitor control module are all disabled.

In the second step, after several cycles, the pipeline ADC completes the quantization, and outputs the total digital output code D _out1 to the output code storage module. At this time, the input voltage selection module enables En_r1, and the output code storage array in the output code storage module is 1 pair. The total digital output code D _out1 of the pipeline ADC is stored, and other signals En_r2, En_su, En_cmp, and En_ctr are not enabled at this time.

In the third step, the input voltage selection module chooses to input V _in2 into the main circuit of the pipeline ADC. At this time, the output coding storage module, the output coding subtraction module, the difference comparison module and the feedback capacitor control module are all disabled.

In the fourth step, after several cycles, the pipeline ADC completes quantization, and outputs the total digital output code D _out2 to the output code storage module. At this time, the input voltage selection module enables En_r2, and the output code storage array in the output code storage module 2 pairs of The total digital output code D _out2 of the pipeline ADC is stored, and other signals En_r1, En_su, En_cmp, and En_ctr are not enabled at this time.

The fifth step, the input voltage selection module selects En_su to enable, the output code subtraction module works, and performs subtraction operation on the two total digital output codes D _out1 and D _out2 latched by the output code storage module, and the difference result ΔD _out is latched, and other signals En_r1, En_r2, En_cmp, and En_ctr are disabled at this time.

The sixth step, the input voltage selection module selects En_cmp to enable, the difference comparison module works, latches the output code subtraction module and inputs the incoming difference result ΔD _out and the ideal difference result ΔD _{out_id} to compare, If ΔD _out is equal to ΔD _{out_id} , that is, there is no gain error, then D_equ is high, D_big and D_small are low; if ΔD _out is greater than ΔD _{out_id} , that is, the inter-stage gain is too large, then D_big is high and D_equ , D_small is low level; if ΔD _out is less than ΔD _{out_id} , that is, the inter-stage gain is small, then D_small is high level, and D_equ and D_big are low level. At this time, other signals En_r1, En_r2, En_su and En_ctr are disabled.

In the seventh step, the input voltage selection module selects En_ctr to enable, and the feedback capacitor control module works, and the working process is described by taking k=3 as an example. If k=3, the feedback capacitance control module outputs three-bit codes Dctr_2, Dctr_1, Dctr_0, namely Dctr. In the initial state, Dctr=100, the output signal is Dctr_2=1, Dctr_1=0, Dctr_0=0, the feedback capacitor switch is turned on at high level, then the effective feedback capacitor C _{f_eq} =C _{f_3} +C _{f_2} =[(N-1)/N]*C _f +C _f /(N*2 ⁰ )=C _f , which is the same as the feedback capacitor that should be connected to the circuit for the traditional pipeline ADC. At this time, other signals En_r1 and En_r2 , En_cmp, and En_su are disabled.

According to equation (4), if there is no gain error, the inter-stage gain is approximately equal to the constant C _s /C _f , but due to the uncertainty of random errors and systematic errors, the actual inter-stage gain may be greater than the constant C _s /C _f , which may also be smaller than the constant C _s /C _f . The present invention determines the magnitude relationship of the inter-stage gain by comparing the magnitude relationship of ΔD _{out_id} of ΔD _out , which has been described above and will not be repeated here.

Therefore, if the signal input from the difference comparison module at this time is that D_equ is high level, and D_big and D_small are low level, it means that the actual inter-stage gain is equal to the ideal inter-stage gain, and the calibration is over; if D_big is high level, When D_equ and D_small are low level, the inter-stage gain is too large, the feedback capacitor control module decrements Dctr by 1, and the final output code Dctr=011, that is, Dctr_2=0, Dctr_1=1, Dctr_0=1, at this time access Effective feedback capacitance in the circuit C _{f_eq} =C _{f_3} +C _{f_1} +C _{f_0} =[(N-1)/N]*C _f +C _f /(N*2 ¹ )+C _f /(N*2 ² )=[(4N-1]/4N]C _f , slightly smaller than C _f , adjust C _{f_eq} smaller; if D_small is high level, D_equ and D_big are low level, then the gain between stages is small, and the feedback capacitor controls The module adds 1 to Dctr, and the final output code Dctr=101, that is, Dctr_2=1, Dctr_1=0, Dctr_0=1, at this time, the effective feedback capacitance C _{f_eq} =C _{f_3} +C _{f_2} +C _{f_0} =[(N-1)/N]*C _f +C _f /(N*2 ⁰ )+C _f /(N*2 ² )=[(4N+1]/4N]C _f , slightly larger than C _f , increase C _{f_eq} .

The eighth step, the input voltage selection module selects En_ctr to be disabled, so that the output code of the feedback capacitor control module is latched. After returning to the first step, re-detection is performed until D_equ is high, and D_big and D_small are low. level, the calibration is over, the input voltage selection module disables En_r1, En_r2, En_cmp, En_su, and En_ctr, and latches all signals. At this time, the size of C _{f_eq} will no longer change, indicating that the calibration is complete.

To sum up, the present invention can be applied to each pipeline sub-stage of the pipeline ADC, and the gain calibration is performed on each sub-stage of the pipeline ADC, which improves the traditional algorithm of high-speed and high-precision pipeline ADC. The algorithm logic can be realized by subtraction and comparison, and the inter-stage gain can be obtained by taking the difference of the value of the same section, which can largely avoid the influence of other errors. It can automatically start and stop automatically. It is efficient, fast, flexible and accurate. It is more suitable for high-speed and high-precision pipeline ADC calibration.

The above descriptions are only the preferred solutions of the present invention, and are not intended to further limit the present invention, and all equivalent changes made by using the contents of the description and drawings of the present invention are within the protection scope of the present invention.

Claims (8)

1. A high-precision assembly line ADC is characterized by comprising a main circuit, an output code storage module, an output code subtraction module, a difference value comparison module, a feedback capacitance control module and an input voltage selection module;

the main circuit outputs a total digital output code to an output code storage module;

the output code storage module stores the total digital output codes of the main circuit;

the output code subtraction module performs subtraction operation on the total digital output codes stored by the output code storage module and outputs the obtained result to the difference value comparison module;

the difference comparison module compares the output result of the output coding subtraction module with an ideal total digital output coding difference set in the difference comparison module in advance and outputs the obtained difference comparison result to the feedback capacitance control module;

the feedback capacitance control module generates a control signal according to an output result of the difference comparison module to control the feedback capacitance in the main circuit;

the input voltage selection module receives the output result of the difference comparison module and generates enable signals of the output code storage module, the output code subtraction module, the difference comparison module and the feedback capacitance control module according to the output result so as to control the calibration or enable the pipeline ADC to work normally.

2. The high-precision pipelined ADC of claim 1, wherein the main circuit comprises a plurality of pipeline sub-stages, a last-stage flash ADC, a delay in-phase module, and a redundancy calibration module;

wherein, a plurality of pipeline substages are connected in sequence, the input end of the next pipeline substage is connected with the analog output end of the previous pipeline substage, and the input end of the first pipeline substage is connected with an input signal V _in The analog output end of the last pipeline sub-stage is connected with the flash memory type ADC of the last stage;

the input end of the delay in-phase module is respectively connected with the digital output end of each pipeline sub-stage and the flash memory type ADC of the last stage; the input end of the redundancy calibration module is connected with the output end of the delay in-phase module;

the delay in-phase module receives the output codes of the sub-stages of each production line and the output codes of the flash memory type ADC of the last stage, and outputs the output codes to the redundancy calibration module; the redundancy calibration module calibrates the received output code and outputs a pipeline ADC total digital output code D _out 。

3. A high precision pipeline ADC according to claim 2 wherein each pipeline sub-stage is formed by a multiplying digital to analog converter MDAC module and an auxiliary analog to digital converter subcodc module which simultaneously receive the input signal V _in And the auxiliary analog-to-digital converter SubADC module controls the multiplication digital-to-analog converter MDAC module to generate analog output which is transmitted to the next pipeline sub-stage, and the auxiliary analog-to-digital converter SubADC module generates digital output which is transmitted to the delay in-phase module.

4. A method for calibrating a high precision pipelined ADC front-end according to any one of claims 1 to 3, comprising the steps of:

step 1: a differential mode direct current voltage input signal V is transmitted to the assembly line ADC through an external signal source _in1 Obtaining a total digital output code D of the pipeline ADC _out1 The output code is stored in an output code storage module;

and 2, step: a differential mode direct current voltage input signal V is transmitted to the assembly line ADC through an external signal source _in2 Obtaining the total digital output code D of the pipeline ADC _out2 The output code is stored in an output code storage module;

and step 3: according to transmission curves of all levels and a redundancy addition calibration algorithm, calculating the current V through a manual theory _in1 And V _in2 Ideal total digital output code D corresponding to the pipeline ADC when respectively input _{out1_id} And D _{out2_id} Outputting the ideal total number of digits to code D _{out1_id} And D _{out2_id} Make a difference, i.e. D _{out1_id} -D _{out2_id} ＝ΔD _{out_id} To obtain the difference value Delta D of two total digital output codes of the pipeline ADC under the ideal condition _{out_id} And stored in the difference comparison module;

and 4, step 4: the output coding subtraction module stores the pipeline ADC obtained in the step 1 and the step 2 in two digital outputs D in the output coding storage module _out1 And D _out2 By subtraction, i.e. D _out1 -D _out2 ＝ΔD _out Obtaining a difference result Delta D _out I.e. in practice the pipeline ADCs input V separately _in1 And V _in2 Outputting the coded difference value by total digital time;

and 5: the difference comparison module compares the delta D _out And Δ D _{out_id} For comparison, the following three cases were obtained:

if Δ D _out >ΔD _{out_id} At the moment, the actual interstage gain of the pipeline ADC is larger than the ideal interstage gain, and the feedback capacitance control module is used for controlling the actual interstage gain of the pipeline ADC according to an analog domain calculation formula of the actual interstage gain of the pipeline ADCWill make the effective feedback capacitance C _{f_eq} Decrease, C _{f_eq} Reducing interstage gain for an effective feedback capacitor of the pipeline ADC sample-and-hold circuit in an amplification phase, and then repeating the step 1, the step 2 and the step 4 until the actual interstage gain is equal to the ideal interstage gain;

if Δ D _out <ΔD _{out_id} At the moment, the actual interstage gain of the assembly line ADC is smaller than the ideal interstage gain, and the feedback capacitance control module enables the effective feedback capacitance C to be in accordance with a calculation formula of an analog domain of the actual interstage gain of the assembly line ADC _{f_eq} Getting larger to make the interstage gain larger, and then repeating the step 1, the step 2 and the step 4 until the interstage gain is equal to the ideal interstage gain;

if Δ D _out＝ ΔD _{out_id} And at the moment, the actual interstage gain of the assembly line ADC is equal to an ideal value, the calibration is stopped, and the control signal of the adjustable feedback capacitor is solidified to enable the effective feedback capacitance value C _{f_eq} No longer changed.

5. The method of claim 4, wherein the two DC differential mode voltage input signals V are used as the front-end calibration of the pipelined ADC _in1 And V _in2 In the same section of the transmission curve, and V _in1 Greater than V _in2 。

6. The method as claimed in claim 4, wherein the ideal interstage gain of the pipeline ADC is StageGain _id Is calculated by the formula

7. The method as claimed in claim 4, wherein the inter-stage gain StageGain detected by the calibration circuit is used for calibrating the front end of the pipeline ADC _det The calculation formula of (2) is as follows:

8. the method as claimed in claim 4, wherein the high-precision pipeline ADC front-end calibration method is characterized in that the pipeline ADC interstage gain StageGain is estimated in an analog domain _ana The calculation formula is as follows:

wherein A is the open-loop gain of the operational amplifier in the pipeline ADC sampling and holding circuit, and C _s The total sampling capacitance of the pipeline ADC sampling and holding circuit at a sampling phase is obtained; beta is a closed loop feedback factor of the pipeline ADC sampling and holding circuit, namely beta = C _{f_eq} /C _s ，C _x A capacitor C connected to the reference voltage when the pipeline ADC sample-and-hold circuit is in the amplification phase _s ＝C _{f_eq} +C _x ，K＝C _x /C _{f_eq} 。

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