CN110620582A - Capacitance mismatch calibration method for pipeline analog-to-digital converter - Google Patents
Capacitance mismatch calibration method for pipeline analog-to-digital converter Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/10—Calibration or testing
- H03M1/1009—Calibration
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Abstract
The invention discloses a capacitance mismatch calibration method for a pipeline analog-to-digital converter, which comprises the following steps: step 1, in a calibration mode, measuring each residual error step amplitude in an input/output curve of a stage circuit of a pipeline analog-to-digital converter, determining actual weight corresponding to the output of each comparator in the stage circuit, and storing the actual weight in an on-chip register; and 2, after the calibration is finished, entering a conversion mode, and calling the stored corresponding actual weight to calculate a final conversion result according to the conversion output of each comparator in the stage circuit. The invention provides a capacitance mismatch calibration method for a pipeline analog-to-digital converter, which not only improves the linearity and the dynamic range of the pipeline analog-to-digital converter, but also does not increase the circuit design complexity and the chip area.
Description
Technical Field
The invention relates to a capacitance mismatch calibration method for a pipeline analog-to-digital converter, which is mainly used for calibrating nonlinear errors introduced by sampling capacitance mismatch in a pipeline circuit and belongs to the technical field of mixed signal integrated circuits.
Background
The high-speed signal processing fields such as wireless networks and information communication have higher and higher requirements on the speed and the precision of the analog-to-digital converter. Among analog-to-digital converters with various structures, a pipeline analog-to-digital converter is a popular research structure for high-performance analog-to-digital converters because three important characteristics, namely precision, speed and power consumption, can be well compromised.
As manufacturing processes evolve, process feature sizes and process voltages continue to scale down, but device-to-device mismatches are not reduced by advances in the process, which degrades the performance of analog circuits. In the pipeline analog-to-digital converter, the mismatch of the sampling capacitors can cause an inter-stage gain error and the jump of an input-output curve of a stage circuit to be highly inconsistent, so that the linearity of the analog-to-digital converter is poor. If the error is not calibrated, the precision of the pipeline analog-to-digital converter is limited to be within 10 bits, and the requirement of the application is difficult to achieve.
The existing capacitance mismatch calibration technologies, such as a dynamic capacitance matching (DEM) technology, a Dither Injection (Dither Injection) technology, a Passive Capacitor Error Averaging (Passive Capacitor Error Averaging) technology, an Active Capacitor Error Averaging (Active Capacitor Error Averaging) technology, and the like, have better calibration effects respectively, but increase the circuit design complexity and the chip area.
Disclosure of Invention
The technical problem to be solved by the invention is to overcome the defects of the prior art and provide a capacitance mismatch calibration method for a pipeline analog-to-digital converter, which not only improves the linearity and the dynamic range of the pipeline analog-to-digital converter, but also does not increase the circuit design complexity and the chip area.
In order to solve the technical problems, the invention adopts the following technical scheme:
a method of capacitance mismatch calibration for a pipelined analog-to-digital converter, comprising the steps of:
step 1, in a calibration mode, measuring each residual error step amplitude in an input/output curve of a stage circuit of a pipeline analog-to-digital converter, determining actual weight corresponding to the output of each comparator in the stage circuit, and storing the actual weight in an on-chip register;
and 2, after the calibration is finished, entering a conversion mode, and calling the stored corresponding actual weight to calculate a final conversion result according to the conversion output of each comparator in the stage circuit.
Further, in step 1, the calibration controller controls the core of the pipelined analog-to-digital converter to work, and measures the real digital weight of each capacitor to be calibrated;
the measurement process starts from the third-stage sub analog-to-digital converter, and when the third-stage sub analog-to-digital converter is calibrated, the measurement is performed by a rear-stage analog-to-digital converter composed of a rear-stage pipeline stage and a flash analog-to-digital converter; when the third-stage sub analog-to-digital converter is calibrated, the second-stage sub analog-to-digital converter is calibrated, and at the moment, the rear-stage analog-to-digital converter consisting of the calibrated third-stage sub analog-to-digital converter, the rear-stage pipeline analog-to-digital converter and the flash analog-to-digital converter performs measurement; when the second-stage sub analog-digital converter is calibrated, the first-stage sub analog-digital converter is calibrated, at the moment, the rear-stage analog-digital converter consisting of the calibrated second-stage and third-stage sub analog-digital converters, the rear-stage pipeline analog-digital converter and the flash analog-digital converter performs measurement, and finally error calibration is finished.
Further, in step 2, the digital calibration circuit performs weighted summation according to the comparator array output result output by the pipelined analog-to-digital converter core and the corresponding capacitance weight, so as to obtain accurate analog-to-digital conversion output.
Further, in the calibration mode, for the sampling network of the flash analog-to-digital converter in the M-bit stage circuit, 2M-1A comparator outputs 0, 2M-1And the output of each comparator is 1, the output of the appointed 1 comparator is switched between 0 and 1, and meanwhile, the differential zero input of the stage circuit is enabled, the output voltage of the stage circuit jumps up and down at the moment, and the amplitude of the output voltage corresponds to the residual step amplitude of the position, corresponding to the appointed comparator, in the input and output curve of the stage circuit.
Further, a subsequent analog-to-digital converter formed by a subsequent circuit is utilized to respectively perform analog-to-digital conversion on the upper voltage and the lower voltage output by the current circuit, and the subtraction of the two values after the analog-to-digital conversion is the actual weight height; and controlling the input of the stage circuit and the output of the comparator according to the step, and measuring the step amplitude of each residual error in the stage circuit in turn.
Further, the output of the comparator in the first three-level sub-ADC circuit is defined as Ti_jAnd has a value of 0 or 1, where i represents the ith stage and j represents the jth comparator output; let W be the digital weight corresponding to the ith analog-to-digital conversion capacitori_jThen the converted output of the analog-to-digital converter is calculated by the following equation:
DO＝∑Ti_jWi_j+Dbe
wherein Dbe is the conversion output of the next-stage ADC consisting of the next-stage pipeline ADC without calibration structure and the flash ADC.
The invention achieves the following beneficial effects:
the invention provides a capacitance mismatch calibration method for a pipeline analog-to-digital converter, which not only improves the linearity and the dynamic range of the pipeline analog-to-digital converter, but also does not increase the circuit design complexity and the chip area.
Drawings
FIG. 1 is a schematic diagram of a third stage pipeline stage calibration;
FIG. 2 is a schematic diagram of a calibration for a second stage pipeline stage;
FIG. 3 is a schematic diagram of a calibration for a first stage pipeline stage;
FIG. 4 is a schematic diagram of the input/output curves of a 3-bit stage circuit;
FIG. 5 is a schematic diagram of a circuit configuration of a comparator sampling network with a calibration structure according to the present invention;
fig. 6 is a schematic diagram of the output result of the comparator control signal S1 when a1/a0 is 00.
Detailed Description
The invention is further described below with reference to the accompanying drawings. The following examples are only for illustrating the technical solutions of the present invention more clearly, and the protection scope of the present invention is not limited thereby.
In pipelined analog-to-digital converters, conversion errors are introduced due to capacitance mismatch and op-amp finite gain effects that cause the gain of the stage circuit to deviate from the ideal value. To calibrate this error, a foreground calibration algorithm is introduced in the first three levels of sub-adc circuits. The basic principle of the algorithm is as follows: in the input-output transfer curve of the stage circuit, each time a digital 1 is added to the sub analog-to-digital converter, the analog residual error correspondingly jumps downwards by a voltage, the voltage step amplitude is determined by the capacitance value of a corresponding capacitor and the operational amplifier gain, the analog residual error step amplitude deviates from an ideal value due to the capacitor mismatch and the finite gain, and an error is brought if the conversion result is calculated by using the ideal weight represented by the digital 1. In order to eliminate the effects of capacitance mismatch and finite gain, it is necessary to measure the magnitude of each residual step in the input-output curve of the stage circuit to determine their actual weights. Thus, the analog-to-digital converter has a calibration mode and a conversion mode. Firstly, in a calibration mode, each comparator in a measurement stage circuit (each capacitor in the measurement stage circuit corresponds to one comparator one by one) outputs a corresponding actual weight, and the actual weight is stored in an on-chip register; secondly, after the calibration is finished, a conversion mode is entered, and the stored actual weight is called instead of the ideal weight to calculate the final conversion result according to the conversion output of each comparator of the stage circuit.
In the calibration mode, the calibration controller controls the inner core of the pipeline analog-to-digital converter to work, and the real digital weight of each capacitor to be calibrated is measured. The measurement process starts from the third stage, and when the third stage is calibrated, the subsequent analog-to-digital converter composed of the subsequent pipeline stage and the flash analog-to-digital converter performs measurement, as shown in fig. 1; when the third stage calibration is completed, the second stage calibration is started, and at this time, the post-stage analog-to-digital converter composed of the calibrated third stage, the post-stage pipeline stage, and the flash analog-to-digital converter performs the measurement, as shown in fig. 2; when the second stage calibration is completed, the first stage calibration is started, and at this time, the post-stage analog-to-digital converter composed of the calibrated second and third stages, the post-stage pipeline stage, and the flash analog-to-digital converter performs measurement, as shown in fig. 3, and finally completes the calibration of the error.
In a normal conversion mode, the digital calibration circuit performs weighted summation according to the output result of the comparator array output by the core of the pipelined analog-to-digital converter and the corresponding capacitance weight value to obtain accurate analog-to-digital conversion output.
Defining the output of a comparator in the first three-level sub analog-to-digital converter circuit as Ti_j. Here, Ti_jWhere i denotes the ith stage and j denotes the jth comparator output, then Ti_jThe output of the jth comparator in the ith stage circuit is 0 or 1. In addition, let W be the digital weight corresponding to the ith analog-to-digital conversion capacitori_jThen the converted output of the analog-to-digital converter is calculated by the following equation:
DO＝∑Ti_jWi_j+Dbe
in the above formula, Dbe is the conversion output of the next-stage adc composed of the next-stage pipeline stage without calibration structure and the flash adc.
The input-output curves of the pipeline stage circuit are shown in fig. 4. In the calibration mode, in order to control the step amplitude of a given position in the input/output curve of the measurement stage, the sampling network of the flash analog-to-digital converter in the stage circuit needs to be improved in the stage circuit design, as shown in fig. 5, so as to achieve the following two goals: 1) the stage circuit inputs may be forced to differential zero inputs; 2) the comparator output 0 or 1 can be controlled. On the basis, 2 in an M-bit stage circuit can be realizedM-1A comparator outputs 0, 2M-1The comparator outputs 1, the output of the appointed 1 comparator is switched between 0 and 1, and meanwhile, the differential zero input of the stage circuit is enabled, the output voltage of the stage circuit jumps up and down at the moment, and the amplitude of the output voltage corresponds to the residual error step amplitude of the position, corresponding to the appointed comparator, in the input and output curve of the comparator. The upper voltage and the lower voltage output by the current stage circuit are respectively subjected to analog-to-digital conversion by using a post-stage analog-to-digital converter formed by a post-stage circuit, and the two values after the analog-to-digital conversion are subtractedI.e. the actual weight height. By controlling the inputs of the stage circuit and the output of the comparator according to this method, the magnitude of each residual step in the stage circuit can be measured in turn.
The logical relationship of the comparator threshold selector circuit is shown in table 1. The circuit is divided into two working states of calibration and non-calibration, and the control signal is FORE. When the FORE is 0, the circuit is in a normal working state, the threshold value of the comparator is connected to a specific voltage according to the function, VRPI is a positive terminal reference voltage, VRNI is a negative terminal reference voltage, and the control signal S does not play a control role at the moment; when the supply is 1, the circuit is in a calibration state, and the control signal S controls the threshold of the comparator to be connected with the power supply or the ground respectively, so that the comparator outputs 0 or 1.
TABLE 1 comparator threshold selector logic truth table
For an M-bit stage circuit, there is 2M-1 array of analog-to-digital conversion capacitors consisting of 2MOutput of 1 comparator to control, corresponding to 2 in the stage input-output transfer curveM1 residual step amplitude. In the calibration mode, a comparator output of 0 or 1 can be controlled by the circuit shown in fig. 5, and based on this, the selective decoding of the comparator, the output value of the comparator and the output timing can be realized by the digital calibration controller.
Taking a 2-bit stage circuit as an example, the circuit has three inputs of a1, a0 and a CLK clock signal, a1 and a0 are provided by the digital calibration controller output, and some combination of a1 and a0 represents a calibration trigger for a certain capacitor of the stage circuit and sends a signal for calibrating the certain capacitor; the circuit has 3 outputs, S1-S3 respectively represent control signals to a comparator corresponding to a certain capacitor, alternate measurement is performed to calibrate the weight corresponding to the certain capacitor, CLK clock is divided by two to control the certain output S to be at a low level in one period and at a high level in another period, for example, A1a0 is 00, which represents calibration of the first capacitor, simulation results of S1 are shown in fig. 6, and the output 0/1 of S1 is alternately output, and the high and low levels are respectively maintained for one clock period. While the remaining 2S signals are one 0 and one 1, e.g., S2/S3 ═ 01, so that the stage circuit output does not saturate. It can be seen from table 2 that each decoding state guarantees that the output states are a0 and a1, and the purpose of this is to control the comparator output so as to control the reference voltages of the corresponding capacitors to be a VRP and a VRN, so that 3 capacitors can be measured respectively when the fixed input voltage is zero.
TABLE 2 comparator control signal decoding table
In table 2, T denotes a square wave signal divided by two times by the sampling clock of the analog-to-digital converter.
By integrating the comparator threshold selection circuit and the calibration decoding circuit described above in the stage circuit, the interface and control between the calibration controller and the stage circuit is simplified. When the controller needs to measure the weight of the ith capacitor of the current stage circuit, the controller can measure the weight as W by setting FORE to 1 and outputting an address A1A0 to i, the residual error output of the stage circuit can automatically jump up and down, and the controller collects and calculates the output of the later stage analog-to-digital converteri_j。
The above description is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, several modifications and variations can be made without departing from the technical principle of the present invention, and these modifications and variations should also be regarded as the protection scope of the present invention.
Claims (6)
1. A capacitance mismatch calibration method for a pipeline analog-to-digital converter is characterized by comprising the following steps:
step 1, in a calibration mode, measuring each residual error step amplitude in an input/output curve of a stage circuit of a pipeline analog-to-digital converter, determining actual weight corresponding to the output of each comparator in the stage circuit, and storing the actual weight in an on-chip register;
and 2, after the calibration is finished, entering a conversion mode, and calling the stored corresponding actual weight to calculate a final conversion result according to the conversion output of each comparator in the stage circuit.
2. The method according to claim 1, wherein in step 1, the calibration controller controls the cores of the pipelined analog-to-digital converter to operate and measures the true digital weights of each capacitor to be calibrated;
the measurement process starts from the third-stage sub analog-to-digital converter, and when the third-stage sub analog-to-digital converter is calibrated, the measurement is performed by a rear-stage analog-to-digital converter composed of a rear-stage pipeline stage and a flash analog-to-digital converter; when the third-stage sub analog-to-digital converter is calibrated, the second-stage sub analog-to-digital converter is calibrated, and at the moment, the rear-stage analog-to-digital converter consisting of the calibrated third-stage sub analog-to-digital converter, the rear-stage pipeline analog-to-digital converter and the flash analog-to-digital converter performs measurement; when the second-stage sub analog-digital converter is calibrated, the first-stage sub analog-digital converter is calibrated, at the moment, the rear-stage analog-digital converter consisting of the calibrated second-stage and third-stage sub analog-digital converters, the rear-stage pipeline analog-digital converter and the flash analog-digital converter performs measurement, and finally error calibration is finished.
3. The method according to claim 2, wherein in step 2, the digital calibration circuit performs weighted summation according to the output result of the comparator array output by the pipelined analog-to-digital converter core and the corresponding capacitance weight to obtain an accurate analog-to-digital conversion output.
4. A method as claimed in claim 2, wherein in the calibration mode, for the sampling network of the flash adc in the M-bit stage circuit, 2M-1A comparator outputs 0, 2M-1One comparator output of 1, the designated 1 comparator output switching between 0 and 1,and simultaneously, the differential zero input of the stage circuit is enabled, the output voltage of the stage circuit jumps up and down at the moment, and the amplitude of the output voltage corresponds to the residual error step amplitude of the position, corresponding to the appointed comparator, in the input and output curve of the stage circuit.
5. The method as claimed in claim 4, wherein the analog-to-digital converter of the next stage is used to perform analog-to-digital conversion on the upper voltage and the lower voltage outputted by the current stage, and the subtraction of the two values after analog-to-digital conversion is the actual weight height; and controlling the input of the stage circuit and the output of the comparator according to the step, and measuring the step amplitude of each residual error in the stage circuit in turn.
6. The method of claim 2, wherein the output of the comparator in the first three stages of sub-adc circuits is defined as Ti_jAnd has a value of 0 or 1, where i represents the ith stage and j represents the jth comparator output; let W be the digital weight corresponding to the ith analog-to-digital conversion capacitori_jThen the converted output of the analog-to-digital converter is calculated by the following equation:
wherein Dbe is the conversion output of the next-stage ADC consisting of the next-stage pipeline ADC without calibration structure and the flash ADC.
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| CN114389613A (en) * | 2022-03-24 | 2022-04-22 | 南京航空航天大学 | Capacitance mismatch calibration method of segmented successive approximation ADC |
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