CN112737583A

CN112737583A - High-precision assembly line ADC and front-end calibration method

Info

Publication number: CN112737583A
Application number: CN202011581048.8A
Authority: CN
Inventors: 夏洪亮; 张翼; 胡鸿飞; 刘依桦; 刘坤; 戚骞; 蔡志匡; 肖建; 郭宇峰
Original assignee: Nanjing University of Posts and Telecommunications
Current assignee: Suzhou Zhijuxinlian Microelectronics Co ltd
Priority date: 2020-12-28
Filing date: 2020-12-28
Publication date: 2021-04-30
Anticipated expiration: 2040-12-28
Also published as: CN112737583B

Abstract

The invention discloses a high-precision pipeline ADC and a front-end calibration method, wherein a differential mode direct current input signal V is input to the pipeline ADC through an external signal source_in1Storing the total digital output code D of the pipeline ADC at the moment_out1Then fixing the input signal of the pipeline ADC to V_in2And storing the output code D of the pipeline ADC at the moment_out2D is_out1And D_out2Making a difference, obtaining the obtained delta D_outWith ideally the pipeline ADC input being V_in1And V_in2Time-of-flight output coded difference Δ D_{out_id}Comparing, judging gain, and adjusting effective feedback capacitor C of MDAC module in ADC according to judgment result_{f_eq}Thereby achieving the purpose of adjusting the gain. The process is repeated until Δ D_out＝ΔD_{out_id}And solidifying the feedback capacitance control signal to finish foreground calibration. The invention overcomes the defects of complex traditional algorithm and low precision in the high-precision production line ADC, and can realize algorithm logic only by storing, subtracting and comparingThe method has the characteristics of high efficiency, rapidness and accuracy, and is relatively suitable for calibrating the high-speed high-precision pipeline ADC.

Description

High-precision assembly line ADC and front-end calibration method

Technical Field

The invention belongs to the field of high-precision assembly line ADC calibration, and particularly relates to a high-precision assembly line ADC and a front-end calibration method thereof.

Background

The structure of a traditional pipeline ADC system is shown in fig. 1(a), where an input signal is directly injected into a first pipeline sub-stage for sampling, and each pipeline sub-stage alternately performs sampling and residual amplification under the control of two-phase non-overlapping clocks. In each sub-stage of the assembly line, during sampling phase, the multiplying digital-to-analog converter MDAC and the auxiliary analog-to-digital converter SubADC simultaneously sample the input signal and finish sampling simultaneously, so as to ensure that the comparators in the multiplying digital-to-analog converter MDAC and the auxiliary analog-to-digital converter SubADC sample the same input signal point, and the auxiliary analog-to-digital converter SubADC generates a digital code D according to the comparison result of the comparators_i(ii) a Digital code D at residual amplified phase_iMultiplying the input signal V with the digital-to-analog converter MDAC_inAnd subtracting to generate a residual signal, amplifying the residual signal by a multiplying digital-to-analog converter (MDAC), sending the generated residual amplified signal to the next pipeline sub-stage to be used as an input signal of the next pipeline sub-stage, and repeating the process. A schematic diagram of a conventional multiplying digital-to-analog converter MDAC is shown in fig. 2(a), and the input-output relationship of the conventional multiplying digital-to-analog converter MDAC is as follows:

wherein V_outIs to amplify the residual error by a multiplying digital-to-analog converter MDACAnd then output to the output signal, V, of the next pipeline sub-stage_refIs a reference voltage, C_iIs a unit sampling capacitor, k is the number of bits of each pipeline sub-stage of the pipeline ADC, and stagegan is an inter-stage gain. In a low-speed low-precision pipeline ADC, a high-gain index of an operational amplifier can be realized relatively simply, so that the inter-stage gain StageGain can be approximately equal to a constant, and no gain error exists at the moment. However, as the pipeline ADC develops towards high speed and high precision, the high speed requires a large bandwidth, the high precision requires a high gain, and the high gain and high bandwidth operation is difficult to realize, so that the inter-stage gain stagegan cannot be approximated to a constant, thereby causing a gain error and affecting the performance of the pipeline ADC. In recent years, high-speed and high-precision pipeline ADCs often adopt a gain sacrificing mode to ensure that the operational amplifier bandwidth is larger, and ensure the working speed of the operational amplifier and the pipeline ADC, which cannot be considered at the same time.

Disclosure of Invention

Aiming at the defects that the gain and the speed of the operational amplifier cannot be considered in the prior art, the invention provides the high-precision pipeline ADC and the effective front-end calibration method. According to claim 5, the two input signals are in the same section, so that errors caused by other factors such as capacitance mismatch can be avoided, and the accuracy of the calibration algorithm is ensured.

The invention relates to a high-precision assembly line ADC, which adopts the technical scheme that: the device comprises a main circuit, an output code storage module, an output code subtraction module, a difference value comparison module, a feedback capacitance control module and an input voltage selection module;

the main circuit outputs a total digital output code to an output code storage module;

the output code storage module stores the total digital output codes of the main circuit;

the output code subtraction module performs subtraction operation on the total digital output codes stored by the output code storage module and outputs the obtained result to the difference value comparison module;

the difference comparison module compares the output result of the output coding subtraction module with an ideal total digital output coding difference set in the difference comparison module in advance and outputs the obtained difference comparison result to the feedback capacitance control module;

the feedback capacitance control module generates a control signal according to an output result of the difference comparison module to control the feedback capacitance in the main circuit;

the input voltage selection module receives the output result of the difference comparison module, if the output result is that gain errors exist, calibration is continued, at the moment, the input voltage selection module also generates enable signals of the output code storage module, the output code subtraction module, the difference comparison module and the feedback capacitance control module to control the calibration, if the gain errors do not exist in the comparison result, the calibration is ended, and an external input signal V is used_inAnd accessing the pipeline ADC, and enabling the pipeline ADC to work normally.

Furthermore, the main circuit comprises a plurality of pipeline sub-stages, a flash memory type ADC of the last stage, a delay in-phase module and a redundancy calibration module;

wherein, a plurality of pipeline substages are connected in sequence, the input end of the next pipeline substage is connected with the analog output end of the previous pipeline substage, and the input end of the first pipeline substage is connected with an input signal V_inThe analog output end of the last pipeline sub-stage is connected with the flash memory type ADC of the last stage;

the input end of the delay in-phase module is respectively connected with the digital output end of each pipeline sub-stage and the flash memory type ADC of the last stage; the input end of the redundancy calibration module is connected with the output end of the delay in-phase module;

the delay in-phase module receives the output codes of the sub-stages of each production line and the output codes of the flash memory type ADC of the last stage, and outputs the output codes to the redundancy calibration module; the redundancy calibration module encodes the received output intoLine alignment and output pipeline ADC total digital output code D_out。

Furthermore, each pipeline sub-stage is composed of a multiplying digital-to-analog converter MDAC module and an auxiliary analog-to-digital converter SubADC module which simultaneously receive an input signal V_inAnd the auxiliary analog-to-digital converter SubADC module controls the multiplication digital-to-analog converter MDAC module to generate analog output and transmit the analog output to the next pipeline sub-stage, and the auxiliary analog-to-digital converter SubADC module generates digital output and transmits the digital output to the delay in-phase module.

The high-precision pipeline ADC front-end calibration method comprises the following steps:

step 1: a differential mode direct current voltage input signal V is transmitted to the assembly line ADC through an external signal source_in1Obtaining the total digital output code D of the pipeline ADC_out1The output code is stored in an output code storage module;

step 2: a differential mode direct current voltage input signal V is transmitted to the assembly line ADC through an external signal source_in2Obtaining the total digital output code D of the pipeline ADC_out2The output code is stored in an output code storage module;

two direct current differential mode voltage input signals V_in1And V_in2In the same section of the transmission curve, and V_in1Greater than V_in2。

And step 3: calculating the current V by manual theoretical calculation according to transmission curves of all levels and a redundancy addition calibration algorithm_in1And V_in2Ideal total digital output code D corresponding to the pipeline ADC when respectively input_{out1_id}And D_{out2_id}Outputting the ideal total number of digits to code D_{out1_id}And D_{out2_id}Make a difference, i.e. D_{out1_id}-D_{out2_id}＝ΔD_{out_id}To obtain the difference value Delta D of two total digital output codes of the pipeline ADC under the ideal condition_{out_id}And stored in the difference comparison module;

and 4, step 4: the output coding subtraction module stores the pipeline ADC obtained in the step 1 and the step 2 in two digital outputs in the output coding storage moduleD_out1And D_out2By subtraction, i.e. D_out1-D_out2＝ΔD_outObtaining a difference result Delta D_outI.e. in practice the pipeline ADCs input V separately_in1And V_in2Outputting the coded difference value by total digital time;

and 5: the difference comparison module compares the delta D_outAnd Δ D_{out_id}For comparison, the following three cases were obtained:

if Δ D_out>ΔD_{out_id}At this time, the actual interstage gain of the pipeline ADC is larger than the ideal interstage gain, and the feedback capacitance control module enables the effective feedback capacitance C to be larger than the ideal interstage gain according to the analog domain calculation formula of the actual interstage gain of the pipeline ADC_{f_eq}Reducing the interstage gain, and then repeating the step 1, the step 2 and the step 4 until the actual interstage gain is equal to the ideal interstage gain;

if Δ D_out<ΔD_{out_id}At this time, the actual interstage gain of the pipeline ADC is smaller than the ideal interstage gain, and the feedback capacitance control module enables the effective feedback capacitance C to be in accordance with the analog domain calculation formula of the actual interstage gain of the pipeline ADC_{f_eq}Getting larger to make the interstage gain larger, and then repeating the step 1, the step 2 and the step 4 until the interstage gain is equal to the ideal interstage gain;

if Δ D_out＝ΔD_{out_id}And at the moment, the actual interstage gain of the assembly line ADC is equal to an ideal value, the calibration is stopped, and the adjustable feedback capacitance control signal is solidified to enable the effective feedback capacitance value C to be equal to the ideal value_{f_eq}No longer changed.

Further, a pipelined ADC ideal interstage gain StageGain is presented herein_idThe calculation formula of (2) is as follows:

the calculation formula of the actual interstage gain StageGain of the pipeline ADC is as follows:

because of V_in1And V_in2Is a fixed differential mode DC input signal that is set, so Δ V_inIs constant, the difference Δ D between the actual total digital output codes of the pipelined ADC_outDifference Δ D from the pipelined ADC theoretical total digital output code_{out_id}The ratio of the magnitudes of (1) is the ratio of the inter-stage gains, i.e. if Δ D_out>ΔD_{out_id}Then, the actual interstage gain StageGain is larger than the ideal interstage gain StageGain_id(ii) a If Δ D_out<ΔD_{out_id}The actual interstage gain StageGain is smaller than the ideal interstage gain StageGain_id(ii) a If Δ D_out＝ΔD_{out_id}Then, the actual interstage gain StageGain is equal to the ideal interstage gain StageGain_idAt this time, it is shown that the gain error has been eliminated, and the adjustable feedback capacitance control signal can be cured and the foreground gain calibration method is ended.

And then, the analog domain calculation formula of the actual interstage gain of the pipeline ADC is provided as follows:

wherein A is the open-loop gain of the operational amplifier in the pipeline ADC sampling hold circuit, C_sThe total sampling capacitance of the pipeline ADC sampling and holding circuit at a sampling phase is obtained; beta is a closed loop feedback factor of the pipeline ADC sampling holding circuit (beta is C)_{f_eq}/C_s)，C_{f_eq}Is an effective feedback capacitance C when the pipeline ADC sample-and-hold circuit is in an amplification phase_xA capacitor C connected to the reference voltage when the pipeline ADC sample-and-hold circuit is in the amplification phase_s＝C_{f_eq}+C_x，K＝C_x/C_{f_eq}。

Thus, when C is decreased_{f_eq}When the time is longer, K is increased, and the interstage gain is reduced; when increasing C_{f_eq}When the time is longer, K is smaller, and the interstage gain is larger; the purpose of adjusting the interstage gain is achieved,and as can be seen from the formulas (1) and (4), the calibration error mainly comes from the matching of the capacitor and the magnitude of the open-loop gain A of the operational amplifier, and both of the calibration error and the open-loop gain A do not change with the working condition, and the calibration can be realized by a foreground calibration method.

The invention has the beneficial effects that: the invention overcomes the defects of complex traditional algorithm and low precision in a high-speed high-precision production line ADC, the algorithm logic can be realized only by storing, subtracting and comparing, and the interstage gain is obtained by taking the value of the same section as the difference, thereby avoiding the influence of other errors to a great extent; the output code storage module, the output code subtraction module, the difference value comparison module and the feedback capacitance control module can be directly integrated into a chip to be realized, and can also be realized outside the chip through an FPGA (field programmable gate array) board, so that the chip area is saved, the automatic start and automatic stop can be realized, the characteristics of high efficiency, rapidness, flexibility and accuracy are realized, and the method is relatively suitable for calibrating the high-speed high-precision assembly line ADC.

Drawings

In order that the present invention may be more readily and clearly understood, a more particular description of the invention briefly described above will be rendered by reference to specific embodiments that are illustrated in the appended drawings.

FIG. 1(a) is an overall system architecture diagram of a conventional pipelined ADC;

FIG. 1(b) is an overall system architecture of the present invention;

FIG. 2(a) is a schematic circuit diagram of a pipeline sub-stage multiplication digital-to-analog converter MDAC in a conventional pipeline ADC;

FIG. 2(b) is a schematic diagram of the circuit structure of the pipeline sub-stage multiplication digital-to-analog converter MDAC of the present invention;

FIG. 3 is a schematic diagram of the operation of the output code storage module, the output code subtraction module, the difference comparison module, the feedback capacitance control module, and the input voltage selection module according to the present invention;

FIG. 4(a) is an ideal transmission curve diagram of a pipeline sub-stage multiplication digital-to-analog converter MDAC;

FIG. 4(b) is a diagram of an ideal transmission curve fitting curve of a pipeline sub-stage multiplication digital-to-analog converter MDAC;

FIG. 4(c) is an ideal transmission curve fitting curve of a pipeline sub-stage multiplication digital-to-analog converter MDAC considering capacitance mismatch;

FIG. 5 is a flow chart of a calibration method of the present invention.

Detailed Description

As shown in fig. 1(b), the high-precision pipeline ADC according to the present invention includes a main circuit, an output code storage module, an output code subtraction module, a difference comparison module, a feedback capacitance control module, and an input voltage selection module;

the main circuit comprises i pipeline sub-stages, a flash memory type ADC (FLASH ADC) of the last stage, a delay in-phase module and a redundancy calibration module; wherein, the input end of the first pipeline substage is connected with the input signal V_inThe input end of the second pipeline sub-stage is connected with the analog output end of the first pipeline sub-stage, and the input signal of the second pipeline sub-stage is the output signal of the first pipeline sub-stage; the input end of the third pipeline sub-stage is connected with the analog output end of the second pipeline sub-stage, the input signal of the third pipeline sub-stage is the output signal of the second pipeline sub-stage, and the analogy is repeated until the ith sub-stage, the analog output end of the ith sub-stage is connected with the input end of the last flash memory type ADC, the input end of the delay in-phase module is respectively connected with the digital output ends of each pipeline sub-stage and the last flash memory type ADC, and the output codes of each pipeline sub-stage and the output codes of the last flash memory type ADC are received and output to the redundancy calibration module; the input end of the redundancy calibration module is connected with the output end of the delay in-phase module, calibrates the received output code and outputs a digital output code D of the pipeline ADC_out；

Each sub-stage of the production line consists of a multiplying digital-to-analog converter (MDAC) module and an auxiliary analog-to-digital converter (SubADC) module which simultaneously receive an input signal V_inThe auxiliary analog-to-digital converter SubADC module controls the multiplication digital-to-analog converter MDAC module to generate analog output which is transmitted to the next pipeline sub-stage, and the auxiliary analog-to-digital converter SubADC module generates digital output which is transmitted to the delay in-phase module;

the feedback capacitance control module generates a control signal according to the difference comparison result, controls a feedback capacitance in the multiplication digital-to-analog converter MDAC, and adjusts or solidifies the feedback capacitance; if the feedback capacitor is adjusted, repeating the calibration process, and if the feedback capacitor is solidified, finishing foreground calibration by the assembly line ADC and starting to normally receive the input signal;

the input voltage selection module is controlled by the difference comparison module, receives a difference comparison result transmitted by the difference comparison module, continues to perform calibration if the comparison result indicates that a gain error exists, generates enable signals of the output code storage module, the output code subtraction module, the difference comparison module and the feedback capacitance control module at the moment, controls the calibration to be performed, and ends the calibration if the comparison result indicates that the gain error does not exist, and transmits an external input signal V_inAnd accessing the pipeline ADC, and enabling the pipeline ADC to work normally.

The unit capacitor of the feedback capacitor is divided into a plurality of unit capacitors according to binary weight, the capacitors are added according to application conditions and are respectively controlled to achieve the purpose of increasing or decreasing the feedback capacitor. The circuit structure of the multiplying digital-to-analog converter MDAC is shown in fig. 2 (b).

Wherein C is_{x_1}，C_{x_2}，……，C_{x_n}Is equal to C_xAnd C is_{f_k}＝[(N-1)/N]*C_f，C_{f_k-1}＝C_f/(N*2⁰)，C_{f_k-2}＝C_f/(N*2¹)，……，C_{f_0}＝C_f/(N*2^k-1) In which C is_{f_k-1}，C_{f_k-2}，……，C_{f_0}For adjustable feedback capacitance, C_fThe feedback capacitance of the circuit to be accessed by the traditional pipeline ADC is large.

In FIG. 2(b), k is the binary digit of the digital code Dctr outputted by the feedback capacitance control module, and N is the adjustable feedback capacitance and the effective feedback capacitance C_{f_eq}The proportionality coefficient can be set according to the requirement. Theoretically, the larger N is, the smaller the adjustable feedback capacitance is, the smaller the adjustment amplitude of the inter-stage gain of the circuit is, the larger k is, the better k is, the larger k is, the smaller the minimum unit of the adjustable feedback capacitance, i.e., the minimum calibration step size is, the smaller the minimum calibration step size is, the more accurate the foreground calibration algorithm is, but the smaller capacitance is difficult to accurately realize, so the compromise between the capacitance precision and the precision of the foreground calibration algorithm is required.

In FIG. 2(b), C_{x_1}，C_{x_2}，……，C_{x_n}In practice, controlled by three switches: respectively control C_{x_1}，C_{x_2}，……，C_{x_n}One of the switches is connected with the lower electrode plate of the capacitor and the input signal V_inThe switch is a sampling switch which is clocked by a sampling clock

Controlling; respectively control C_{x_1}，C_{x_2}，……，C_{x_n}The other switch of the switch (2) can be called as an operation switch, and one end of the operation switch is connected with a reference voltage +/-V_refOne end of the input end is connected with a capacitor lower stage plate and is coded by the output code D of the Sub ADC_iControl and amplification of clock with residual error

The phases are the same; finally, C_{x_1}，C_{x_2}，……，C_{x_n}All connected to the same switch, here called earthing switch, one end of which is connected to C_{x_1}，C_{x_2}，……，C_{x_n}The other end of the upper board is connected with a reference voltage V_icmIs connected toGround switch sampled clock

The control is carried out by controlling the temperature of the air conditioner,

and

going low in phase but earlier causes the switch to open.

In FIG. 2(b), C_{f_k-1}，C_{f_k}-2，……，C_{f_0}In fact, the three switches respectively control C_{f_k-1}，C_{f_k-2}，……，C_{f_0}One of the switches of (2) is connected to an input signal V_inOne end of the sampling switch is connected with a lower polar plate of a capacitor, the switch is also a sampling switch and is subjected to a sampling clock

Control, but is different from C_{x_1}，C_{x_2}，……，C_{x_n}And C_{f_k}Is C_{f_k-1}，C_{f_k-2}，……，C_{f_0}The upper plate of the switch is connected with another switch, namely a feedback capacitance adjusting switch, and one end of the switch is connected with a terminal C_{f_k-1}，C_{f_k}-2，……，C_{f_0}The other end of the upper polar plate is connected with the upper polar plates of all other capacitors, the feedback capacitor adjusting switch is controlled by the output digital code Dctr of the feedback capacitor adjusting module, wherein the kth position of the feedback capacitor C can be adjusted_{f_k-1}Controlled by the kth bit of the digital code Dctr output by the feedback capacitance adjustment module, namely Dctr _ k-1, wherein the kth bit can adjust the feedback capacitance C_{f_k-2}Controlled by the k-1 th bit of the digital code Dctr output by the feedback capacitance adjusting module, namely Dctr _ k-2, and so on, the jth adjustable feedback capacitance C_{f_j}Controlled by the j-1 th bit of the digital code Dctr output by the feedback capacitance adjusting module, namely Dctr _ j-1, if the feedback capacitance adjusting switch is switched off, C_{f_k-1}，C_{f_k}-2，……，C_{f_0}The upper polar plate is suspended, does not participate in the sampling of the input signal, and is not connected into a loop, so that the circuit is disconnected at the momentThe capacitance corresponding to the open feedback capacitance adjusting switch is inactive in the circuit, and the feedback capacitance adjusting module adjusts the effective feedback capacitance C of the access circuit through the feedback capacitance adjusting switch_{f_eq}Of the value of (c); c in FIG. 2(b)_{f_k-1}，C_{f_k}-2，……，C_{f_0}A third switch connected to the capacitor lower stage and the operational amplifier output terminal, referred to as loop switch, and receiving the residual amplified clock

And (4) controlling.

In FIG. 2(b), the OPA is an operational amplifier, and the negative input terminals of the operational amplifier are respectively connected with the capacitors C_{x_1}、C_{x_2}、……、C_{x_n}、C_{f_k}Upper polar plate, positive input end grounded GND, output end V_outiAnd a loop switch is connected.

In FIG. 2(b), C_{f_k}Controlled by three switches, two of which are the same as the sampling switch and the grounding switch and are also called the sampling switch and the grounding switch respectively, and the third switch is the same as the loop switch and is also the loop switch.

As can be seen from fig. 1(b), the pipeline ADC main circuit will output the total digital output code to the output code storage module, and as shown in fig. 3, two storage modules are provided in the output code storage module, and the output code storage array 1 is for D_out1Storing, outputting coded storage array 1 to D_out2And storing, and outputting the stored codes to the output code subtraction module of the next stage through two output ports. The output coding storage module is provided with four main input ports, wherein CLK is a system clock; d_outThe port is used for directly receiving the total digital output code of the pipeline ADC main circuit; en _ r1 and En _ r2 are enable signals for the output code storage array 1 and the output code storage array 2, respectively. When En _ r1 is enabled, then storage output code storage array 1 is paired with D_outIs stored as D_out1. If En _ r2 is enabled, then the storage output encoded storage array 2 is stored for D_outIs stored as D_out2. En _ r1 should be at the inputV_in1Time enabled, En _ r2 should be at input V_in2Time-enable, ensuring that both storage arrays store the correct value, neither En _ r1 nor En _ r2 is enabled, output code storage array 1 and output code storage array 2 perform a latch operation.

As shown in fig. 3, the output encoding subtraction module also has four main input ports, where CLK is the system clock; en _ su is an enabling port of the slave, the output coding subtraction module performs subtraction only when En _ su is enabled, and the other time is in a latch holding state, so that the influence of unnecessary values input to the rear stage on algorithm operation is avoided, and meanwhile, the rear stage can stably receive input signals; one of the other two ports is used for receiving D output by the output code storage module_out1And the other D is used for receiving the output of the output code storage module_out2When enabled and receiving the input signal, this module executes D_out1Decrease D_out2And outputs the subtraction result Δ D_outFor use by the difference comparison module.

As shown in fig. 3, the difference comparison module has three main input ports, where CLK is the system clock; the second is an enabling end controlled by En _ cmp, when the enabling signal is not enabled, the difference comparison module executes latch operation, and when the enabling signal is enabled, the difference comparison module executes comparison operation; the other input end receives the output signal Delta D of the output coding subtraction module_outThe difference comparison module compares the delta D_outWith Δ D stored in the difference comparison module beforehand_{out_id}Making a comparison if Δ D_outIs equal to Δ D_{out_id}If there is no gain error, D _ equ is high level, and D _ big and D _ small are low level; if Δ D_outGreater than Δ D_{out_id}If the inter-stage gain is larger, the D _ big is at a high level, and the D _ equ and the D _ small are at a low level; if Δ D_outLess than Δ D_{out_id}That is, if the inter-stage gain is small, D _ small is at a high level, and D _ equ and D _ big are at a low level. And three output ports of the difference comparison module respectively send D _ small, D _ equ and D _ big to the feedback capacitor control module and the input voltage selection module to control the feedback capacitor control module and the input voltage selection module.

As shown in figure 3 of the drawings,the feedback capacitance control module functions like a counter and has five main input ports, wherein CLK is a system clock, En _ ctr receives an enable signal, and the other three receive three input signals, D _ small, D _ equ and D _ big. The feedback capacitance control module has k bit outputs, namely Dctr _ k-1, Dctr _ k-2, … … and Dctr _0, and is connected into the multiplication digital-to-analog converter MDAC to control the feedback capacitance adjusting switch. When D _ equ is at a high level and D _ big and D _ small are at a low level, no gain error exists, and the output of the feedback capacitance control module is kept unchanged at the moment; when D _ big is high level and D _ equ and D _ small are low level, the inter-stage gain is large, and the effective feedback capacitor C should be reduced at this time_{f_eq}The feedback capacitance control module performs 1 reduction operation to reduce the original latched code by 1, corresponding to the effective feedback capacitance C_{f_eq}Decreasing by one minimum step size; when D _ small is at high level and D _ equ and D _ big are at low level, the inter-stage gain is small, and the effective feedback capacitor C should be increased_{f_eq}The feedback capacitance control module adds 1 to the original latched code and adds 1 to the original code corresponding to the effective feedback capacitance C_{f_eq}One minimum step size is increased.

As shown in fig. 3, the input voltage selection module has eight main input ports, one of which is a calibration method enable signal En _ cal, when En _ cal is not enabled, the calibration method does not work, when En _ cal is enabled, the calibration flow starts; two of the system clocks CLK, the other three of which receive three input signals D _ small, D _ equ, D _ big; the last three are connected with three input signals V_in，V_in1And V_in2。V_inIs an input signal, V, to be connected when the pipeline ADC is in normal operation_in1Is the DC differential mode input voltage, V, required in step 1_in2The required direct current differential mode input voltage in the step 2 is connected into an input voltage selection module, and the input voltage selectively connects the input voltage into a pipeline ADC main circuit, namely V_inS. When the calibration method works, the input voltage selection module respectively performs the steps of the output code storage module, the output code subtraction module, the difference comparison module, the inverse code comparison module and the inverse code selection module on the basis of the steps of the calibration, through enable signals En _ r1, En _ r2, En _ su, En _ cmp and En _ ctrAnd the feed capacitance control module controls.

FIG. 4(a) is an ideal case of a multiplying DAC MDAC transfer curve, where- (3V)_ref)/4，-(V_ref)/4，(V_ref)/4，(3V_ref) And/4, as the discrimination point of the Sub ADC comparator, a folding curve is arranged between the discrimination points of the two comparators, and corresponds to an output code D of the Sub ADC_i. V of the invention_in1And V_in2Should be in the same output coding section of Sub ADC and V_in1Greater than V_in2。

Fig. 4(b) is a transmission curve that is ideally fitted to a straight line by the multiplying dac MDAC transmission curve, and fig. 4(c) is a transmission curve that is fitted to a straight line by the multiplying dac MDAC transmission curve in the presence of capacitance mismatch. If get V_in1And V_in3As can be seen from FIG. 4(b), in actuality, V_in1And V_in3The corresponding total digital output code is subtracted and divided by V_in1And V_in3The transmission curve slope, i.e., the inter-stage gain, can also be determined from the difference. However, as shown in fig. 4(c), in the presence of capacitance mismatch, a linear transmission curve is fitted, and an Error _ cap exists between each comparator discrimination section, which causes an Error step Error _ cap to be included in the obtained total digital output coding difference value, so that the slope calculation is erroneous, and therefore, two dc common mode input voltages of the present invention need to be taken in the same output coding section of the Sub ADC, thereby avoiding the influence of other errors on the result. At the same time, V_in1Is greater than V_in2This is to prevent negative results, facilitate calculation, and V_in1And V_in2The difference should not be too small, and quantization errors are easily caused by too small a difference.

The following describes the working flow of the high-precision pipelined ADC front-end calibration method in detail with reference to fig. 5:

and accessing the pipeline ADC into a test environment, enabling En _ cal and starting a calibration process.

In a first step, an input voltage selection module selects V_in1Input pipeline ADC main circuit, thisThe time output code storage module, the output code subtraction module, the difference comparison module and the feedback capacitance control module are all disabled.

Second, after several cycles, the pipeline ADC completes quantization and outputs the total digital output code D_out1To the output code storage module, the input voltage selection module enables En _ r1, and the output code storage array 1 in the output code storage module outputs the code D to the total number of the pipeline ADC_out1Storing is performed while none of the other signals En _ r2, En _ su, En _ cmp, En _ ctr are enabled.

Thirdly, the input voltage selection module selects V_in2The input flow line ADC main circuit, output code storage module, output code subtraction module, difference comparison module, feedback capacitance control module all do not enable this moment.

Fourthly, after a plurality of periods, the assembly line ADC completes the quantization and outputs the total digital output code D_out2To the output code storage module, the input voltage selection module enables En _ r2, and the output code storage array 2 in the output code storage module outputs the code D to the total number of the pipeline ADC_out2Storing is performed while none of the other signals En _ r1, En _ su, En _ cmp, En _ ctr are enabled.

Fifthly, the input voltage selection module selects the En _ su enable, the output code subtraction module works, and two total digital output codes D latched by the output code storage module are output_out1And D_out2Performing subtraction operation and obtaining difference result delta D_outLatched, and the other signals En _ r1, En _ r2, En _ cmp, En _ ctr are not enabled.

Sixthly, the input voltage selection module selects En _ cmp to be enabled, the difference value comparison module works, the output coding subtraction module is latched and the input subtraction result delta D is input_outDifference result Delta D from the ideal case_{out_id}Making a comparison if Δ D_outIs equal to Δ D_{out_id}If there is no gain error, D _ equ is high level, and D _ big and D _ small are low level; if Δ D_outGreater than Δ D_{out_id}I.e., the inter-stage gain is larger, D _ big is high level,d _ equ and D _ small are low level; if Δ D_outLess than Δ D_{out_id}That is, if the inter-stage gain is small, D _ small is at a high level, and D _ equ and D _ big are at a low level. At this time, none of the other signals En _ r1, En _ r2, En _ su, En _ ctr are enabled.

And seventhly, enabling the En _ ctr by selecting the input voltage selection module, enabling the feedback capacitance control module to work, and explaining the working process by taking k as an example of 3. If k is 3, the feedback capacitance control module outputs the three-bit codes Dctr _2, Dctr _1, Dctr _0, i.e., Dctr. In the initial state, when Dctr is 100, the output signal Dctr _2 is 1, Dctr _1 is 0, Dctr _0 is 0, the feedback capacitance switch is turned on at high level, and then the effective feedback capacitance C connected into the circuit is turned on at this time_{f_eq}＝C_{f_3}+C_{f_2}＝[(N-1)/N]*C_f+C_f/(N*2⁰)＝C_fThe other signals En _ r1, En _ r2, En _ cmp, En _ su are not enabled at this time, as the feedback capacitance of the circuit to which the conventional pipelined ADC should be connected.

From the equation (4), if there is no gain error, the inter-stage gain is approximately equal to a constant, i.e., C_s/C_fHowever, due to uncertainty in random and systematic errors, the actual inter-stage gain may be greater than the constant C_s/C_fMay be smaller than the constant C_s/C_fBy comparing Δ D_outDelta D of_{out_id}The magnitude relationship determines the magnitude relationship of the inter-stage gains, which is described above and will not be described herein.

Therefore, if the signal input by the difference comparison module is D _ equ is high level and D _ big and D _ small are low level, the actual interstage gain is equal to the ideal interstage gain, and the calibration is finished; if D _ big is high level and D _ equ, D _ small is low level, the inter-stage gain is large, the feedback capacitance control module reduces 1 to Dctr, and finally the output code Dctr is 011, i.e. Dctr _2 is 0, Dctr _1 is 1, Dctr _0 is 1, at this time, the effective feedback capacitance C connected to the circuit is_{f_eq}＝C_{f_3}+C_{f_1}+C_{f_0}＝[(N-1)/N]*C_f+C_f/(N*2¹)+C_f/(N*2²)＝[(4N-1]/4N]C_fSlightly smaller than C_fMixing C with_{f_eq}Reducing; if D _ small is high level and D _ equ, D _ big are low level, the inter-stage gain is small, the feedback capacitance control module adds 1 to Dctr, and finally the output code Dctr is 101, i.e. Dctr _2 is 1, Dctr _1 is 0, Dctr _0 is 1, at this time, the effective feedback capacitance C in the access circuit is accessed_{f_eq}＝C_{f_3}+C_{f_2}+C_{f_0}＝[(N-1)/N]*C_f+C_f/(N*2⁰)+C_f/(N*2²)＝[(4N+1]/4N]C_fSlightly greater than C_fMixing C with_{f_eq}And (5) adjusting the size to be larger.

Eighthly, the input voltage selection module selects to disable En _ ctr, so that the output code of the feedback capacitor control module is latched, the first step is returned, detection is carried out again until D _ equ is at a high level and D _ big and D _ small are at low levels, calibration is finished, the input voltage selection module enables En _ r1, En _ r2, En _ cmp, En _ su and En _ ctr to be disabled, all signals are latched, and at the moment, C _ r _ ctr is enabled_{f_eq}Is no longer changed, indicating that the calibration is complete.

In summary, the invention can be applied to each pipeline sub-stage of the pipeline ADC, performs gain calibration on each sub-stage of the pipeline ADC, improves the disadvantages of complex algorithm and low precision in the high-speed high-precision pipeline ADC, can realize algorithm logic only by storing, subtracting and comparing, and obtains inter-stage gain by making difference between values of the same section, thereby avoiding the influence of other errors to a great extent.

The above description is only a preferred embodiment of the present invention, and is not intended to limit the present invention, and all equivalent variations made by using the contents of the present specification and the drawings are within the protection scope of the present invention.

Claims

1. A high-precision assembly line ADC is characterized by comprising a main circuit, an output code storage module, an output code subtraction module, a difference value comparison module, a feedback capacitance control module and an input voltage selection module;

the input voltage selection module receives the output result of the difference comparison module and generates enable signals of the output code storage module, the output code subtraction module, the difference comparison module and the feedback capacitance control module according to the output result so as to control the calibration or enable the pipeline ADC to work normally.

2. The high-precision pipelined ADC of claim 1, wherein the main body circuit comprises a plurality of pipelined sub-stages, a flash ADC of a last stage, a delay in-phase module, and a redundancy calibration module;

the delay in-phase module receives the output codes of the sub-stages of each production line and the output codes of the flash memory type ADC of the last stage, and outputs the output codes to the redundancy calibration module; the redundancy calibration module calibrates the received output code and outputs a pipeline ADC total digital output code D_out。

3. A high precision pipeline ADC according to claim 2 wherein each pipeline sub-stage is formed by a multiplying digital to analog converter MDAC module and an auxiliary analog to digital converter subcodc module which simultaneously receive the input signal V_inAnd the auxiliary analog-to-digital converter SubADC module controls the multiplication digital-to-analog converter MDAC module to generate analog output and transmit the analog output to the next pipeline sub-stage, and the auxiliary analog-to-digital converter SubADC module generates digital output and transmits the digital output to the delay in-phase module.

4. A method for calibrating a high precision pipelined ADC front-end according to any one of claims 1 to 3, comprising the steps of:

and step 3: according to transmission curves of all levels and a redundancy addition calibration algorithm, calculating the current V through a manual theory_in1And V_in2Ideal total digital output code D corresponding to the pipeline ADC when respectively input_{out1_id}And D_{out2_id}Outputting the ideal total number of digits to code D_{out1_id}And D_{out2_id}Make a difference, i.e. D_{out1_id}-D_{out2_id}＝ΔD_{out_id}Resulting in the ideal case of two total digital output encodings of the pipelined ADCDifference Δ D of_{out_id}And stored in the difference comparison module;

and 4, step 4: the output coding subtraction module stores the pipeline ADC obtained in the step 1 and the step 2 in two digital outputs D in the output coding storage module_out1And D_out2By subtraction, i.e. D_out1-D_out2＝ΔD_outObtaining a difference result Delta D_outI.e. in practice the pipeline ADCs input V separately_in1And V_in2Outputting the coded difference value by total digital time;

if Δ D_out>ΔD_{out_id}At this time, the actual interstage gain of the pipeline ADC is larger than the ideal interstage gain, and the feedback capacitance control module enables the effective feedback capacitance C to be larger than the ideal interstage gain according to an analog domain calculation formula of the actual interstage gain of the pipeline ADC_{f_eq}Reducing the interstage gain, and then repeating the step 1, the step 2 and the step 4 until the actual interstage gain is equal to the ideal interstage gain;

if Δ D_out<ΔD_{out_id}At this time, the actual interstage gain of the pipeline ADC is smaller than the ideal interstage gain, and the feedback capacitance control module enables the effective feedback capacitance C to be achieved according to the analog domain calculation formula of the actual interstage gain of the pipeline ADC_{f_eq}Getting larger to make the interstage gain larger, and then repeating the step 1, the step 2 and the step 4 until the interstage gain is equal to the ideal interstage gain;

5. The method of claim 4, wherein the two DC differential mode voltage input signals V are used as the front-end calibration of the pipelined ADC_in1And V_in2In the same section of the transmission curve, and V_in1Greater than V_in2。

6. The method as claimed in claim 4, wherein the ideal interstage gain of the pipeline ADC is StageGain_idIs calculated by the formula

7. The method for calibrating the front end of the pipeline ADC with high precision according to claim 4, wherein the calculation formula of the actual interstage gain StageGain of the pipeline ADC is as follows:

8. the method according to claim 4, wherein the analog domain calculation formula of the actual interstage gain of the pipeline ADC is as follows:

wherein A is the open-loop gain of the operational amplifier in the pipeline ADC sampling and holding circuit, and C_sThe total sampling capacitance of the pipeline ADC sampling and holding circuit at a sampling phase is obtained; beta is a closed loop feedback factor of the pipeline ADC sampling and holding circuit, namely beta is C_{f_eq}/C_s，C_{f_eq}Is an effective feedback capacitance C when the pipeline ADC sample-and-hold circuit is in an amplification phase_xA capacitor C connected to the reference voltage when the pipeline ADC sample-and-hold circuit is in the amplification phase_s＝C_{f_eq}+C_x，K＝C_x/C_{f_eq}。