CN117650788A

CN117650788A - Successive approximation cyclic ADC (analog-to-digital converter) and signal conversion method and system thereof

Info

Publication number: CN117650788A
Application number: CN202311344728.1A
Authority: CN
Inventors: 宋贺伦; 龚精武; 茹占强; 程素珍
Original assignee: Suzhou Institute of Nano Tech and Nano Bionics of CAS
Current assignee: Suzhou Institute of Nano Tech and Nano Bionics of CAS
Priority date: 2023-10-17
Filing date: 2023-10-17
Publication date: 2024-03-05

Abstract

The invention discloses a successive approximation cyclic ADC (analog-to-digital converter) and a signal conversion method and system thereof, wherein the successive approximation cyclic ADC comprises a comparator, a capacitance unit, a residual sampling capacitance and an amplifier; the first end of the capacitor unit is connected with the second input end of the comparator, and the second end of the capacitor unit is connected with the input voltage, the reference voltage and the ground voltage through the first control switch. According to the successive approximation cyclic ADC, the signal conversion method and the signal conversion system thereof, the amplifier of the successive approximation cyclic ADC is in the off state in the quantization stage of the capacitor unit, so that the power consumption is greatly reduced. The successive approximation cyclic ADC provided by the invention can generate multi-bit digital codes in one cycle, so that the number of times of participation of the amplifier in work is greatly reduced, the single conversion speed is improved, and the overall power consumption is also reduced. The successive approximation cyclic ADC system based on the split structure can eliminate the mismatch of the capacitor unit and the limited gain error of the amplifier by using a background calibration algorithm, and improves the accuracy of the ADC.

Description

Successive approximation cyclic ADC (analog-to-digital converter) and signal conversion method and system thereof

Technical Field

The invention relates to the field of digital-analog hybrid circuits, in particular to a successive approximation cyclic ADC and a signal conversion method and system thereof.

Background

A Cyclic analog-to-digital converter (Cyclic ADC) is a converter architecture that folds multiple stages of a pipelined ADC into one stage; pipelined ADCs process in parallel by dividing the conversion of analog input into multiple stages, with very high throughput compared to other architectures, but with excessive power consumption and taking up excessive area compared to cyclic analog-to-digital converters.

In a Cyclic ADC, multiple stages are folded into one stage, thereby reducing chip area and significantly reducing power consumption. However, the Cyclic ADC has a disadvantage in that the processing of the analog input requires a plurality of cycles, the remaining residual voltage of the upper cycle is processed in this cycle, and the amplified residual voltage is passed to the next cycle after the conversion is completed, thereby reducing the conversion speed. Furthermore, each time the residual voltage is amplified, the amplifier needs to participate, and the setup time of the amplifier limits the speed of a single transition. To increase the switching speed of the amplifier, the amplifier consumes excessive power.

As processes progress and transistor feature sizes shrink, successive approximation analog-to-digital converters (SAR ADCs) are widely used due to their digitizing characteristics. The SAR ADC gradually approximates the input signal by converting in a gradual flip from the high-order capacitance to the low-order capacitance. Because of this characteristic, the SAR ADC requires only a small amount of analog circuits, and does not require an amplifier required in the cyclic ADC, thereby further reducing power consumption and improving conversion speed. However, the accuracy of SAR ADC is related to the number of capacitors used and the size of the cell capacitance. In applications requiring high accuracy, a larger unit capacitance is required to counteract the effects of the capacitance mismatch. Thus, SAR ADCs occupy more area than Cyclic ADCs.

Because of non-ideal factors in the circuit, such as limited gain and input offset of the amplifier, capacitance mismatch, input offset of the comparator, thermal noise of the sampling switch, and the like, the precision of the SAR ADC or the Cyclic ADC is often limited to 10-12 bits, which is also at the cost of complexity of the circuit, such as increasing the open loop gain of the amplifier to reduce the gain error of the amplifier, increasing the capacitance size to offset the capacitance mismatch, and the like. The current mainstream high-precision ADCs therefore often have calibration circuitry to reduce the complexity of the analog circuitry. The calibration technology is mainly divided into four types, namely analog foreground calibration, analog background calibration, digital foreground calibration and digital background calibration, and the digital background calibration is capable of tracking PVT changes without interrupting the normal working state of the ADC, so that the advantages of almost no need of changing an analog circuit are paid attention to.

The information disclosed in this background section is only for enhancement of understanding of the general background of the invention and should not be taken as an acknowledgement or any form of suggestion that this information forms the prior art already known to a person of ordinary skill in the art.

Disclosure of Invention

The invention aims to provide a successive approximation cyclic ADC which can reduce the participation times of an amplifier, improve the conversion speed and effectively reduce the chip area by amplifying residual voltage and multiplexing capacitance.

To achieve the above object, an embodiment of the present invention provides a successive approximation cyclic ADC including:

the comparator is provided with a first input end, a second input end and an output end, wherein the first input end of the comparator is connected with a common mode voltage;

the first ends of the capacitor units are connected with the second input end of the comparator, the first ends of the capacitor units are connected with the first ends of the first switches, the second ends of the first switches are connected with the common mode voltage, and the second ends of the capacitor units are connected with the input voltage, the reference voltage and the ground voltage through the first control switch;

the first end of the residual sampling capacitor is connected with the first end of the second switch, the second end of the second switch is connected with the first end of the capacitor unit, and the second end of the residual sampling capacitor is connected with the common-mode voltage through the second control switch; and

the amplifier is provided with a first input end, a second input end and an output end, wherein the first input end of the amplifier is connected with the first end of the residual sampling capacitor, the second input end of the amplifier is connected with the common-mode voltage, and the output end of the amplifier is connected with the second end of the capacitor unit through a third switch.

In one or more embodiments of the present invention, the successive approximation cyclic ADC further comprises a fourth switch, a first terminal of the fourth switch being connected to the first terminal of the residual sampling capacitor and to the first input terminal of the amplifier, and a second terminal of the fourth switch being connected to the common mode voltage.

In one or more embodiments of the invention, the capacitive unit further comprises a redundant capacitive unit.

In one or more embodiments of the invention, the successive approximation cyclic ADC further comprises a logic control module that generates a control signal for controlling the first control switch based on the output signal of the comparator.

In one or more embodiments of the present invention, the successive approximation cyclic ADC further includes a fifth switch, a first end of the fifth switch being connected to the first control switch, a second end of the fifth switch being connected to the input voltage, a first end of the third switch being connected to the output of the amplifier, and a second end of the third switch being connected to the first end of the fifth switch.

The invention also discloses a successive approximation cyclic ADC system, which comprises: the first successive approximation cyclic ADC, the second successive approximation cyclic ADC, the first weight calculation module, the second weight calculation module, the first calculation module and the second calculation module;

the first successive approximation cyclic ADC and the second successive approximation cyclic ADC are both connected with input voltage, the second end of a residual sampling capacitor of the first successive approximation cyclic ADC is connected with a first offset voltage through a second control switch, the second end of the residual sampling capacitor of the second successive approximation cyclic ADC is connected with a second offset voltage through a second control switch, the first weight calculation module is used for carrying out weight calculation on a digital code output by the first successive approximation cyclic ADC, the second weight calculation module is used for carrying out weight calculation on a digital code output by the second successive approximation cyclic ADC, the first calculation module obtains an error signal based on the first weight calculation module and the second weight calculation module and feeds the error signal back to the first weight calculation module and the second weight calculation module to adjust weight, and the second calculation module is used for carrying out operation on signals output by the first weight calculation module and the second weight calculation module to obtain a result signal.

The invention also discloses a signal conversion method of the successive approximation cyclic ADC, which comprises the following steps:

in the sampling stage, a first end of a capacitor unit is communicated with a common mode voltage, a second end of the capacitor unit is communicated with an input voltage, a first end of a residual sampling capacitor is communicated with the first end of the capacitor unit, a second end of the residual sampling capacitor is connected with the common mode voltage, and the input voltage is sampled through the capacitor unit;

in the quantization stage, disconnecting the first end of the capacitor unit from the common mode voltage, disconnecting the second end of the capacitor unit from the input voltage, alternately connecting the second ends of the capacitor units with the reference voltage, connecting the rest capacitor units with the ground voltage, comparing the voltage at the first end of the capacitor unit with the common mode voltage through a comparator, outputting the voltage, and storing the residual voltage through a residual sampling capacitor;

in a residual sampling stage, disconnecting a first end of a capacitor unit from a first end of a residual sampling capacitor, amplifying residual voltage through an amplifier, communicating an output end of the amplifier with a second end of the capacitor unit, communicating the first end of the capacitor unit with a common-mode voltage, and sampling the amplified residual voltage through the capacitor unit;

in the residual quantization stage, the first end of each capacitor unit is disconnected from the common mode voltage, the second end of each capacitor unit is alternately communicated with the reference voltage, the rest capacitor units are communicated with the ground voltage, and the voltage at the first end of each capacitor unit is compared with the common mode voltage through a comparator and output.

in the sampling stage, a first end of a capacitor unit is communicated with a common mode voltage, a second end of the capacitor unit is communicated with an input voltage, a first end of a residual sampling capacitor is disconnected with the first end of the capacitor unit, the first end of the residual sampling capacitor and the second end of the residual sampling capacitor are connected with the common mode voltage so as to reset the residual sampling capacitor, and the input voltage is sampled through the capacitor unit;

in the quantization stage, disconnecting the first end of the capacitor unit from the common mode voltage, disconnecting the second end of the capacitor unit from the input voltage, alternately connecting the second ends of the capacitor units with the reference voltage, connecting the rest capacitor units with the ground voltage, and comparing the voltage at the first end of the capacitor unit with the common mode voltage through a comparator to output;

in a residual sampling stage, disconnecting a first end of a residual sampling capacitor from a common mode voltage, communicating the first end of a capacitor unit with the first end of the residual sampling capacitor to store residual voltage, disconnecting the first end of the capacitor unit from the first end of the residual sampling capacitor after storage, amplifying the residual voltage through an amplifier, communicating an output end of the amplifier with a second end of the capacitor unit, communicating the first end of the capacitor unit with the common mode voltage, and sampling the amplified residual voltage through the capacitor unit;

In one or more embodiments of the invention, after the capacitor unit samples the amplified residual voltage, the second terminal of the residual sampling capacitor is connected to the common mode voltage.

In one or more embodiments of the present invention, the redundant capacitor unit is connected to a ground voltage in a quantization phase and a residual quantization phase.

Compared with the prior art, according to the successive approximation cyclic ADC, the signal conversion method and the signal conversion system thereof, the amplifier of the successive approximation cyclic ADC can be in the off state in the quantization stage of the capacitor unit, so that the power consumption is greatly reduced.

The successive approximation cyclic ADC provided by the invention can save a large amount of area through multiplexing the capacitance unit.

The successive approximation cyclic ADC provided by the invention can generate multi-bit digital codes by one cycle, so that the number of times of participation of an amplifier in work is greatly reduced, the single conversion speed is improved, and the overall power consumption is reduced, so that compared with the traditional cyclic ADC, the successive approximation cyclic ADC provided by the invention is improved in speed.

The successive approximation cyclic ADC system based on the split structure can eliminate the mismatch of the capacitor unit and the limited gain error of the amplifier by using a background calibration algorithm, and improves the accuracy of the ADC.

Drawings

Fig. 1 is a circuit schematic of a successive approximation cyclic ADC according to an embodiment of the invention.

Fig. 2 is a conversion flow diagram of the successive approximation cyclic ADC of fig. 1.

Fig. 3 is a schematic circuit diagram of a successive approximation cyclic ADC with a fourth switch added according to an embodiment of the invention.

Fig. 4 is a conversion flow diagram of the successive approximation cyclic ADC in fig. 3.

Fig. 5 is a circuit schematic of a successive approximation cyclic ADC system according to an embodiment of the invention.

FIG. 6 is a graph comparing residual curves with and without inter-stage redundancy in accordance with an embodiment of the present invention.

FIG. 7 is a graph comparing incremental linear systems with nonlinear systems after adding input offsets in accordance with one embodiment of the present invention.

Fig. 8 is a comparison of pre-calibration and post-calibration FFTs (fast fourier transforms) according to an embodiment of the invention.

FIG. 9 is a graph comparing INL (integral nonlinearity) before and after calibration according to an embodiment of the present invention.

Detailed Description

Specific embodiments of the invention will be described in detail below with reference to the drawings, but it should be understood that the scope of the invention is not limited to the specific embodiments.

Throughout the specification and claims, unless explicitly stated otherwise, the term "comprise" or variations thereof such as "comprises" or "comprising", etc. will be understood to include the stated element or component without excluding other elements or components.

As shown in fig. 1, a successive approximation cyclic ADC comprises: the device comprises a comparator CMP, a plurality of capacitor units, a residual sampling capacitor Cinj, an amplifier AMP and a LOGIC control module SAR LOGIC.

The comparator CMP has a first input, a second input and an output, the first input of the comparator CMP being connected to the common mode voltage Vcm. In one embodiment, the first input of the comparator CMP is a negative input and the second input of the comparator CMP is a positive input.

In one embodiment, six capacitor units are provided, which are a first capacitor unit C1, a second capacitor unit C2, a third capacitor unit C3, a fourth capacitor unit C4, a fifth capacitor unit C5 and a sixth capacitor unit C6. The sixth capacitor unit C6 is a high-order capacitor unit. The fifth capacitance unit C5, the fourth capacitance unit C4, the third capacitance unit C3, the second capacitance unit C2 and the first capacitance unit C1 are capacitance units which are gradually reduced.

The capacitor unit further includes a redundant capacitor unit C0. The redundant capacitor unit C0, the first capacitor unit C1, the second capacitor unit C2, the third capacitor unit C3, the fourth capacitor unit C4, the fifth capacitor unit C5 and the sixth capacitor unit C6 form a capacitor array.

The first ends of the capacitor units C6, C5, C4, C3, C2, C1 and C0 are all connected to the second input end of the comparator CMP, and the first ends of the capacitor units C6, C5, C4, C3, C2, C1 and C0 are connected to the first end of the first switch sw1, and the second end of the first switch sw1 is connected to the common-mode voltage Vcm. The second ends of the capacitor units C6, C5, C4, C3, C2, C1, C0 are respectively connected with the input voltage Vin, the reference voltage Vref and the ground voltage GND through corresponding first control switches, seven first control switches are also arranged corresponding to the capacitor units C6, C5, C4, C3, C2, C1, C0, and are respectively first control switches k0, k1, k2, k3, k4, k5 and k6, and each first control switch is provided with a common end connected with the second ends of the corresponding capacitor units C6, C5, C4, C3, C2, C1, C0, and three connection ends respectively connected with the input voltage Vin, the reference voltage Vref and the ground voltage GND.

The number of the capacitors of the capacitor units C6, C5, C4, C3, C2, C1, C0 is to the power i of 2, i being an integer greater than or equal to 0. In one embodiment, the number of capacitors of the sixth capacitor unit C6 is 5 times 2, the number of capacitors of the fifth capacitor unit C5 is 4 times 2, the number of capacitors of the fourth capacitor unit C4 is 3 times 2, the number of capacitors of the third capacitor unit C3 is 2 times 2, the number of capacitors of the second capacitor unit C2 is 1 times 2, the number of capacitors of the first capacitor unit C1 is 0 times 2, the number of capacitors of the redundant capacitor unit C0 is 0 times 2, and from the first capacitor unit C1 to the sixth capacitor unit C6, i are sequentially increased by 1 from 0 to 5.

In an embodiment, a first end of the residual sampling capacitor Cinj is connected to a first end of the second switch sw2, a second end of the second switch sw2 is connected to the first ends of all the capacitor units, and a second end of the residual sampling capacitor Cinj is connected to the common-mode voltage Vcm through the second control switch k 7. The second control switch k7 has a common terminal and three connection terminals, the common terminal of the second control switch k7 is connected to the second terminal of the residual sampling capacitor Cinj, and one connection terminal of the second control switch k7 is connected to the common mode voltage Vcm.

As shown in fig. 1, the amplifier AMP has a first input terminal, a second input terminal, and an output terminal, and in one embodiment, the first input terminal of the amplifier AMP is a negative input terminal, and the second input terminal of the amplifier AMP is a positive input terminal; a first input terminal of the amplifier AMP is connected to a first terminal of the residual sampling capacitor Cinj and a second input terminal of the amplifier AMP is connected to the common mode voltage Vcm.

The output terminal of the amplifier AMP is connected to the second terminal of each capacitive unit through a third switch sw3, and the successive approximation cyclic ADC further comprises a fifth switch sw5. In one embodiment, the output terminal of the amplifier AMP is connected to the first terminal of the third switch sw3, the second terminal of the fifth switch sw5 is connected to the input voltage Vin, and the second terminal of the third switch sw3 is connected to the first terminal of the fifth switch sw5 and the corresponding connection terminals of the first control switches k0, k1, k2, k3, k4, k5 and k 6.

In one embodiment, the LOGIC control module SAR LOGIC generates control signals for controlling the closing and opening of the first control switches k0, k1, k2, k3, k4, k5 and k6 based on the output signal of the comparator CMP, and the first control switches k0, k1, k2, k3, k4, k5 and k6 can be controlled by a switching strategy of VCM-based timing to further reduce power consumption and improve one-bit precision.

As shown in fig. 2, this embodiment further discloses a signal conversion method of a successive approximation cyclic ADC, including:

in the sampling phase, the first end of the capacitor unit C6, C5, C4, C3, C2, C1, C0 is connected to the common mode voltage Vcm (i.e. the first switch sw1 is closed), the second end of the capacitor unit C6, C5, C4, C3, C2, C1, C0 is connected to the input voltage Vin (i.e. the common end of the first control switch k0, k1, k2, k3, k4, k5, k6 is connected to the connection end connected to the input voltage Vin, the fifth switch sw5 is closed), the first end of the residual sampling capacitor Cinj is connected to the first end of the capacitor unit C6, C5, C4, C3, C2, C1, C0 (i.e. the second switch sw2 is closed), the second end of the residual sampling capacitor Cinj is connected to the common mode voltage Vcm (i.e. the common end of the second control switch k7 is connected to the connection end connected to the common mode voltage Vcm), and the input voltage Vin is sampled by the capacitor unit C6, C5, C4, C3, C2, C0.

In the quantization phase, the first ends of the capacitor units C6, C5, C4, C3, C2, C1, C0 are disconnected from the common mode voltage Vcm (i.e. the first switch sw1 is opened), the second ends of the capacitor units C6, C5, C4, C3, C2, C1, C0 are disconnected from the input voltage Vin (i.e. the common ends of the first control switches k0, k1, k2, k3, k4, k5, k6 are disconnected from the connection ends connected to the input voltage Vin, the fifth switch sw5 is opened), the second ends of the capacitor units C6, C5, C4, C3, C2, C1 are alternately connected to the reference voltage Vref, and the second ends of the remaining capacitor units are connected to the ground voltage GND. In the quantization stage, the second terminal of the redundant capacitor unit C0 is always connected to the ground voltage GND. The voltage at the first end of the capacitor unit is compared with the common mode voltage Vcm through a comparator CMP, and the residual voltage is stored through a residual sampling capacitor Cinj.

In one embodiment, when the quantization phase is started after sampling, the first switch sw1 is turned off, and the charges of the upper plates (first ends) of the capacitor units C6, C5, C4, C3, C2, C1, C0 can be expressed asi from 0 to 6 indicates 7 capacitive elements.

In the first quantization stage, the high-order capacitor unit C6 is switched to the reference voltage Vref, and the other capacitor units C5, C4, C3, C2, C1, C0 are connected to GND, at which time the upper plate charges of the capacitor units C6, C5, C4, C3, C2, C1, C0 areAccording to the conservation of charge of the upper plate of the capacitor unit, the voltage Vx of the upper plate of the capacitor unit C6 is:

because the capacitance numbers of the capacitor units C6, C5, C4, C3, C2, and C1 of the successive approximation cycle ADC are in an equal-ratio array with a common ratio of 2, i.e., C (i+1) =2ci (i=1 to 5), i.e., if the capacitance number of the capacitor unit C1 is 1, the capacitance number of the capacitor unit C2 is 2, and the capacitance number of the capacitor unit C3 is 4 …, and the capacitance number of the capacitor unit C6 is 32. The number of the redundant capacitor units C0 is the same as the number of the capacitor units C1, and the redundant capacitor units C0 only participate in sampling, and no switching occurs in the quantization stage. Therefore, in the first quantization phase, the plate voltage on the capacitor unit C6 is:

after the plate voltage build-up on the capacitive cell C6 is completed, a first comparison is started by the comparator CMP. When (when)When greater than 0, the capacitor unit C6 switches back to the ground voltage GND. If->Below zero, the capacitive unit C6 remains unchanged. After the switching of the high-order capacitor unit is completed, the same operation is completed for the next high-order capacitor unit, namely the voltage of the upper polar plate of the capacitor unit is increased +.>And then a comparison is made. And so on until the lowest-order capacitor unit C1 completes the same operation, and the whole conversion process is finished. The residual voltage Vy of the last plate of the final capacitor unit is:

wherein f _i Indicating that the output of the comparator CMP is either 1 or 0.

In the residual sampling phase, the first end of the capacitor unit C6, C5, C4, C3, C2, C1, C0 is disconnected from the first end of the residual sampling capacitor Cinj (i.e. the second switch sw2 is opened), the residual voltage Vy is amplified by the amplifier AMP, the output end of the amplifier AMP is connected to the second end of the capacitor unit (i.e. the third switch sw3 is closed, the common end of the first control switch k0, k1, k2, k3, k4, k5, k6 is closed to the connection end connected to the input voltage Vin), the first end of the capacitor unit C6, C5, C4, C3, C2, C1, C0 is connected to the common mode voltage Vcm (the first switch sw1 is closed), and the amplified residual voltage is sampled by the capacitor unit C6, C5, C4, C3, C2, C1, C0.

In the residual quantization stage, the first ends of the capacitor units C6, C5, C4, C3, C2, C1, C0 are disconnected from the common mode voltage Vcm, the second ends of the capacitor units C6, C5, C4, C3, C2, C1 are alternately connected to the reference voltage Vref, the remaining capacitor units are connected to the ground voltage GND, and the voltage at the first ends of the capacitor units and the common mode voltage Vcm are compared and output through the comparator CMP.

Specifically, in the residual sampling stage, the second switch sw2 is turned off, and the residual voltage Vy is fixed at the negative input end of the amplifier AMP, where the amplified residual voltage Vy is:

then, the third switch sw3 is turned off, and the capacitor units C6, C5, C4, C3, C2, C1, and C0 sample the amplified residual voltages, and after the sampling is completed, a residual quantization phase is started, where the residual quantization phase and the first quantization phase are the same, and are not described herein again.

As shown in fig. 3, the successive approximation cyclic ADC further includes a fourth switch sw4, a first end of the fourth switch sw4 is connected to a first end of the residual sampling capacitor Cinj and a first input end of the amplifier AMP, and a second end of the fourth switch sw4 is connected to the common mode voltage Vcm.

As shown in fig. 4, in the sampling phase, the first ends of the capacitor units C6, C5, C4, C3, C2, C1, C0 are connected to the common mode voltage Vcm, the second ends of the capacitor units C6, C5, C4, C3, C2, C1, C0 are connected to the input voltage Vin, the first ends of the residual sampling capacitors Cinj are disconnected from the first ends of the capacitor units C6, C5, C4, C3, C2, C1, C0, the first ends of the residual sampling capacitors Cinj and the second ends of the residual sampling capacitors Cinj are connected to the common mode voltage Vcm to reset the residual sampling capacitors Cinj, and the input voltage Vin is sampled through the capacitor units C6, C5, C4, C3, C2, C1, C0.

In the quantization stage, the first ends of the capacitor units C6, C5, C4, C3, C2, C1, C0 are disconnected from the common mode voltage Vcm, the second ends of the capacitor units C6, C5, C4, C3, C2, C1, C0 are disconnected from the input voltage Vin, the second ends of the capacitor units C6, C5, C4, C3, C2, C1 are alternately connected to the reference voltage Vref, the remaining capacitor units are connected to the ground voltage GND, and the voltage at the first ends of the capacitor units and the common mode voltage Vcm are compared and output through the comparator CMP.

In the residual sampling phase, the first terminal of the residual sampling capacitor Cinj is disconnected from the common mode voltage Vcm (i.e. the fourth switch sw4 is opened), the first terminal of the capacitor unit C6, C5, C4, C3, C2, C1, C0 is connected to the first terminal of the residual sampling capacitor Cinj to store the residual voltage (i.e. the second switch sw2 is closed), after the storage, the first terminal of the capacitor unit C6, C5, C4, C3, C2, C1, C0 is disconnected from the first terminal of the residual sampling capacitor Cinj (i.e. the second switch sw2 is opened), the residual voltage is amplified by the amplifier AMP, the output terminal of the amplifier AMP is connected to the second terminal of the capacitor unit C6, C5, C4, C3, C2, C1, C0, and the first terminal of the capacitor unit C6, C5, C4, C3, C2, C1, C0 is connected to the common mode voltage Vcm (i.e. the first switch sw1 is closed), and the residual voltage is amplified by the capacitor unit C6, C4, C3, C2, C0.

In the residual quantization stage, the first ends of the capacitor units C6, C5, C4, C3, C2, C1, C0 are disconnected from the common mode voltage Vcm (i.e., the first switch sw1 is opened), the second ends of the capacitor units C6, C5, C4, C3, C2, C1 are alternately connected to the reference voltage Vref, the remaining capacitor units are connected to the ground voltage GND, the second ends of the redundant capacitor units C0 are always connected to the ground voltage GND, and the voltage at the first ends of the capacitor units and the common mode voltage Vcm are compared and output through the comparator CMP.

In the residual sampling stage, after the capacitor units C6, C5, C4, C3, C2, C1, C0 sample the amplified residual voltages, the first and second ends of the residual sampling capacitor Cinj are connected to the common mode voltage Vcm to reset the residual sampling capacitor Cinj.

Fig. 3 shows a successive approximation cyclic ADC of multiple cycles according to the present invention. In the successive approximation cyclic ADC in fig. 1, the first switch sw1 and the second switch sw2 are in an off state during the sampling phase, and thus the residual sampling capacitance Cinj is reset to the common mode voltage Vcm accordingly. During the first quantization phase, the second switch sw2 is always in the off state, so the residual voltage remains on the residual sampling capacitor Cinj. However, during the residual sampling phase, the second switch sw2 is in an off state, and the residual sampling capacitor Cinj cannot be reset to the common mode voltage Vcm, so the structure can be reset only once. On the basis of fig. 1, a fourth switch sw4 is additionally arranged on the upper polar plate (first end) of the residual sampling capacitor Cinj, and the fourth switch sw4 is closed, so that the residual sampling capacitor Cinj can be reset in a specific stage.

After the residual quantization phase is completed, the second switch sw2 is closed, and the charges on the upper plates of the capacitor units C6, C5, C4, C3, C2, C1, C0 are redistributed among the capacitor units C6, C5, C4, C3, C2, C1, the redundant capacitor unit C0 and the residual sampling capacitor Cinj. Assuming that the upper plate voltages of the capacitor units C6, C5, C4, C3, C2, C1, C0 before the redistribution are V1, the lower plate voltages are V2, the upper plate voltage of the residual sampling capacitor Cinj is Vcm, the lower plate voltage of the residual sampling capacitor Cinj is V3, and after the load redistribution occurs, it is assumed that the lower plate voltages of the capacitor units C6, C5, C4, C3, C2, C1, the redundant capacitor unit C0 and the residual sampling capacitor Cinj remain unchanged, so that only the upper plate voltages of the capacitors change. According to conservation of charge:

(V1-V2)Ctotal+(Vcm-V3)Cinj＝(Vy-V2)Ctotal+(Vy-V3)Cinj

wherein Vy is the upper plate voltage of the capacitor units C6, C5, C4, C3, C2, C1, C0 after charge transfer, i.e. Vy is the residual voltage, and the total capacitance Ctotal is expressed as:thus, the first and second substrates are bonded together,

because V1 is represented as the residual voltage after the last conversion is completed,

so that the number of the parts to be processed,

therefore, the residual voltage Vy after transfer is attenuated to a certain degree, and the attenuation factor isThis is equivalent to the amplifier AMP gain reduction. And in the actual production process, there will be a mismatch in the size of the capacitor +.>Will deviate from the actual value by a certain amount. In order to calibrate for the degradation in ADC accuracy due to these bias and attenuation effects in residual transfer, calibration techniques are required to improve the accuracy of the ADC.

The lower polar plate of the residual sampling capacitor Cinj is always connected with V in the residual sampling and residual quantizing processes _cm Therefore, when residual sampling is performed, the charge sampled by the upper polar plate isDuring the residual quantization stage, the high-order capacitor unit C6 is switched to Vref, and the other capacitor units are grounded to the voltage GND, and the upper plate charges of the capacitor units C5, C4, C3, C2, C1, C0 are +.> According to conservation of charge

The formula shows that during the first residual voltage transfer, although there is no significant charge redistribution step, the residual voltage still decays, consistent with the characteristics of the second residual voltage transfer. Therefore, calibration techniques are required to calibrate these deviations, either the architecture of fig. 1 or the architecture of fig. 3.

As shown in fig. 5, the present invention also discloses a successive approximation cyclic ADC system, including: the first successive approximation cyclic ADC10, the second successive approximation cyclic ADC20, the first weight calculation module 30, the second weight calculation module 40, the first calculation module 50, and the second calculation module 60. The first successive approximation cyclic ADC10 and the second successive approximation cyclic ADC20 are identical in structure and are the successive approximation cyclic ADCs described above.

The first successive approximation cyclic ADC10 and the second successive approximation cyclic ADC20 are both connected to the input voltage Vin. As shown in fig. 3, the second end of the residual sampling capacitor Cinj of the first successive approximation cyclic ADC10 is connected to the first offset voltage-Vos through the second control switch k7, and in the sampling stage, the second end of the residual sampling capacitor Cinj of the first successive approximation cyclic ADC10 is connected to the first offset voltage-Vos; the second end of the residual sampling capacitor Cinj of the second successive approximation cyclic ADC20 is connected to the second offset voltage Vos through the second control switch k7, and in the sampling stage, the second end of the residual sampling capacitor Cinj of the second successive approximation cyclic ADC20 is connected to the second offset voltage Vos.

The first weight calculation module 30 is configured to perform weight calculation on the digital code output by the first successive approximation cyclic ADC10, and the second weight calculation module 40 is configured to perform weight calculation on the digital code output by the second successive approximation cyclic ADC 20. The digital code output by the first successive approximation cyclic ADC10 is a digital code (0 or 1) output by a comparator CMP in the first successive approximation cyclic ADC10, the digital code output by the second successive approximation cyclic ADC20 is a digital code (0 or 1) output by a comparator CMP in the second successive approximation cyclic ADC20, and a product obtained by multiplying the digital code output by each comparator CMP by weights corresponding to the capacitor units C1, C2, C3, C4, C5, and C6 is used as the output digital code Douta of the first weight calculation module 30 and the output digital code Doutb of the second weight calculation module 40.

The first calculation module 50 obtains an error signal error based on the signals output from the first and second weight calculation modules 30 and 40 and feeds the error signal error back to the first and second weight calculation modules 30 and 40 to adjust the weights. The second calculating module 60 is configured to calculate the signals output by the first weight calculating module 30 and the second weight calculating module 40 to obtain a result signal X. The error signal error is equal to the difference of the signal Douta output by the first weight calculation module 30 minus the signal Doutb output by the second weight calculation module 40. The resulting signal X is equal to the sum of the signal Douta output by the first weight calculation module 30 and the signal Doutb output by the second weight calculation module 40 divided by two.

Fig. 5 is a schematic diagram of a successive approximation cyclic ADC system based on a split structure according to the invention. Based on the original successive approximation cyclic ADC, the structure is divided into two parts, and different direct current offset voltages (-Vos, vos) are injected into the two successive approximation cyclic ADCs. The two identical successive approximation cyclic ADCs acquire the same input signal Vin, the sampling rate is unchanged, and the sum of the digital outputs of the two weight calculation modules is halved to be a final result signal X.

The principle of digital calibration is described below and can be expressed by the following formula for an ideal successive approximation cyclic ADC

f(Vin)＝kVin+e

Where Vin represents the analog input, k represents the digital gain, e represents the dc offset introduced by the successive approximation cyclic ADC, and f (Vin) represents the digital output. The system is an incremental linear system, and for any gain linear system, the difference between any two input responses is a linear function of the difference between the two inputs, i.e. as follows

f(x ₁ )-f(x ₂ )＝k(x ₁ -x ₂ )

Thus, after different offset voltages are injected into the successive approximation cyclic ADC with identical transmission characteristics, their difference will be constant.

f(Vin+Vos)-f(Vin-Vos)＝2kVos

Fig. 6 (a) shows that their difference is constant for an incremental linear system after injection misalignment. However, in a practical successive approximation cyclic ADC, the transmission characteristics tend to be a nonlinear system, i.e., due to capacitive mismatch and gain error of the amplifier AMP

f (vin+Vos) -f (Vin-Vos) noteqconst (constant)

The difference between the nonlinear systems will superimpose an error term between 2kVos that can be used for calibration as compared to the difference between the incremental linear systems being constant, and when the error term is zero, this indicates that calibration is complete. Fig. 6 (b) shows that the difference for a nonlinear system after injection of offset voltage will change with analog input.

In successive approximation cycleIn the ADC, the final digital codes Douta and Doutb can be obtained by the weight w of each bit ^T And the digital code f of each bit _i Is represented by the inner product:

Douta＝Doutb＝w ^T ·f _i

wherein the relative proportion of the weight vector w to the capacitor units C6, C5, C4, C3, C2 and C1 is generally an equal-ratio array with the common ratio of 2, and the digital codes f of each bit are _i I.e. the output 0 or 1 of the comparator. However, due to the mismatch of the capacitive units C6, C5, C4, C3, C2, C1 and the limited gain error, the elements in w will deviate from the ideal values, the task of digital calibration is to find the actual w in the digital domain. Specifically, the matrix equation is solved, that is q·w=0,

wherein f _a,1 (1)f _a,2 (1)…f _a,n (1) Representing the digital code generated by the first conversion of the first successive approximation cycle ADC 10; f (f) _a,1 (2)f _a,2 (2)…f _a,n (2) Representing the digital code generated by the second conversion of the first successive approximation cyclic ADC 10; f (f) _a,1 (n)f _a,2 (n)…f _a,n (n) represents the digital code generated by the nth conversion of the first successive approximation cyclic ADC 10. f (f) _b,1 (1)f _b,2 (1)…f _b,n (1) Representing the digital code generated by the first conversion of the second successive approximation cyclic ADC 20; f (f) _b,1 (2)f _b,2 (2)…f _b,n (2) Representing the digital code resulting from the second conversion of the second successive approximation cyclic ADC 20; f (f) _b,1 (n)f _b,2 (n)…f _b,n (n) represents the digital code resulting from the nth conversion of the second successive approximation cyclic ADC 20.

If the matrix equation is directly solved, the inverse of the matrix Q is involved, and the calculation cost is huge. A gradient descent algorithm is used to solve for w. Using mean square error as the loss function J (w), i.e

The true weight vector w is approximated by an iterative equation, which is a gradient descent algorithm, until the error term is 0.

w _n+1 ＝w _n -μ·J ^′ (w)

J ^′ (w) represents the derivative of the loss function J (w) with respect to w. μ represents a learning rate. w (w) _n Representing weights before iteration, w _n+1 Representing the weights after the iteration. Meanwhile, to avoid w from being trapped in the zero solution, one element in the weight vector may be fixed.

In the invention, offset voltage is injected through residual sampling capacitor Cinj. When the sampling phase is finished and the quantization phase is started, the lower polar plate of the residual sampling capacitor Cinj is connected with Vcm-Vos, and the lower polar plate of the residual sampling capacitor Cinj is kept unchanged all the time, so that positive offset voltage is injected; if the lower plate of the residual sampling capacitor Cinj is connected with Vcm-Vos, when the sampling phase is ended and the quantization phase is started, the lower plate of the residual sampling capacitor Cinj is connected with vcm+vos, and then the lower plate of the residual sampling capacitor Cinj is always kept unchanged, and then negative offset voltage is injected. During the sampling phase, the plate charges on the capacitor units C6, C5, C4, C3, C2, C1, C0 areDuring the first quantization, the high-order capacitor unit C6 is switched to Vref, and the other capacitor units C5, C4, C3, C2, C1, C0 are connected to GND, at this time, the upper plate charges of the capacitor units are Obtained from conservation of charge

Thus the injected offset voltage isThe magnitude of the injected voltage can be controlled by adjusting Vos and Cinj.

One necessary premise that digital calibration exists is redundancy. For the successive approximation cyclic ADC proposed by the present invention, inter-stage redundancy and intra-stage redundancy can be used, the principle is explained below with inter-stage redundancy.

As shown in fig. 7, in the successive approximation cyclic ADC, if the first stage converts 7 bits, as shown in fig. 1, the amplifier AMP needs to amplify 2 in the absence of redundancy ⁷ =128 times, if there is redundancy of 1bit, the amplifier AMP needs to amplify 2 ⁶ =64 times. The transfer residual curves are shown in fig. 7 (a) and 7 (b), respectively. One advantage of redundancy is that errors due to incomplete capacitor cell establishment can be directly calibrated, if the high-order capacitor cell is not fully established, which corresponds to the shift of the inversion point to the right, and in the absence of redundancy, the residual voltage generated will exceed the range of the latter stage, as shown in fig. 7 (c), which severely reduces the ADC linearity. If redundancy exists, although the inversion point moves rightward, the residual voltage generated is still in the subsequent stage range, and as shown in fig. 7 (d), the redundancy can calibrate the case where the inversion point moves leftward in the differential circuit. Another benefit of redundancy is that it eliminates residual voltage curves due to capacitive cell mismatch from exceeding the range that can be handled by the later stages. As shown in fig. 7 (e), if there is no redundancy, the residual voltage exceeds the processing range of the subsequent stage due to the mismatch of the capacitor cells, and in the case of fig. 7 (f), the residual voltage is still within the processing range of the subsequent stage although the capacitor cells are not matched.

The foregoing descriptions of specific exemplary embodiments of the present invention are presented for purposes of illustration and description. It is not intended to limit the invention to the precise form disclosed, and obviously many modifications and variations are possible in light of the above teaching. The exemplary embodiments were chosen and described in order to explain the specific principles of the invention and its practical application to thereby enable one skilled in the art to make and utilize the invention in various exemplary embodiments and with various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims and their equivalents.

Claims

1. A successive approximation cyclic ADC comprising:

2. The successive approximation cyclic ADC of claim 1, further comprising a fourth switch, a first terminal of the fourth switch being coupled to the first terminal of the residual sampling capacitor and to the first input terminal of the amplifier, and a second terminal of the fourth switch being coupled to the common mode voltage.

3. The successive approximation cyclic ADC of claim 1, wherein the capacitance unit further comprises a redundant capacitance unit.

4. The successive approximation cyclic ADC of claim 1, further comprising a logic control module that generates a control signal for controlling the first control switch based on an output signal of the comparator.

5. The successive approximation cyclic ADC of claim 1, further comprising a fifth switch, a first terminal of the fifth switch being coupled to the first control switch, a second terminal of the fifth switch being coupled to the input voltage, a first terminal of the third switch being coupled to the output of the amplifier, a second terminal of the third switch being coupled to the first terminal of the fifth switch.

6. A successive approximation cyclic ADC system, comprising: the first successive approximation cyclic ADC of any one of claims 1 to 5, the second successive approximation cyclic ADC of any one of claims 1 to 5, the first weight calculation module, the second weight calculation module, the first calculation module, and the second calculation module;

7. A method of signal conversion for a successive approximation cyclic ADC comprising:

8. A method of signal conversion for a successive approximation cyclic ADC comprising:

9. The method of signal conversion of a successive approximation cyclic ADC of claim 8, wherein the second terminal of the residual sampling capacitor is connected to the common mode voltage after the capacitor unit samples the amplified residual voltage.

10. The signal conversion method of a successive approximation cyclic ADC according to claim 7 or 8, wherein the redundant capacitor unit is connected to a ground voltage in a quantization stage and a residual quantization stage.