WO2010140559A1

WO2010140559A1 - Successive-approximation type ad converter circuit

Info

Publication number: WO2010140559A1
Application number: PCT/JP2010/059175
Authority: WO
Inventors: 文裕井上
Original assignee: ミツミ電機株式会社
Priority date: 2009-06-03
Filing date: 2010-05-31
Publication date: 2010-12-09
Also published as: JP2010283484A

Abstract

In a successive-approximation type AD converter circuit, AD conversion accuracy is improved by reducing noise in a comparator circuit without reduction in apparent conversion speed. Provided is a successive-approximation type AD converter circuit provided with a comparator circuit, a register and a local DA converter circuit. The comparator circuit is provided with multiple amplification stages connected in cascade with a coupling capacitance between each adjacent two thereof, and determines which of an inputted analogue voltage and a compared voltage is larger. The register sequentially retrieves results of the determination of the comparator circuit and stores these results. The local DA converter circuit converts a value in the register into a voltage to generate the compared voltage. In this AD converter circuit, load capacitance adjusting units (16) and a control circuit (15) are provided, whereby capacitance values of the load capacitance adjusting units are set smaller in conversion of higher-order bits, and larger in conversion of lower-order bits. The load capacitance adjusting units (16) are connected to output terminals of the respective amplification stages of the comparator circuit (11). The control circuit (15) generates a signal for changing capacitance values of the load capacitance adjusting units.

Description

Successive approximation type AD converter circuit

The present invention relates to a technique for improving conversion accuracy in a successive approximation AD converter circuit, and more particularly to a technique suitable for use in an AD converter circuit having a chopper comparator.

Portable electronic devices such as mobile phones, PDAs (Personal Digital Assistants), and digital cameras are equipped with a microprocessor to control the system inside the device, and the microprocessor monitors the temperature, battery voltage, etc. Control is in progress. Therefore, equipment is provided with sensors for detecting temperature, battery voltage, etc., and a microprocessor with an A / D conversion circuit for converting analog signals from these sensors into digital signals is used. There are many.

Also, it is desired that the A / D conversion circuit built in the microprocessor or the like has a small circuit scale. As such an A / D conversion circuit, for example, an A / D conversion circuit using a so-called chopper type comparator using a CMOS inverter as an amplifier as shown in FIG. 14 is known.

In this A / D conversion circuit, a switch (sampling switch) SS1 on the analog signal input side is turned on with the sampling clock short-circuited between the input and output terminals of the CMOS inverter, and the logical threshold voltage of the inverter is used as a reference. The input signal Vin is sampled into the capacitor Cs. Thereafter, the sampling switch SS1 is turned off, the switch SS2 on the comparison voltage input side is turned on, the comparison voltage Vref is applied to the sampling capacitor Cs, and the input and output of the CMOS inverter are shut off, whereby each inverter becomes an amplifier. Operates and changes output. At this time, since the input is amplified by the three-stage inverter, the output becomes the power supply voltage Vcc or the ground potential GND which is almost at the logic level, and the determination result of the magnitude relation between Vin and Vref is output.

Japanese Patent Laid-Open No. 7-95080

In an AD conversion circuit using a chopper type comparator, thermal noise generated by elements such as resistors and transistors during sampling, and noise (substrate noise) due to leakage current flowing in the substrate are taken into the sampling capacitor, resulting in an error in the AD conversion result. In addition to this, an error occurs in the AD conversion result due to noise generated in a CMOS inverter as an amplification stage during comparison.

Here, the noise generated in the CMOS inverter is represented by 2 kT / 3CL (k is Boltzmann constant, T is absolute temperature), where CL is the inverter load capacitance (parasitic capacitance). From this, it can be understood that the noise of the inverter can be reduced by increasing the load capacitance CL. However, the size of the load capacity of the CMOS inverter in the chopper type comparator has a great influence on the operation speed, and the operation speed decreases when the load capacity is increased. Therefore, conventionally, the design is generally made so that the load capacity becomes small.

On the other hand, errors caused by taking thermal noise of the resistor and substrate noise into the sampling capacitor can be reduced by measures such as increasing the capacitance value of the sampling capacitor, but doing so increases the area and costs. In addition to increasing the speed, the conversion speed decreases and other problems occur. Note that the thermal noise taken into the sampling capacitor is represented by kT / C, in which the noise VR ² generated by the resistor is integrated by a low-pass filter as shown in FIG.

Paying attention to the fact that there is a trade-off between increasing the conversion speed and reducing noise as described above, two sampling capacitors and sampling switches are provided, and the capacitors are switched according to the level of the input signal. Thus, an invention has been proposed in which improvement in AD conversion accuracy and conversion speed are both achieved (Patent Document 1). However, since the present invention has two systems of sampling capacitors and sampling switches, when the semiconductor integrated circuit is formed, there is a problem that the occupied area of the circuit is greatly increased and the cost is increased. In addition, although an error occurs in the AD conversion result due to noise generated in the CMOS inverter, in the invention of Patent Document 1, a load capacitance (parasitic capacitance) existing between the output terminal of the inverter constituting the comparison circuit and the ground point. ) Is not taken into consideration at all, and thus errors due to noise generated in the CMOS inverter cannot be prevented.

By the way, it is effective to increase the load capacity of the inverter in order to reduce the noise (thermal noise) generated in the inverter. However, as described above, when the load capacity of the inverter is increased, the operation speed of the comparator is lowered. Therefore, conventionally, the design is made such that the load capacity (parasitic capacity) is reduced, and the noise is sufficiently reduced. It has been found that there is a problem that the AD conversion accuracy decreases.

The present invention has been made paying attention to the above-mentioned problems, and the object of the present invention is to reduce noise in the comparison circuit without reducing the apparent conversion speed in the successive approximation type AD conversion circuit. An object of the present invention is to improve the AD conversion accuracy.

Another object of the present invention is to reduce erroneous comparison and determination and improve AD conversion accuracy in a successive approximation AD converter circuit.

Still another object of the present invention is to make it possible to correct errors due to noise and improve AD conversion accuracy in a successive approximation AD converter circuit.

In order to achieve the above object, the present invention provides:
A comparison circuit that includes a plurality of amplification stages connected in cascade via a coupling capacitor, determines the magnitude of the input analog voltage and the comparison voltage, a register that sequentially captures and holds the determination result of the comparison circuit, and a value of the register In a successive approximation AD converter circuit comprising a local DA converter circuit that converts the voltage into a voltage and generates the comparison voltage,
Load capacity adjustment means connected to the output terminal of the amplification stage of the comparison circuit;
A control circuit for generating a signal for changing the capacity value of the load capacity adjusting means;
The capacity value of the load capacity adjusting means is reduced when converting the upper bits, and the capacity value of the load capacity adjusting means is increased when converting the lower bits. .

The output voltage of the amplification stage of the conventional comparator circuit is longer in the initial stage of conversion, that is, in the upper bit comparison operation, until the target level is reached. Although the time is shortened, according to the above-described configuration of the present invention, a comparison operation is performed at a high speed in order to reduce the load capacity of the amplification stage during the conversion of the upper bits, while the load capacity is increased during the conversion of the lower bits. Therefore, the settling time is longer than in the conventional case, but the noise reduction effect is enhanced. Further, since the period of the clock for operating the comparison circuit is determined by the settling time of the most significant bit, even if the settling time of the lower bits becomes longer than before, the AD conversion time as a whole is not extended, Noise can be reduced and the occurrence of errors can be suppressed.

Preferably, when the lower bit is converted, the settling time of the output voltage of the amplification stage to which the load capacity adjusting unit is connected is the same as the maximum settling time when the upper bit is converted. As described above, the capacity value of the load capacity adjusting means is changed. As a result, it is possible to achieve both high speed comparison and low noise in a balanced manner, that is, maximum noise reduction within a range in which the apparent conversion speed is not lowered at all.

Preferably, the load capacitance adjusting means includes one or more capacitive elements and a switch element connected in series with any one of the capacitive elements, and the switch element is turned on or off. Thus, the capacity value is changed. As a result, it is possible to realize a load capacity adjusting means having a relatively simple configuration and suitable for the semiconductor integrated circuit.

Other inventions in this application are:
A comparison circuit that includes a plurality of amplification stages connected in cascade via a coupling capacitor, determines the magnitude of the input analog voltage and the comparison voltage, a register that sequentially captures and holds the determination result of the comparison circuit, and a value of the register In a successive approximation AD converter circuit comprising a local DA converter circuit that converts the voltage into a voltage and generates the comparison voltage,
Load capacity adjustment means connected to the output terminal of the amplification stage of the comparison circuit;
A switch capable of switching between one or more capacitors having one terminal connected to the input terminal of the first amplification stage of the comparison circuit and a voltage applied to the other terminal of the capacitor based on the output of the comparison circuit A sub-DA conversion circuit having means;
Generates a control signal for the sub-D / A converter circuit in accordance with the output of the comparison circuit, causes the comparison circuit to perform a redundant comparison, averages the output of the comparison circuit, and generates a correction signal for the register value And a control circuit for generating a signal for changing the capacity value of the load capacity adjusting means;
The capacity value of the load capacity adjusting means is reduced when converting the upper bits, and the capacity value of the load capacity adjusting means is increased when converting the lower bits, and the local DA converter circuit After a normal AD conversion operation using, a redundancy comparison operation using the sub DA conversion circuit is executed using the conversion result as a start value.

According to the above configuration, the comparison operation is performed at a high speed to reduce the load capacity of the amplification stage when converting the upper bits, while the load capacity is increased when converting the lower bits, so that the AD conversion time is not extended. It is possible to reduce noise and suppress the occurrence of errors, and obtain an AD conversion value in which an error due to switching noise is corrected by a redundancy comparison performed after a normal AD conversion operation.

Here, preferably, the control circuit causes the redundant comparison using the sub DA conversion circuit to be executed a plurality of times, and the result of the normal AD conversion operation using the local DA conversion circuit and the redundant comparison of the plurality of times are performed. An averaging process with the result is performed, and the value of the register can be changed according to the result of the averaging process. This makes it possible to obtain a more accurate AD conversion value in which an error due to switching of the amplification stage is corrected.

Still another invention of this application is:
A comparison circuit that includes a plurality of amplification stages connected in cascade via a coupling capacitor, determines the magnitude of the input analog voltage and the comparison voltage, a register that sequentially captures and holds the determination result of the comparison circuit, and a value of the register A local DA converter circuit that converts the voltage into a voltage and generates the comparison voltage; a load capacity adjustment means connected to the output terminal of the amplification stage of the comparison circuit; and a signal that changes the capacitance value of the load capacity adjustment means A successive approximation AD converter circuit including a control circuit,
The comparison circuit is
A first comparison stage having a first amplification stage and a second comparison stage having a second amplification stage, each having a first amplification stage in common among the plurality of amplification stages and connected to each subsequent stage via a coupling capacitor;
A first comparison point shift circuit connected to the input terminal of the first amplification stage and a second comparison point shift circuit connected to the input terminal of the second amplification stage;
A logic circuit unit that generates a predetermined code in accordance with an output of the first comparison unit and an output of the second comparison unit, and performs a calculation process on the generated code to generate a value to be stored in the register;
The first comparison point shift circuit and the second comparison point shift circuit include the comparison circuit when amplifying a potential difference between the input analog voltage and the comparison voltage by the first comparison unit and the second comparison unit, respectively. Operates to shift the voltage by a predetermined amount in the opposite directions,
The control circuit is configured to decrease the capacity value of the load capacity adjusting means when converting the upper bits, and to increase the capacity value of the load capacity adjusting means when converting the lower bits.

According to the above configuration, the comparison operation is performed at a high speed to reduce the load capacity of the amplification stage when converting the upper bits, while the load capacity is increased when converting the lower bits, so that the AD conversion time is not extended. Noise can be reduced and the occurrence of errors can be suppressed. In addition, since comparison is performed at two comparison points that avoid the original comparison point, erroneous determination is less likely to occur, and a first comparison unit and a second comparison unit are provided, and determination is performed in parallel by the two comparison units. As a result, the time required for conversion does not have to be long.

Preferably, three types of the predetermined codes generated by the logic circuit unit are set, and when the first code is generated, the local DA converter circuit performs the previous comparison operation in the next comparison operation. When the second code is generated, the local DA converter circuit generates the same voltage as the comparison voltage in the previous comparison operation when the second code is generated. When the third code is generated, in the next comparison operation, the local DA converter circuit is configured to generate a voltage lower than the comparison voltage in the previous comparison operation. As a result, the comparison voltage in the next comparison operation changes according to the previous comparison result, so that even if a comparison error occurs, the determination can be led in the direction of correcting the error in the subsequent comparison operation. A conversion result with few errors can be obtained.

Preferably, each of the first comparison point shift circuit and the second comparison point shift circuit includes a first capacitor having one terminal connected to an input terminal of the first amplification stage or an input terminal of the second amplification stage. A first changeover switch for switching a voltage applied to the other terminal of the first capacitor and a second changeover switch for switching a voltage applied to the other terminal of the second capacitor, The switch and the second change-over switch are configured so that the direction of the voltage to be switched is different. As a result, the first comparison point shift circuit and the second comparison point shift circuit can be realized with a relatively simple circuit.

According to the present invention, in the successive approximation type AD converter circuit, it is possible to improve the AD conversion accuracy by reducing noise in the comparison circuit without reducing the apparent conversion speed. In addition, erroneous comparison and determination can be reduced and AD conversion accuracy can be improved. Furthermore, there is an effect that an error due to noise can be corrected and AD conversion accuracy can be improved.

1 is a circuit configuration diagram showing an embodiment of a successive approximation AD converter circuit according to the present invention. It is explanatory drawing which shows the sampling capacitor Cs and the low-pass filter which makes the load capacity of an amplification stage C, and its input-output characteristic. It is a graph which shows the relationship between the number of conversion bits in a successive approximation type AD converter circuit, and the static time (maximum value) per bit. It is a graph which shows the relationship between the load capacity ratio of the amplification stage which becomes the same as the settling time of the conversion bit and the most significant bit in a successive approximation type AD converter circuit. It is a circuit diagram which shows the specific example of a load capacity adjustment means. It is a circuit diagram which shows the specific example of a load capacity adjustment means. It is a circuit diagram which shows the specific example of a load capacity adjustment means. It is a circuit diagram which shows the specific example of a load capacity adjustment means. It is a circuit diagram which shows the specific example of a load capacity adjustment means. It is a circuit diagram which shows the specific example of a load capacity adjustment means. It is a circuit diagram which shows the other structural example of the chopper type | mold comparator of the successive approximation type AD converter circuit of an Example. FIG. 3 is a circuit configuration diagram showing a second embodiment of a successive approximation AD converter circuit according to the present invention. In the AD converter circuit of 2nd Embodiment, it is the time chart which showed the level of the output voltage (Vref) of a local DA converter circuit for every cycle, taking a time axis on a horizontal axis. FIG. 3 is a circuit configuration diagram showing a second embodiment of a successive approximation AD converter circuit according to the present invention. In the AD conversion circuit of 3rd Embodiment, it is explanatory drawing which shows the method of the process of the code which shows the comparison result of each bit taking 4 bit AD conversion as an example. FIG. 10 is an operation explanatory diagram showing a part of the comparison operation of the (n−1) th bit and the comparison operation of the (n−2) th bit in the AD conversion circuit of the third embodiment. It is explanatory drawing which shows an example of the change of the output voltage of local DAC during the conversion operation at the time of performing AD conversion in the AD conversion circuit of 3rd Embodiment. It is conversion explanatory drawing which shows the mode of conversion when a misjudgment generate | occur | produces in the conventional general AD converter circuit. It is explanatory drawing which shows the relationship between the switching frequency of an inverter, and the code change of an AD conversion output in case an analog input voltage is taken on a horizontal axis and the variation in switching frequency is small. It is explanatory drawing which shows the relationship between the switching frequency of an inverter, and the code change of AD conversion output in case an analog input voltage is taken on a horizontal axis and the variation in switching frequency is large. It is a circuit block diagram which shows the structural example of the conventional AD converter circuit provided with the chopper type comparator.

Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows an embodiment of a successive approximation AD converter circuit according to the present invention. The AD conversion circuit shown in FIG. 1 is a sample-and-hold circuit 11 that alternately samples an analog input Vin input to an analog input terminal and a comparison voltage Vref applied to a reference voltage terminal to hold a difference voltage. A chopper comparator 12 that amplifies the differential voltage sampled by the sample and hold circuit 11, a successive approximation register 13 that sequentially captures the output of the chopper comparator 12, and a signal output from the register 13 The local DA conversion circuit 14 that outputs the voltage obtained by DA-converting the output code of the register 13 as the comparison voltage Vref to the sample and hold circuit 11 when the switch is switched, and the control that outputs the predetermined signal using the output of the comparator 12 as an input Each CMOS inverter of the circuit 15 and the comparator 12 Comprising INV1, INV2, connected to the output terminal of INV3 load capacitance adjusting means 16a, 16b, and 16c.

The sample and hold circuit 11 includes a pair of sampling switches SS1 and SS2 that are complementarily turned on and off by a sampling clock φs and a clock / φs having a phase opposite to the sampling clock φs, a connection node between the switches SS1 and SS2, and the chopper comparator The sampling capacitor Cs is connected between 12 input terminals.

The chopper comparator 12 has three CMOS inverters INV1, INV2, and INV3 connected in cascade through capacitors C2 and C3, and switches S1, S2, and S3 that short-circuit the input / output terminals for each inverter. It is set as the provided structure.

In the comparator 12 of this embodiment, the switches S1, S2, and S3 are turned on during the sampling period, and the input and output of the inverters INV1, INV2, and INV3 are short-circuited. The potential is equal to the threshold value VLT. Therefore, in the sample and hold circuit 11, the switch SS1 on the input terminal side is turned on by the sampling clock φs. As a result, the input analog voltage Vin is sampled in the sampling capacitor Cs with reference to VLT. That is, Cs is charged with a charge corresponding to the potential difference between VLT and Vin. The capacitors C2 and C3 are charged with voltages (VLT2-VLT1) and (VLT3-VLT2) which are the differences between the logic threshold values of the inverters.

At the time of comparison determination (hold period), in the sample and hold circuit 11, the reference side switch SS2 is turned on by the sampling clock / φs. As a result, charges corresponding to the potential difference (Vref−Vin) between the input analog voltage Vin and the comparison voltage Vref remain in the sampling capacitor Cs. In the comparator 12, the switches S1, S2, and S3 are turned off by φs and the input and output of the inverters INV1, INV2, and INV3 are cut off, so that each inverter operates as an amplifier and outputs according to the input potential. Change.

At this time, the potential difference (Vref−Vin) is transmitted to the input terminal of the first-stage inverter INV1 through the sampling capacitor Cs, and the potential difference is gradually amplified by the inverters INV1, INV2, and INV3. As a result, the result of comparing the input analog voltage Vin and the comparison voltage Vref appears at the output of the inverter INV3. Specifically, when Vin is higher than Vref, the output of the inverter INV3 is at a low level (ground potential GND), and when Vin is lower than Vref, the output of the inverter INV3 is at a high level (power supply voltage Vdd).

The control circuit 15 generates clocks φs and / φs for the sample and hold circuit 11 and the comparator 12, and generates and outputs control signals for the load capacity adjusting means 16a, 16b and 16c. In addition, the control circuit 15 includes a counter inside, for example, and is configured to generate a control signal while grasping how many bits of the comparison operation are being performed.

Here, the reason why the load capacity is adjusted by the load capacity adjusting means 16a to 16c will be described.

In the successive approximation type AD converter circuit, the output voltage of the amplification stage is the time until the output reaches the target level even if the input voltage rises sharply by the integration operation of the low pass filter of R and C as shown in FIG. It takes time, and the change in the reference voltage is larger at the initial stage of conversion, that is, the comparison operation of the upper bits. Therefore, the settling time until the voltage reaches the target level is long, and the number of comparisons is repeated to shift to the lower bits. The shorter the settling time.

Therefore, in the AD converter circuit of the embodiment of FIG. 1, the load capacity of each amplification stage of the comparator 12 is reduced during high-order bit conversion to perform high-speed comparison operation, and the load capacity is increased during low-order bit conversion. Thus, the load capacity adjusting means 16a to 16c are controlled so that the noise reduction effect is enhanced. By performing such control, the occurrence of errors can be suppressed without extending the AD conversion time as a whole.

Next, a desirable method for adjusting the load capacity by the load capacity adjusting means 16a to 16c will be described.

The present inventor examined the relationship between the number of AD conversion bits and the settling time for the AD conversion circuit as shown in FIG. 14, and found that the maximum value, that is, the most significant bit settling time and the number of AD conversion bits. There was a proportional relationship as shown in FIG.

Further, with respect to the load capacity of the amplification stage (inverter) in the AD converter circuit of FIG. 14, the capacity value at each conversion bit necessary for setting the same time as the settling time of the most significant bit is 14 bits, 13 bits. , 12-bit and 11-bit AD converter circuits were estimated. Then, when the capacity ratio between the capacity value and the minimum load capacity value of the amplification stage (inverter) was obtained, the result shown in FIG. 4 was obtained.

Therefore, if the load capacity adjusting means 16a to 16c are controlled so that the load capacity increases according to the characteristics of FIG. 4 as the number of comparisons, that is, the conversion bit progresses, the occurrence of errors can be suppressed without extending the AD conversion time as a whole. Can do. Specifically, as shown in FIG. 4, in the case of 14-bit AD conversion, the capacity ratio is about twice when the sixth bit is converted, about four times for the third bit, about seven times for the first bit, and about It can be seen that it is sufficient to increase the number of bits by about 14 with 0 bits. However, a circuit that changes the load capacity every time has a complicated configuration and an increased occupation area. In particular, since the capacity ratio does not change so much when converting the first bit, that is, the upper bits, the capacity value may be switched in several steps in the range below the characteristic lines in FIG.

Next, specific examples of the load capacity adjusting means 16a, 16b, 16c that can be switched as described above will be described with reference to FIGS. 5A to 5F. 5A to 5F show circuit examples of the load capacity adjusting means, respectively. In FIG. 5A to FIG. 5F, what is indicated by reference sign INVi is composed of a P-channel MOSFET (insulated gate field effect transistor) Q1 and an N-channel MOS transistor Q2 constituting each amplification stage (inverter) of the comparator 12. It is a CMOS inverter.

The load capacity adjusting means of FIG. 5A is composed of one capacitive element Cl1 and one on / off switch connected in series between the output node of the inverter and the grounding point. The capacitance value is changed by being turned on or off by a signal from the control circuit 15. The load capacity adjusting means shown in FIG. 5B is composed of two series-type capacitative elements Cl1, Cl2 and Cl2 and an on / off switch in parallel. The load capacity adjusting means shown in FIG. 5C includes two series-type capacitive elements Cl1, Cl2, a series-type capacitive element Cl3 connected in parallel with the Cl2, and an on / off switch. The load capacity adjusting means shown in FIG. 5D includes two parallel capacitive elements Cl1 and Cl2, and an on / off switch connected in series with the Cl2.

Further, the load capacity adjusting means of FIG. 5E is provided with an on / off switch in series with the capacitive element Cl1 of FIG. 5D. The load capacity adjusting means in FIG. 5F includes two capacitive elements Cl1, Cl2 in series and on / off switches, and two capacitive elements Cl3, Cl4 in series connected to the connection node of Cl1 and Cl2. Two capacitive elements Cl5 and Cl6 in series connected to the connection node of Cl3 and Cl4 and the on / off switch and one of the series configuration connected to the connection node of Cl5 and Cl6 Each capacitor element Cl7 and an on / off switch.

Among the load capacity adjusting means, FIGS. 5A to 5D are capable of switching the capacitance value in two stages, FIG. 5E is capable of switching in three stages, and FIG. 5F is capable of switching in 12 stages. 5A to 5F show specific examples in which the capacitance value can be switched stepwise, but a variable capacitance element whose capacitance value changes according to the applied voltage, such as a MOSFET gate capacitance or a varicap diode, is used. Then, the capacitance value may be changed.

In the embodiment of FIG. 1, the load capacity adjusting means is provided for each of the three amplification stages. However, the load capacity adjusting means may be provided for one amplification stage or two amplification stages. Here, since the input conversion noise of the noise generated in the second and subsequent amplification stages is smaller than that in the first stage, when the load capacitance adjusting means is provided in only one amplification stage, the first amplification stage. It is desirable to provide in. However, when the gain of the first amplification stage is small, the load capacity adjusting means may be provided only in the second amplification stage.

Further, as shown in FIG. 6, in a chopper type comparator configured such that a feedback capacitor Cf is connected between an input terminal and an output terminal of a CMOS inverter and gain adjustment is possible, load capacity adjusting means 16i is provided at the output of the inverter. You may do it. A comparator provided with a feedback capacitor can reduce noise as compared with a comparator that does not have a feedback capacitor by itself, but noise can be further reduced by providing a load capacitance adjusting means.

In the above embodiment, assuming an AD conversion circuit with a fixed number of bits, when converting the upper bits, the load capacity of the amplification stage is reduced to increase the speed, and when converting the lower bits, the amplification stage However, the above embodiment is applied to an AD converter circuit having a variable number of bits that can be converted, and the load capacity is increased when the number of bits is large. Thus, noise may be reduced, and when the number of bits is small, the load capacity may be reduced to increase the speed.

When the AD conversion circuit is mounted on an LSI such as a microprocessor having a CPU (central processing unit), a register capable of setting the load capacity value by the CPU is provided. It is also possible to configure the load capacity adjusting means to be controlled according to the set value.

FIG. 7 shows an embodiment of another AD conversion circuit suitable using a chopper type comparator having a load capacity adjustment function of the present invention.

In this embodiment, a sub DA conversion circuit (SubDAC) 17 connected to the input terminal of the first stage CMOS inverter INV1 of the comparator 12 is provided. Although not particularly limited, the load capacity adjusting means 16 is connected to the output terminal of the first-stage CMOS inverter INV1. Other CMOS inverters may be provided with load capacity adjusting means. Since the specific example and function of the load capacity adjusting means 16 are the same as those in the above embodiment, the description thereof is omitted.

The sub DA conversion circuit 17 is connected to the capacitors CDA1... CDAk, one terminal of which is connected to the input terminal of the first-stage inverter INV1, and to the other terminal of each capacitor CDA1. Switch SW11... SW1k for selectively applying. Vref_h and Vref_l are voltages corresponding to an upper limit value and a lower limit value of a voltage range FSR (Full Scale Range) in which AD conversion is possible.

Capacity CDA1 ...... CDAk are each 2 ^0, 2 ^1, the capacitance value such that the relationship with the weight of the ...... 2 ^k-1 is set. For example, when the local DA converter circuit 14 is a charge distribution type circuit using a weight capacitor, the smallest capacitor CDak is the same as the smallest capacitor among the weight capacitors constituting the local DA converter circuit. The capacitance value is smaller than that. The switches SW11... SW1k perform a switching operation of the voltage to be applied according to a signal from the control circuit 15. The two weighted weight capacity constituting the local DA conversion circuit 14 ^0, 2 ^1, when ...... 2 ^n, k is a positive integer smaller than n. It is also possible to set the capacitance value of the largest weighted capacitance in the sub DA conversion circuit 16 to the same capacitance value as the smallest one of the weighted capacitances in the local DA conversion circuit 14.

The control circuit 15 is configured to have a function of averaging a plurality of redundant comparison results output from the comparator 12 by a redundant comparison operation described later. Such a function can be constituted by a register (accumulator) for holding the redundant comparison result of the comparator 12 and an arithmetic circuit (adder) for averaging the redundant comparison results of a plurality of times.

The output of the comparator 12 can be supplied / shut off to the successive approximation register 13 via a transmission gate G1 such as an AND gate. The transmission gate G1 is controlled by the control circuit 15 by the local DA conversion circuit 14. When the conversion is started, the output of the comparator 12 is transmitted to the successive approximation register 13, and when the normal DA conversion is completed, the transmission of the output of the comparator 12 to the successive approximation register 13 is controlled.

Next, the operation procedure of the AD conversion circuit of this embodiment will be described with reference to FIG. FIG. 8 shows the level of the output voltage (Vref) of the local DA converter circuit for each cycle, with the horizontal axis representing the time axis.

In FIG. 8, a period indicated by a symbol T1 is a period in which a normal AD conversion operation using the local DA converter circuit 14 is performed, and the same number of times (n times) as the number of weighting capacitors while switching the DAC output. ) Is only compared. A period indicated by a symbol T2 is a period in which a redundant comparison operation using the sub DA conversion circuit is performed, and the same sequence is repeated a plurality of times (m times) in the redundant comparison. In each redundancy comparison, the comparison is performed k times by switching the switches SW11... SW1k in FIG.

Furthermore, the redundant comparison performed after the normal AD conversion is started by using the conversion result obtained by the normal AD conversion as a start value, that is, without newly sampling while holding the AD conversion value in the successive approximation register. Although not shown in FIG. 8, when m redundant comparison sequences are completed, the low-order bits of the normal AD conversion result and the k redundant comparison results are averaged, and the average value is determined according to the average value. Then, addition or subtraction is performed on a value obtained by normal AD conversion and held in the successive approximation register.

During normal AD conversion operation (including sampling), the voltage Vref_h is applied to the terminal of the largest capacitor CDAk by the changeover switch SW1k in the sub DA converter circuit, and the terminals of the capacitors CDAk-1 to CDA1 smaller than that. The voltage Vref_l is applied to the switch SW1k-1 to SW11. In the redundant comparison, first, the voltage applied to the terminal of the largest capacitor CDAk is switched from Vref_h to Vref_l by the switch SW1k. As a result, the same state as when the reference voltage Vref output from the local DA conversion circuit 14 is lowered is set. In this state, the comparator 12 operates and performs comparison, and then, according to the output of the comparator, the voltage applied to the terminals of the capacitors CDAk-1 to CDA1 is set to Vref_h or Vref_l, whereby redundant comparison is performed. .

According to a trial calculation by the present inventor, an SN ratio of 3 dB is improved by executing one redundancy comparison sequence after a normal AD conversion, and an SN ratio of 6 dB is executed by executing the redundancy comparison sequence three times, and the redundancy comparison sequence is executed 15 times. It was found that the SN ratio could be improved by 12 dB. Therefore, if the allowable deviation of the AD conversion output is 2 codes, +3 redundant comparisons are performed, if the allowable deviation is 3 codes, +6 redundant comparisons are performed, and if the allowable deviation is 4 codes, +15 times are compared. It is desirable to perform a redundant comparison. Even when the redundant comparison sequence is executed 15 times, the change in the reference voltage is small and the settling time is shortened in the comparison of the lower bits, so that the comparison time can be made shorter than usual and the value of k is n. Since it can be made relatively small compared to the value, the conversion time does not increase drastically.

Further, regarding the number of comparisons in each redundant comparison sequence, that is, the number of bits of the sub DA conversion circuit, if the error generation range of the AD conversion output code = target value ± 2LSB, the conversion result in the normal AD conversion is shifted. In view of the above, it is preferable to make correction within a range of ± 4LSB, and a 3-bit redundant comparison (k = 3) may be used.

By the way, in the successive approximation AD converter circuit, an error is caused in the AD conversion result by taking in thermal noise generated by elements such as resistors and transistors during sampling or noise (substrate noise) due to leakage current flowing in the substrate into the sampling capacitor. In addition to this, an error occurs in the AD conversion result due to switching noise generated in the amplification stage at the time of comparison.

13A and 13B, the analog input voltage is taken on the horizontal axis, and the relationship between the switching frequency of the inverter and the code change of the AD conversion output is shown. Of these, FIG. 13A shows a case where the variation in switching frequency is small, and FIG. 13B shows a case where the variation in switching frequency is large.

13A and 13B, when the variation in switching frequency is small as shown in FIG. 13A, the conversion result is more stable than the upper graph and there is less possibility of an error, but the switching frequency as shown in FIG. 13B. It can be seen that when the variation in the number is large, the conversion result becomes unstable and an error is likely to occur. Specifically, when ± 3.3σ becomes wider than 1 LSB (for example, 1 mV) when the variation in switching frequency has a normal distribution, a part of the switching frequency distribution overlaps as shown in FIG. 13B. Even if an analog input is converted from analog to analog, a constant digital code output cannot be obtained, and an error is likely to occur.

In particular, an AD converter circuit including a chopper comparator often has characteristics as shown in FIG. 13B. On the other hand, in the present embodiment, after normal AD conversion, the conversion result is taken over and the lower bit redundancy comparison is performed a plurality of times and averaged to obtain an output code near the center of the distribution of FIG. 13B. Thus, a value obtained by correcting an error due to switching noise of the inverter or the like can be obtained.

When the AD conversion circuit is mounted on an LSI such as a microprocessor having a CPU (central processing unit), a register capable of setting the values of k and m by the CPU is provided, and the control circuit 15 However, it is also possible to configure the sub DA conversion circuit 17 to operate with the number of comparisons corresponding to the set value of this register.

FIG. 9 shows still another embodiment of the AD conversion circuit suitable for use with the chopper type comparator having the load capacity adjustment function of the present invention. Although not particularly limited, the load capacity adjusting means 16 is connected to the output terminal of the first-stage CMOS inverter INV1. Other CMOS inverters may be provided with load capacity adjusting means. Since the specific example and function of the load capacity adjusting means 16 are the same as those in the above embodiment, the description thereof is omitted.

In this embodiment, the chopper type comparator 12 includes three CMOS inverters INV1, INV21, INV31 connected in cascade via coupling capacitors C21, C31, and switches S1, S1 that short-circuit the input / output terminals for each inverter. S21 and S31 are provided, and the first comparator section CMP1 in which the comparison point shift circuit CPS1 is connected to the input side of the second-stage inverter INV21 and the first-stage inverter INV1 are shared, and the subsequent stages are connected via coupling capacitors C22 and C32. The second comparator section CMP2 in which two CMOS inverters INV22 and INV32 are connected in cascade and the comparison point shift circuit CPS2 is connected to the input side of the inverter INV22, and the logic circuit section LG. The outputs of the first and second comparator units CMP1 and CMP2 are supplied to the logic circuit unit LG, and the logic circuit unit LG generates control signals for the comparison point shift circuits CPS1 and CPS2 based on the two outputs. It is configured.

In the comparator unit CMP1, the switches S1, S21, and S31 are turned on during the sampling period and the inputs and outputs of the inverters INV1, INV21, and INV31 are short-circuited. Is equal to the potential. Therefore, in the sample and hold circuit 11, when the switch SS1 on the input terminal side is turned on by the sampling clock φs, the input analog voltage Vin is sampled in the sampling capacitor Cs with reference to VLT. That is, Cs is charged with a charge corresponding to the potential difference between VLT and Vin. The coupling capacitors C21 and C31 are charged with voltages (VLT21−VLT1) and (VLT31−VLT21) which are the differences between the logic threshold values of the inverters. Inverters INV22 and INV32 of the comparator unit CMP2 are turned on by the switches S22 and S32 between the input and output terminals, and similarly, the coupling capacitors C22 and C32 are charged with the voltage difference between the logic threshold values of the inverters.

At the time of comparison determination (hold period), in the sample and hold circuit 11, the reference side switch SS2 is turned on by the sampling clock / φs. As a result, charges corresponding to the potential difference (Vref−Vin) between the input analog voltage Vin and the comparison voltage Vref remain in the sampling capacitor Cs. Further, in the comparator 12, the switches S1, S21, and S31 are turned off by φs and the input / output of the inverters INV1, INV21, and INV31 is cut off, so that each inverter operates as an amplifier and outputs according to the input potential. Change.

At this time, the potential difference (Vref−Vin) is transmitted to the input terminal of the first-stage inverter INV1 via the sampling capacitor Cs, and the potential difference is gradually amplified by the inverters INV1, INV21, INV31 in the first comparator unit CMP1. Go. Similarly, in the second comparator unit CMP2, the potential difference is gradually amplified by the inverters INV1, INV22, INV32. As a result, a result of comparing the input analog voltage Vin and the comparison voltage Vref appears at the outputs of the inverters INV31 and INV32.

In this embodiment, the comparison point shift circuit CPS1 can be switched between a capacitor CS1 having one terminal connected to the input terminal of the inverter INV21 and a predetermined reference voltage Vref0 and Vref1 connected to the other terminal of the capacitor. Switch SW11. The comparison point shift circuit CPS2 includes a capacitor CS2 having one terminal connected to the input terminal of the inverter INV22, and a switch SW12 connected to the other terminal of the capacitor and capable of switching between predetermined reference voltages Vref0 and Vref2. It is comprised by. The capacitors CS1 and CS2 are the same as each other, and can have the same capacitance value as the smallest one of the weighting capacitors constituting the local DA converter circuit 14, for example.

The switches SW11 and SW12 perform a voltage switching operation so that voltages changing in opposite directions are applied to CS1 and CS2. That is, first, the same voltage reference voltage Vref0 is applied, then the voltage Vref1 higher than Vref0 is applied to one side, and the voltage Vref2 lower than Vref0 is applied to the other side. Be controlled. In addition, switching of the switches SW11 and SW12, that is, switching of the reference voltage is performed in synchronization with the sampling clock φs. Instead of applying the same voltage reference voltage Vref0 first, different voltages Vref1 and Vref2 are applied, and then a voltage Vref1 ′ higher than the first applied voltage Vref1 is applied to one and the other is lower than Vref2. The voltage Vref2 ′ may be applied.

As described above, the comparison point shift circuit CPS1 switches the voltage applied to the terminal of the capacitor CS1 in the direction of increasing from Vref0 to Vref1 during sampling and comparison operation, while the comparison point shift circuit CPS2 changes the capacitance CS2 of the capacitor CS1. By switching the voltage applied to the terminal in the direction of decreasing from Vref0 to Vref2, the comparison point shift circuit CPS1 extracts the charge from the capacitor C21, and the comparison point shift circuit CPS2 injects the charge into the capacitor C22. As a result, the comparison point shift circuit CPS1 changes the comparison voltage (comparison point) to Vref + ΔV1, and the comparison point shift circuit CPS2 outputs a determination result equivalent to the comparison point changed to Vref−ΔV2. Will come to be.

The change amounts ΔV1 and ΔV2 of the comparison point are distributed to the capacitors C21 and C22 by the charges injected by the capacitors CS1 and CS2 by the applied voltage changes ΔVref1 (= Vref1−Vref0) and ΔVref2 (= Vref0−Vref2). Can be expressed as an input conversion value by dividing by the gain A1 of the inverter INV1.

ΔV1 = CS1 / (C21 + CS1) × ΔVref1 / A1
ΔV2 = CS2 / (C22 + CS2) × ΔVref2 / A1
In the AD conversion circuit having n-bit resolution, ΔVref1, ΔVref2, CS1, and CS2 are set so as to satisfy ΔV1, ΔV2 ≦ FS / 2 ⁿ * 2 ^(k−2) during the k-th bit comparison operation. By doing so, a conversion result with few misjudgments can be obtained. Note that FS is a potential difference between an upper limit and a lower limit of a voltage range FSR (Full Scale Range) in which AD conversion is possible. When the values of the capacitors CS1 and CS2 are fixed as in the embodiment of FIG. 9, the voltage differences ΔVref1 and ΔVref2 before and after switching may be changed for each comparison operation.

Here, the operation principle of the chopper type comparator of the present embodiment will be described with reference to FIG. FIG. 11 shows a part of the comparison operation of the (n-1) th bit and the comparison operation of the (n-2) th bit. As shown in the figure, in the present embodiment, two comparison points are set by avoiding the original comparison point, that is, the comparison point set in the one having only one comparator unit, and shifting the comparison point up and down. Further, the shift amount of the comparison point is made smaller as the number of comparisons is followed.

Furthermore, the determination result is represented by, for example, three types of codes (1,0), (0, 1), and (0, 0) according to the input voltage range. Accordingly, the logic circuit unit LG of FIG. 9 is provided with a conversion circuit including a logic gate that generates the above three types of codes based on the outputs of the comparator units CMP1 and CMP2. The conversion circuit generates a code of (1, 0) when the outputs of the comparator units CMP1 and CMP2 are 1, 1, and generates a code of (0, 1) when the outputs of the CMP1 and CMP2 are 0, 1. When the outputs of CMP1 and CMP2 are 0 and 0, a code (0, 0) is generated. Such a circuit can be realized by an AND gate and an exclusive OR gate. The comparison point is always lower in the comparator unit CMP2, and the outputs of CMP1 and CMP2 do not become 1 and 0. Therefore, there is no need to consider a code corresponding to such a case.

Next, in the comparison operation of the (n-2) th bit, when it is (1, 0) according to the three types of codes indicating the determination result of the (n-1) th bit, As shown in (1), the comparison points are both shifted higher. When the determination result of the (n-1) th bit is (0, 1), the comparison is performed by shifting the comparison point closer as shown in (2), and the determination result is (0, 0). If it is, the comparison is performed by shifting the comparison points downward as shown in (3). That is, the next comparison operation is performed in any of the ranges (1), (2), and (3) according to the determination result (code) of the previous comparison operation.

FIG. 12A shows an example of a change in the output voltage of the local DAC during the conversion operation when AD conversion is performed according to the principle as described above. On the other hand, FIG. 12B shows a change in the output voltage of the local DAC when AD conversion is performed at the original comparison point using a conventional chopper comparator. Conventionally, due to the occurrence of a single determination mistake, particularly at an early stage, an erroneous determination is repeated with an inappropriate comparison voltage thereafter, and an incorrect AD conversion result is output as shown in FIG. 12B. There is. On the other hand, when the present embodiment for performing a comparison that avoids the original comparison point is applied, when the potential of the input voltage Vin is close to the original comparison point, an erroneous determination at the upper bits hardly occurs, and finally. It can be seen that a conversion result with few errors can be obtained.

The results (three types of 2-bit codes) obtained by repeating the comparison as described above are added by shifting one digit at a time, and the least significant bit is subjected to processing such as truncation, as shown in FIG. Thus, the original AD conversion result can be obtained. Therefore, the logic circuit portion LG of FIG. 9 is provided with an arithmetic circuit including a bit shifter (shift register), an adder, and the like. The processing of the least significant bit is not limited to rounding down and may be rounded up. When the AD conversion circuit is mounted on an LSI such as a microprocessor having a CPU, the above calculation may be performed by the CPU.

As described above, according to the AD conversion circuit of the present embodiment, the conventional chopper type comparator (corresponding to the first comparator unit) of FIG. 9 includes two inverters and two capacitive elements for AC coupling. By adding the second comparator unit and the comparison point shift circuit provided for each comparator unit, there is an effect that a highly accurate AD conversion result can be obtained without extending the conversion time. .

In addition, since the first-stage inverter INV1 is shared by the two comparator units, the output of the two comparator units is less likely to cause an error, and the scale of the added circuit can be reduced, greatly increasing the cost. It can be avoided.

Furthermore, in the above-described embodiment, it has been described that the deviation amount of the comparison point is reduced as the number of comparisons is followed. However, ΔVk = ΔVk while satisfying the condition of ΔVk ≦ FS / 2 ⁿ * 2 ^(k−2). −1 = ΔVk−2..., ΔVref1, ΔVref2 and CS1, CS2 may be set so that the shift amount of the comparison point is the same over the comparison of a plurality of bits. The number of elements constituting the point shift circuit can be reduced and the area can be reduced.

Although the invention made by the present inventors has been specifically described based on the embodiment, the present invention is not limited to the above embodiment. For example, in the above embodiment, a comparator in which three stages of CMOS inverters are cascade-connected is shown, but two inverters may be cascade-connected, or four inverters may be cascade-connected.

In the above embodiment, the CMOS inverter is used as the amplification stage constituting the chopper type comparator, but a single-ended differential amplifier circuit or a differential input-differential output amplifier circuit is used instead of the CMOS inverter. May be.

DESCRIPTION OF SYMBOLS 11 Sample hold circuit 12 Comparator 13 Successive comparison register 14 Local DA converter circuit 15 Control circuit 16 Load capacity adjustment means 17 Sub DA converter circuit CPS1, CPS2 Comparison point shift circuit SS1, SS2 Sampling switch S1, S2, S3 Short circuit switch Cs sampling capacity C2, C3 coupling capacity Cf feedback capacity

Claims

A comparison circuit that includes a plurality of amplification stages connected in cascade via a coupling capacitor, determines the magnitude of the input analog voltage and the comparison voltage, a register that sequentially captures and holds the determination result of the comparison circuit, and a value of the register A successive approximation AD converter circuit comprising: a local DA converter circuit that converts the voltage into a voltage and generates the comparison voltage;
Load capacity adjustment means connected to the output terminal of the amplification stage of the comparison circuit;
A control circuit for generating a signal for changing the capacity value of the load capacity adjusting means;
The capacity value of the load capacity adjusting means is reduced when converting the upper bits, and the capacity value of the load capacity adjusting means is increased when converting the lower bits. A successive approximation AD converter circuit characterized by the above.
The load capacitance so that the settling time of the output voltage of the amplification stage to which the load capacitance adjusting means is connected when converting the lower bits is the same as the maximum settling time when converting the upper bits 2. The successive approximation AD converter circuit according to claim 1, wherein a capacitance value of the adjusting means is changed.
The load capacitance adjusting means includes one or more capacitive elements and a switch element connected in series with any one of the capacitive elements, and the capacitance value is changed when the switch element is turned on or off. The successive approximation AD converter circuit according to claim 1, wherein the successive approximation AD converter circuit is provided.
A comparison circuit that includes a plurality of amplification stages connected in cascade via a coupling capacitor, determines the magnitude of the input analog voltage and the comparison voltage, a register that sequentially captures and holds the determination result of the comparison circuit, and a value of the register A successive approximation AD converter circuit comprising: a local DA converter circuit that converts the voltage into a voltage and generates the comparison voltage;
Load capacity adjustment means connected to the output terminal of the amplification stage of the comparison circuit;
A switch capable of switching between one or more capacitors having one terminal connected to the input terminal of the first amplification stage of the comparison circuit and a voltage applied to the other terminal of the capacitor based on the output of the comparison circuit A sub-DA conversion circuit having means;
Generates a control signal for the sub-D / A converter circuit in accordance with the output of the comparison circuit, causes the comparison circuit to perform a redundant comparison, averages the output of the comparison circuit, and generates a correction signal for the register value And a control circuit for generating a signal for changing the capacity value of the load capacity adjusting means;
The capacity value of the load capacity adjusting means is reduced when converting the upper bits, and the capacity value of the load capacity adjusting means is increased when converting the lower bits, and the local DA converter circuit A successive-approximation-type AD converter circuit configured to execute a redundant comparison operation using the sub-DA converter circuit by using the conversion result as a start value after a normal AD-converting operation using the A / D converter.
The control circuit performs a redundancy comparison using the sub DA conversion circuit a plurality of times, and performs an averaging process between a result of a normal AD conversion operation using the local DA conversion circuit and a result of the plurality of redundancy comparisons 5. The successive approximation AD converter circuit according to claim 4, wherein the register value can be changed according to the result of the averaging process.
A comparison circuit that includes a plurality of amplification stages connected in cascade via a coupling capacitor, determines the magnitude of the input analog voltage and the comparison voltage, a register that sequentially captures and holds the determination result of the comparison circuit, and a value of the register A local DA converter circuit that converts the voltage into a voltage and generates the comparison voltage; a load capacity adjustment means connected to the output terminal of the amplification stage of the comparison circuit; and a signal that changes the capacitance value of the load capacity adjustment means A successive approximation AD converter circuit comprising a control circuit, wherein the comparison circuit comprises:
A first comparison stage having a first amplification stage and a second comparison stage having a second amplification stage, each having a first amplification stage in common among the plurality of amplification stages and connected to each subsequent stage via a coupling capacitor;
A first comparison point shift circuit connected to the input terminal of the first amplification stage and a second comparison point shift circuit connected to the input terminal of the second amplification stage;
A logic circuit unit that generates a predetermined code in accordance with an output of the first comparison unit and an output of the second comparison unit, and performs a calculation process on the generated code to generate a value to be stored in the register;
The first comparison point shift circuit and the second comparison point shift circuit include the comparison circuit when amplifying a potential difference between the input analog voltage and the comparison voltage by the first comparison unit and the second comparison unit, respectively. Operates to shift the voltage by a predetermined amount in the opposite directions,
The control circuit sequentially reduces the capacity value of the load capacity adjusting means when converting the upper bits, and increases the capacity value of the load capacity adjusting means when converting the lower bits. Comparison type AD converter circuit.
Three types of the predetermined codes generated by the logic circuit unit are set,
When the first code is generated, in the next comparison operation, the local DA converter circuit generates a voltage higher than the comparison voltage in the previous comparison operation, and when the second code is generated, the next time. In the comparison operation, the local DA converter circuit generates the same voltage as the comparison voltage in the previous comparison operation. When the third code is generated, the local DA conversion circuit generates the voltage in the next comparison operation. 7. The successive approximation AD converter circuit according to claim 6, wherein the conversion circuit generates a voltage lower than a comparison voltage in the previous comparison operation.
The first comparison point shift circuit and the second comparison point shift circuit respectively include a first capacitor and a second capacitor having one terminal connected to the input terminal of the first amplification stage or the input terminal of the second amplification stage. A first changeover switch for switching a voltage applied to the other terminal of the first capacitor and a second changeover switch for switching a voltage applied to the other terminal of the second capacitor, the first changeover switch and the second switch 8. The successive approximation type AD converter circuit according to claim 6, wherein the direction of the voltage switched by the change-over switch is different.