CN106357268B - Comparator delay correction circuit, method and ADC in a kind of ADC - Google Patents
Comparator delay correction circuit, method and ADC in a kind of ADC Download PDFInfo
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- CN106357268B CN106357268B CN201610871262.4A CN201610871262A CN106357268B CN 106357268 B CN106357268 B CN 106357268B CN 201610871262 A CN201610871262 A CN 201610871262A CN 106357268 B CN106357268 B CN 106357268B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/10—Calibration or testing
- H03M1/1009—Calibration
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
- H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
- H03M1/462—Details of the control circuitry, e.g. of the successive approximation register
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Abstract
Comparator delay correction circuit in ADC provided by the present application, is arranged the logic circuit that is connected with latch in data register, and logic circuit controls latch output predetermined level signal in initial preset duration of current ADC clock cycle；After preset duration, the output of latch is exported depending on comparator.In this way, the latch of corresponding positions can be made to force to export level signal identical with input signal in the initial stage of each ADC clock cycle, i.e., the predetermined level signal for guaranteeing the latch output of corresponding positions to assume was influenced without the comparator output delay by a upper clock cycle, namely, the next bit conversion of ADC is not influenced by the output delay of upper bit comparison result, to guarantee that ADC is worked normally.
Description
Technical field
This application involves analog-digital converter technical field, more particularly to a kind of ADC (Analog-to-
Digital Converter, A-D converter) comparator delay correction circuit, method and ADC.
Background technique
ADC is widely applied in fields such as Industry Control, medical instrument and microprocessor submodule translation interfaces, and being used for will
Analog signal is converted to digital signal.
Comparator is the important module in ADC, the transmission delay of comparator be determine entire ADC conversion speed it is important
One of factor.
For example, SAR (successive approximation register) type ADC is to be compared by turn, that is, each clock cycle can only compare one
Secondary, N then need to compare n times.When the voltage infinite approach of two inputs of comparator, comparator output delay is more than one
Clock cycle, it will cause ADC that can not detect correct comparator output, and then ADC is caused to can not work normally.
It referring to Figure 1, is a kind of circuit structure schematic diagram of SAR ADC of the prior art, PA is the anti-phase input of comparator
End inputs the output of DAC (Digital-to-Analog Converter, digital-to-analog converter)；PB is the homophase input of comparator
End, inputs analog signal to be converted；SAR ADC gradually comparand register highest will set 1 first, and instruction DAC output is corresponding
Voltage signal is carried out to the inverting input terminal of comparator with the analog voltage signal Vi to be converted of comparator non-inverting input terminal input
Compare, if Vi is greater than the voltage signal of DAC output, comparator output is binary number " 1 ", conversely, comparator output two
System number " 0 ".Successively compare to the last one, at this point, final latch data and exporting, data, that is, Vi of final output is corresponding
Digital signal.
Fig. 2 is referred to, the waveform diagram of each key point in circuit shown in Fig. 1 is shown, ADC_CLK is the clock week of ADC
Phase, each clock cycle, interior comparison was primary；PA is the waveform diagram of the inverting input terminal of comparator；PB is the same mutually defeated of comparator
Enter the waveform diagram at end；COMP is the waveform diagram of the output end of comparator；CAP_PULSE is the control clock signal of trigger D1；
LATCH_PULSE is the control clock signal of latch D2, when rising edge occurs in LATCH_PULSE pulse, triggers latch
Latch the data of the Q0 output of D1；As shown in Fig. 2, COMP=1 in a upper clock cycle, in this clock cycle, the voltage at the end PA
Slightly larger than the voltage at the end PB, and the voltage of PA and PB is very close, and in this case, the output of comparator should be COMP=
0, still, comparator compares the end PA and the size of the end PB voltage takes a long time more than one clock cycle；At this point, D1 is triggered
Device detects the output COMP=1 of the output practical Shi Shangyi clock cycle of comparator, when LATCH_PULSE pulse rises
Along when, the data of a upper clock cycle are input in latch D2 by D1 trigger, cause latch D2 latch error in data,
And then ADC is caused to can not work normally.
Summary of the invention
In view of this, the application provides comparator delay correction circuit, method and ADC in a kind of ADC, to solve when comparing
When the voltage infinite approach of two input terminals input of device, the technical issues of analog-to-digital conversion converting machine can not work normally, this
Application provides the following technical solutions:
In a first aspect, the present invention provides comparator delay correction circuit in a kind of analog-digital converter ADC, the ADC includes
Digital analog converter DAC, comparator and data register, the data register include multistage latch；The first of the DAC is defeated
Enter the output end that end connects the data register, the second input terminal input reference voltage signal, output end connects the comparison
The inverting input terminal of device, the non-inverting input terminal of the comparator input voltage signal to be converted, comparator delay school in the ADC
Positive circuit includes: logic circuit and clock generation circuit, wherein every grade of latch connects a logic circuit；
The first input end of each logic circuit connects the output end of the comparator, and the second of the logic circuit
Input terminal connects the first output end of the clock generation circuit, and it is same that the output end of the logic circuit connects the logic circuit
The control terminal of the latch of level-one；The input terminal of the latch inputs predetermined level signal, the clock of the latch
Control terminal connects the second output terminal of the clock generation circuit；
The logic circuit exports in initial preset duration of current ADC clock cycle for controlling the latch
Predetermined level signal, and after the preset duration, control the output of comparator described in the latches；
The input terminal of the clock generation circuit inputs ADC clock cycle signal, when first output end exports first
Clock signal, the second output terminal export second clock signal.
Optionally, the predetermined level signal is high level signal.
Optionally, the latch is d type flip flop；
The input terminal of the d type flip flop is the input terminal of the latch, for inputting the predetermined level signal；It is described
The output end of d type flip flop is the output end of the latch, and the Clock control end of the d type flip flop is the clock of the latch
Control terminal, the reset terminal of the d type flip flop are the control terminal of the latch.
Optionally, the logic circuit includes NOR logic circuit；
The first input end of the NOR logic circuit is the first input end of the logic circuit, the or logic electricity
Second input terminal on road is the second input terminal of the logic circuit, and the output end of the NOR logic circuit is the logic electricity
The output end on road.
Optionally, the clock generation circuit includes pulse-generating circuit, and connect with the pulse-generating circuit
Delay circuit；
The input terminal of the pulse-generating circuit is the input terminal of the clock generation circuit, the pulse-generating circuit
Output end is the first output end of the clock generation circuit, and the output end of the delay circuit is the clock generation circuit
Second output terminal；
The pulse-generating circuit, for generating the pulse signal of one fixed width according to the ADC clock cycle signal；
The delay circuit, the pulse delay signal preset time output for exporting the pulse-generating circuit.
Second aspect, the present invention provide a kind of analog-digital converter ADC, comprising: digital analog converter DAC, comparator, data are posted
Storage and logic circuit, the data register include multistage latch, and every grade of latch connects the logic electricity
Road；
The first input end of the DAC connects the output end of the data register, the second input terminal input reference voltage
Signal, output end connect the inverting input terminal of the comparator；The non-inverting input terminal of the comparator inputs voltage letter to be converted
Number；
The first input end of each logic circuit connects the output end of the comparator, and the second of the logic circuit
Input terminal connects the first output end of the clock generation circuit, and it is same that the output end of the logic circuit connects the logic circuit
The control terminal of the latch of level-one；The input terminal of the latch inputs predetermined level signal, the clock of the latch
Control terminal connects the second output terminal of the clock generation circuit；
The logic circuit exports in initial preset duration of current ADC clock cycle for controlling the latch
Predetermined level signal, and after the preset duration, control the output of comparator described in the latches；
The input terminal of the clock generation circuit inputs ADC clock cycle signal, when first output end exports first
Clock signal, the second output terminal export second clock signal.
The third aspect, the present invention provide comparator time delay correction method in a kind of analog-digital converter ADC, are applied in ADC,
The ADC includes digital analog converter DAC, comparator, data register and logic circuit, and the data register includes multistage lock
Storage, every grade of register pair answer the logic circuit；The described method includes:
Within the current ADC clock cycle in initial preset duration, the logic circuit generates the first level signal, and will
First level signal is supplied in the data register and is in the latch with level-one with the logic circuit, so that institute
It states latch and exports predetermined level signal in the preset duration；
After initial preset duration of current ADC clock cycle, the logic circuit is according to the output of the comparator
Signal exports second electrical level signal, and the second electrical level signal is supplied to the latch, so that the latch is in institute
State the output signal that preset duration latches the comparator later.
Optionally, the predetermined level signal is high level signal.
Optionally, in the initial preset duration within the current ADC clock cycle, the logic circuit generates the first electricity
Ordinary mail number, comprising:
In initial preset duration of current ADC clock cycle, height that the logic circuit is inputted according to first input end
Level signal exports low level signal；
After the preset duration initial in the current ADC clock cycle, the logic circuit is according to the comparator
Output signal exports second electrical level signal, comprising:
It is described when the comparator exports high level signal after initial preset duration of current ADC clock cycle
Logic circuit exports low level signal；
It is described when the comparator exports low level signal after initial preset duration of current ADC clock cycle
Logic circuit exports high level signal.
Optionally, the output signal of the logic circuit is input to the reset terminal of the latch, the method also includes:
After initial preset duration of current ADC clock cycle, when the logic circuit exports high level signal, control
Make the latch output low level signal；When the logic circuit exports low level signal, the latch output is controlled
High level signal.
It can be seen via above technical scheme that compared with prior art, comparator delay correction in ADC provided by the present application
Circuit, be arranged the logic circuit that is connected with latch in data register, logic circuit the current ADC clock cycle initially
In preset duration, control latch exports predetermined level signal；After preset duration, the output of latch depends on comparator
Output.In this way, the latch of corresponding positions can be made to force output and input signal phase in the initial stage of each ADC clock cycle
Same level signal, that is, the latch output for guaranteeing corresponding positions was the predetermined level signal of hypothesis without by a upper clock cycle
Comparator output delay influence, that is, ADC next bit conversion by a upper bit comparison result output delay do not influenced,
To guarantee that ADC is worked normally.
Detailed description of the invention
In order to illustrate the technical solutions in the embodiments of the present application or in the prior art more clearly, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
The embodiment of application for those of ordinary skill in the art without creative efforts, can also basis
The attached drawing of offer obtains other attached drawings.
Fig. 1 shows the circuit structure schematic diagram of existing SAR ADC a kind of；
Fig. 2 shows the waveform diagrams of each key point of circuit shown in Fig. 1；
Fig. 3 shows the schematic diagram of the comparator delay correction circuit in a kind of ADC of the embodiment of the present application；
Fig. 4 shows a kind of specific adc circuit schematic illustration of the embodiment of the present invention；
Fig. 5 shows the corresponding waveform diagram of each key point of circuit shown in Fig. 4；
Fig. 6 shows the flow chart of comparator time delay correction method in a kind of ADC of the embodiment of the present invention.
Specific embodiment
Below in conjunction with the attached drawing in the embodiment of the present application, technical solutions in the embodiments of the present application carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of embodiments of the present application, instead of all the embodiments.It is based on
Embodiment in the application, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall in the protection scope of this application.
Fig. 3 is referred to, the schematic diagram of the comparator delay correction circuit in a kind of ADC of the embodiment of the present application is shown, it should
Circuit is applied in SAR ADC, as shown in figure 3, the circuit includes digital analog converter (DAC) 100, comparator 200, data
Register 300 and clock generation circuit 400, each data register 300 include multi-level register, and every grade of register includes patrolling
Collect circuit 310 and latch 320.
Data register 300, for being produced as the binary data of DAC input, meanwhile, latch the output knot of comparator
Fruit；The flip flop number for including in data register 300 is identical as the digit of ADC.
DAC100, for the reference voltage V according to inputREF, and the binary data of input, export corresponding simulation
Voltage signal and the inverting input terminal for being input to comparator 200.
The non-inverting input terminal of comparator 200 inputs voltage signal to be converted, and the voltage signal with inverting input terminal input
It is compared, obtains comparison result, comparison result latches the corresponding positions of interior data register 300.
It following is a brief introduction of the working principle of ADC:
First, it is assumed that highest order is binary one in data register 300, other positions are binary number " 0 ", and should
Binary data is supplied to DAC, so that DAC exports corresponding analog voltage signal according to reference voltage.
For example, assuming that the highest order of data register 300 is " 1 " for the first time, then this latch for 8 ADC
In data be " 1,000 0000 " and be supplied to DAC100, if the reference voltage of DAC100 input is VREF, then DAC100 is defeated
Analog voltage out is VREF/2。
The voltage signal of DAC100 output is transmitted to the inverting input terminal of comparator 200, the electricity more to be converted of comparator 200
Signal and the voltage signal of inverting input terminal input is pressed to compare if voltage signal to be converted is greater than the voltage signal of DAC output
It is high level compared with the output of device 200, and the high level is latched into the highest order of data register 300, that is, data register is most
High-order is finally " 1 "；, whereas if voltage signal to be converted is less than the voltage signal of DAC output, then comparator 200 exports low
Level, and the low level signal is latched into the highest order of data register 300, that is, the highest order of data register 300 is final
For " 0 ".
Then, it is assumed that time high-order process for being " 1 ", repeating that above-mentioned highest order is " 1 " of data register 300, finally
Obtain time actual value of a high position.Above-mentioned process is repeated by turn, the data in final data register, that is, voltage pair to be converted
The digital signal answered.
The present invention is improved to data register, and when gradually comparing, when gradually comparing a certain position, which is posted
Storage is exported in the preset duration of ADC clock cycle as " 1 ", that is, total energy guarantees the input initial stage of next bit register
" 1 " is inside remained, without the comparison result delay by upper one.
As shown in figure 3, every grade of register of data register 300 includes a latch 320 and a logic circuit
310。
The first input end of the output end connection logic circuit 310 of comparator 200, the second input terminal of logic circuit 310
Input the first clock signal, the control terminal of the output end connection latch 320 of logic circuit 310.The input terminal of latch 320 is defeated
Enter predetermined level signal, Clock control end inputs second clock signal.Latch 320 is used to provide preset number letter for DAC100
Number, then, the output result of latched comparator.
400 input terminal of clock generation circuit inputs ADC clock cycle signal, and the first output end exports the first clock signal,
Second output terminal exports second clock signal.
The corresponding logic circuit 310 of present bit exports corresponding level letter in ADC clock cycle initial preset duration
Number it is supplied to latch 320, so that latch 320 is exported in preset duration as predetermined level signal；Moreover, in preset duration
Later, the output of latch 400 depends on the output of the comparator 200.
In one possible implementation of the present invention, predetermined level signal is high level signal, that is, latch 320
Input terminal input high level signal makes ADC clock cycle of the latch 320 after control clock arrives by logic circuit 300
High level signal is exported in initial preset duration.After preset duration, the output of latch 320 depends on comparator 200
Output, if the output of comparator 200 is high level signal, latch 320 exports high level signal；If comparator 200 is defeated
It is out low level signal, then latch 320 exports low level signal.
Comparator delay correction circuit in ADC provided in this embodiment, is arranged in data register and is connected with latch
Logic circuit, logic circuit exports latch in the ADC clock cycle initial preset duration after control clock arrives
Identical level signal is inputted with latch；After preset duration, the output of latch is exported depending on comparator.In this way,
The latch of corresponding positions can be made to force to export level letter identical with input signal in the initial stage of each ADC clock cycle
Number, that is, guaranteed that the latch output of corresponding positions was defeated without the comparator by a upper clock cycle for the predetermined level signal assumed
The influence being delayed out, that is, the next bit conversion of ADC is not influenced by the output delay of upper bit comparison result, to guarantee ADC
It works normally.
Fig. 4 is referred to, shows a kind of specific adc circuit schematic illustration of the embodiment of the present invention, in the present embodiment, is patrolled
Collecting circuit can make latch force output high level signal in ADC initial stage clock cycle.
As shown in figure 4, logic circuit is NOR logic circuit, latch is d type flip flop.
The inverting input terminal PA of the output end connection comparator C of DAC, the non-inverting input terminal PB input of comparator C are to be converted
Voltage signal, an input terminal of the output end connection NOR logic circuit of comparator C.
Another input terminal input of NOR logic circuit has the first clock signal, the output end connection of NOR logic circuit
The reset terminal CLR of d type flip flop.First clock signal is the pulse in the initial preset duration of ADC clock cycle for high level
Signal.
Input terminal input high level the signal VDD, output end Q of d type flip flop are the output of a certain position ADC；D type flip flop when
Clock control terminal inputs second clock signal.
Preferably, clock generation circuit includes pulse-generating circuit 410 and delay circuit 420, pulse-generating circuit 410
Input terminal input has ADC clock cycle signal, and the output end of pulse-generating circuit 410 connects the input terminal of delay circuit 420, together
When, the output end of pulse-generating circuit 410 exports the first clock signal；The output end output second clock letter of delay circuit 420
Number.That is, second clock signal lags a period of time than the first clock signal.
Fig. 5 is referred to, shows the corresponding waveform diagram of each key point of circuit shown in Fig. 4, this Figure only shows one
Each signal waveform of a ADC clock cycle.
ADC_CLK is the clock cycle of ADC, and comparison is primary in each clock cycle；PA is the anti-phase input of comparator C
The waveform diagram at end；PB is the waveform diagram of the non-inverting input terminal of comparator C；COMP is the waveform diagram of the output end of comparator C；CAP_
PULSE is the control clock signal of d type flip flop, and CAP_PULSE0 is the first clock signal of NOR logic circuit input；
In conjunction with Fig. 4 and Fig. 5, in ADC_CLK between high period, t0-t2 period CAP_PULSE0 is high level, even
One input terminal of logical not component is " 1 ", at this point, no matter COMP is high level or low level, NOR logic circuit output
It is always low level；At this point, d type flip flop CLR input be low level, wherein the end CLR of d type flip flop be high level effectively (that is,
When the end CLR input high level, the output of d type flip flop output end is " 0 "), therefore, the output end Q of d type flip flop remains input terminal
Level signal VDD, that is, within the t0-t2 period, the output regardless of comparator, the output of d type flip flop is all VDD.
After instant t 2, CAP_PULSE0 is low level, i.e., NOR logic circuit a input terminal is " 0 ", at this point,
The output of NOR logic circuit depends on another input terminal (COMP)；If COMP is high level, NOR logic circuit is defeated
It is out low level, the input of the end CLR is low level, and d type flip flop output end is identical as its input terminal, is high level VDD；If COMP
For low level, then NOR logic circuit output is high level, and the level of the end the CLR input of d type flip flop is effective, therefore, d type flip flop
Output is " 0 ".It can be seen that the output of d type flip flop depends on the output COMP of comparator after the t2 moment, if COMP is high electricity
Flat, then d type flip flop exports high level；If COMP is low level, d type flip flop exports low level, that is, is locked using d type flip flop
Deposit the output result of comparator.
Preferably, CAP_PULSE ratio CAP_PULSE0 lag a period of time (that is, t1-t0), this lag time difference to
Guarantee that the output signal of NOR logic circuit is transferred to d type flip flop.
Comparator delay correction circuit in ADC provided in this embodiment, using logic circuit control latch in ADC clock
Output inputs identical level signal with latch in period initial preset duration；After preset duration, latch it is defeated
Comparator is depended on out to export.In this way, the latch pressure of corresponding positions can be made defeated in the initial stage of each ADC clock cycle
Level signal identical with input signal out, that is, the latch output for guaranteeing corresponding positions is the predetermined level signal of hypothesis, without
It was influenced by the comparator output delay of a upper clock cycle, that is, the next bit conversion of ADC is not defeated by upper bit comparison result
The influence being delayed out, to guarantee that ADC is worked normally.
Corresponding to comparator delay correction circuit embodiment in above-mentioned ADC, the present invention also provides comparators in ADC to prolong
When bearing calibration embodiment.
Fig. 6 is referred to, the flow chart of comparator time delay correction method in a kind of ADC of the embodiment of the present invention, the party are shown
Method is applied in above-mentioned ADC in comparator delay correction circuit, and the ADC includes DAC, comparator, data register and patrols
Circuit is collected, the data register includes multistage latch, and every grade of register pair answers the logic circuit；The side
Method includes:
S110, within the current ADC clock cycle in initial preset duration, the logic circuit generates the first level letter
Number, and first level signal is supplied in the data register and is in the latch with level-one with the logic circuit
Device, so that the latch exports predetermined level signal in the preset duration.
In one possible implementation of the present invention, the predetermined level signal is high level signal.
In initial preset duration of current ADC clock cycle, height that the logic circuit is inputted according to first input end
Level signal exports low level signal.
S120, after initial preset duration of current ADC clock cycle, the logic circuit is according to the comparator
Output signal exports second electrical level signal, and the second electrical level signal is supplied to the latch, so that the latch
The output signal of the comparator is latched after the preset duration.
It is described when the comparator exports high level signal after initial preset duration of current ADC clock cycle
Logic circuit exports low level signal, and the latch exports high level signal；When the comparator exports low level signal,
The logic circuit exports high level signal, and the latch exports low level signal.
Comparator time delay correction method in ADC provided in this embodiment, is arranged in data register and is connected with latch
Logic circuit, the logic circuit control latch output predetermined level letter in initial preset duration of current ADC clock cycle
Number；After preset duration, the output of latch is exported depending on comparator.In this way, in the initial rank of each ADC clock cycle
Duan Douneng makes the latch of corresponding positions force to export level signal identical with input signal, that is, guarantees the latch of corresponding positions
Output was influenced for the predetermined level signal assumed without the comparator output delay by a upper clock cycle, that is, under ADC
One conversion is not influenced by the output delay of upper bit comparison result, to guarantee that ADC is worked normally.
For the various method embodiments described above, for simple description, therefore, it is stated as a series of action combinations, but
Be those skilled in the art should understand that, the application is not limited by the described action sequence because according to the application, certain
A little steps can be performed in other orders or simultaneously.Secondly, those skilled in the art should also know that, it is retouched in specification
The embodiment stated belongs to preferred embodiment, necessary to related actions and modules not necessarily the application.
Each embodiment in this specification is described in a progressive manner, the highlights of each of the examples are with other
The difference of embodiment, the same or similar parts in each embodiment may refer to each other.For device disclosed in embodiment
For, since it is corresponded to the methods disclosed in the examples, so being described relatively simple, related place is said referring to method part
It is bright.
Finally, it is to be noted that, herein, relational terms such as first and second and the like be used merely to by
One entity or operation are distinguished with another entity or operation, without necessarily requiring or implying these entities or operation
Between there are any actual relationship or orders.Moreover, the terms "include", "comprise" or its any other variant meaning
Covering non-exclusive inclusion, so that the process, method, article or equipment for including a series of elements not only includes that
A little elements, but also including other elements that are not explicitly listed, or further include for this process, method, article or
The intrinsic element of equipment.In the absence of more restrictions, the element limited by sentence "including a ...", is not arranged
Except there is also other identical elements in the process, method, article or apparatus that includes the element.
For convenience of description, it is divided into various units when description apparatus above with function to describe respectively.Certainly, implementing this
The function of each unit can be realized in the same or multiple software and or hardware when application.
As seen through the above description of the embodiments, those skilled in the art can be understood that the application can
It realizes by means of software and necessary general hardware platform.Based on this understanding, the technical solution essence of the application
On in other words the part that contributes to existing technology can be embodied in the form of software products, the computer software product
It can store in storage medium, such as ROM/RAM, magnetic disk, CD, including some instructions are used so that a computer equipment
(can be personal computer, server or the network equipment etc.) executes the certain of each embodiment of the application or embodiment
Method described in part.
The foregoing description of the disclosed embodiments makes professional and technical personnel in the field can be realized or use the application.
Various modifications to these embodiments will be readily apparent to those skilled in the art, as defined herein
General Principle can be realized in other embodiments without departing from the spirit or scope of the application.Therefore, the application
It is not intended to be limited to the embodiments shown herein, and is to fit to and the principles and novel features disclosed herein phase one
The widest scope of cause.
Claims (10)
1. comparator delay correction circuit in a kind of analog-digital converter ADC, the ADC include digital analog converter DAC, comparator and
Data register, the data register include multistage latch；The first input end of the DAC connects the data register
Output end, the second input terminal input reference voltage signal, output end connects the inverting input terminal of the comparator, the comparison
The non-inverting input terminal of device inputs voltage signal to be converted, which is characterized in that comparator delay correction circuit includes: in the ADC
Logic circuit and clock generation circuit, wherein every grade of latch connects a logic circuit；
The first input end of each logic circuit connects the output end of the comparator, the second input of the logic circuit
End connects the first output end of the clock generation circuit, and the output end of the logic circuit connects the same level-one of logic circuit
The latch control terminal；The input terminal of the latch inputs predetermined level signal, the clock control of the latch
End connects the second output terminal of the clock generation circuit；
The logic circuit, it is default for controlling latch output in initial preset duration of current ADC clock cycle
Level signal, and after the preset duration, control the output of comparator described in the latches；
The input terminal of the clock generation circuit inputs ADC clock cycle signal, and first output end exports the first clock letter
Number, the second output terminal exports second clock signal.
2. circuit according to claim 1, which is characterized in that the predetermined level signal is high level signal.
3. circuit according to claim 2, which is characterized in that the latch is d type flip flop；
The input terminal of the d type flip flop is the input terminal of the latch, for inputting the predetermined level signal；The D touching
The output end for sending out device is the output end of the latch, and the Clock control end of the d type flip flop is the when clock of the latch
End processed, the reset terminal of the d type flip flop are the control terminal of the latch.
4. circuit according to claim 2, which is characterized in that the logic circuit includes NOR logic circuit；
The first input end of the NOR logic circuit is the first input end of the logic circuit, the NOR logic circuit
Second input terminal is the second input terminal of the logic circuit, and the output end of the NOR logic circuit is the logic circuit
Output end.
5. circuit according to claim 2, which is characterized in that the clock generation circuit includes pulse-generating circuit, with
And the delay circuit being connect with the pulse-generating circuit；
The input terminal of the pulse-generating circuit is the input terminal of the clock generation circuit, the output of the pulse-generating circuit
End is the first output end of the clock generation circuit, and the output end of the delay circuit is the second of the clock generation circuit
Output end；
The pulse-generating circuit, for generating the pulse signal of one fixed width according to the ADC clock cycle signal；
The delay circuit, the pulse delay signal preset time output for exporting the pulse-generating circuit.
6. a kind of analog-digital converter ADC characterized by comprising digital analog converter DAC, comparator, data register, logic
Circuit and clock generation circuit, the data register include multistage latch, are patrolled described in every grade described latch connection one
Collect circuit；
The first input end of the DAC connects the output end of the data register, the second input terminal input reference voltage signal,
Output end connects the inverting input terminal of the comparator；The non-inverting input terminal of the comparator inputs voltage signal to be converted；
The first input end of each logic circuit connects the output end of the comparator, the second input of the logic circuit
End connects the first output end of the clock generation circuit, and the output end of the logic circuit connects the same level-one of logic circuit
The latch control terminal；The input terminal of the latch inputs predetermined level signal, the clock control of the latch
End connects the second output terminal of the clock generation circuit；
The logic circuit, it is default for controlling latch output in initial preset duration of current ADC clock cycle
Level signal, and after the preset duration, control the output of comparator described in the latches；
The input terminal of the clock generation circuit inputs ADC clock cycle signal, and first output end exports the first clock letter
Number, the second output terminal exports second clock signal.
7. comparator time delay correction method in a kind of analog-digital converter ADC, which is characterized in that be applied in ADC, the ADC packet
Digital analog converter DAC, comparator, data register, logic circuit and clock generation circuit are included, the data register includes more
Grade latch, every grade of register connect a logic circuit, wherein the first input end of each logic circuit
The output end of the comparator is connected, the second input terminal of the logic circuit connects the first output of the clock generation circuit
End, the output end of the logic circuit connect the logic circuit with the control terminal of the latch of level-one；The latch
Input terminal input predetermined level signal, the Clock control end of the latch connect the clock generation circuit second output
End；The described method includes:
Within the current ADC clock cycle in initial preset duration, the logic circuit generates the first level signal, and will be described
First level signal is supplied in the data register and is in the latch with level-one with the logic circuit, so that the lock
Storage exports predetermined level signal in the preset duration；
After initial preset duration of current ADC clock cycle, the logic circuit is according to the output signal of the comparator
Second electrical level signal is exported, and the second electrical level signal is supplied to the latch, so that the latch is described pre-
If latching the output signal of the comparator after duration.
8. the method according to the description of claim 7 is characterized in that the predetermined level signal is high level signal.
9. according to the method described in claim 8, it is characterized in that,
In the initial preset duration within the current ADC clock cycle, the logic circuit generates the first level signal, packet
It includes:
In initial preset duration of current ADC clock cycle, high level that the logic circuit is inputted according to first input end
Signal exports low level signal；
After the preset duration initial in the current ADC clock cycle, the logic circuit is according to the output of the comparator
Signal exports second electrical level signal, comprising:
After initial preset duration of current ADC clock cycle, when the comparator exports high level signal, the logic
Circuit output low level signal；
After initial preset duration of current ADC clock cycle, when the comparator exports low level signal, the logic
Circuit output high level signal.
10. according to the method described in claim 8, it is characterized in that, the output signal of the logic circuit is input to the lock
The reset terminal of storage, the method also includes:
After initial preset duration of current ADC clock cycle, when the logic circuit exports high level signal, institute is controlled
State latch output low level signal；When the logic circuit exports low level signal, the high electricity of latch output is controlled
Ordinary mail number.
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| CN201610871262.4A CN106357268B (en) | 2016-09-29 | 2016-09-29 | Comparator delay correction circuit, method and ADC in a kind of ADC |
| PCT/CN2017/076301 WO2018058900A1 (en) | 2016-09-29 | 2017-03-10 | Comparer delay correction circuit in adc, method and adc |
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| CN106357268B (en) * | 2016-09-29 | 2019-08-23 | 珠海格力电器股份有限公司 | Comparator delay correction circuit, method and ADC in a kind of ADC |
| CN107907173A (en) * | 2017-12-14 | 2018-04-13 | 湖北天禹环保科技有限公司 | A kind of analog-digital converter for ultrasonic gas flowmeter |
| CN109257023B (en) * | 2018-08-24 | 2022-10-14 | 中国电子科技集团公司第三十六研究所 | Power amplifier protection circuit and method |
| CN110535470B (en) * | 2019-08-26 | 2022-06-14 | 中国电子科技集团公司第二十四研究所 | Comparator clock generation circuit and high-speed successive approximation type analog-to-digital converter |
| CN113497619B (en) * | 2020-04-03 | 2024-01-26 | 龙芯中科技术股份有限公司 | Trigger circuit, control circuit and chip |
| CN111416621B (en) * | 2020-04-10 | 2023-06-02 | 中国科学院上海微系统与信息技术研究所 | Power consumption reduction circuit and method for current steering DAC |
| CN113114257B (en) * | 2021-04-19 | 2023-08-08 | 西安交通大学 | Sub-high-order advanced successive approximation analog-to-digital converter and control method |
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| US8482444B1 (en) * | 2011-07-28 | 2013-07-09 | The Boeing Company | Calibration of analog-to-digital converter data capture |
| KR20150072972A (en) * | 2013-12-20 | 2015-06-30 | 한국과학기술원 | Analog to Digital Converter for interpolation using Calibration of Clock |
| CN104967451A (en) * | 2015-07-31 | 2015-10-07 | 中国科学院电子学研究所 | Successive approximation type analog-to-digital converter |
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| CN105306059B (en) * | 2015-11-20 | 2018-06-19 | 中国科学院微电子研究所 | A kind of gradually-appoximant analog-digital converter device |
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| US8482444B1 (en) * | 2011-07-28 | 2013-07-09 | The Boeing Company | Calibration of analog-to-digital converter data capture |
| KR20150072972A (en) * | 2013-12-20 | 2015-06-30 | 한국과학기술원 | Analog to Digital Converter for interpolation using Calibration of Clock |
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| CN106357268A (en) | 2017-01-25 |
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