CN109412598B - Successive approximation type analog-to-digital conversion device - Google Patents

Successive approximation type analog-to-digital conversion device Download PDF

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CN109412598B
CN109412598B CN201811265671.5A CN201811265671A CN109412598B CN 109412598 B CN109412598 B CN 109412598B CN 201811265671 A CN201811265671 A CN 201811265671A CN 109412598 B CN109412598 B CN 109412598B
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CN109412598A (en
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李瑞兴
黄俊钦
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Hefei Songhao Electronic Technology Co ltd
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Hefei Songhao Electronic Technology Co ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/34—Analogue value compared with reference values
    • H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type

Abstract

The invention discloses a successive approximation type analog-to-digital conversion device, wherein an analog-to-digital conversion device SADC comprises a digital-to-analog conversion unit DAC, a comparison unit COMP and a logic control unit. The logic control unit comprises a plurality of D triggers DFF, a plurality of two-input OR gates, a three-input AND gate, a two-input NAND gate, an INV inverter AND a delay unit, AND the delay time of the delay unit is 5-10 ns. The implementation scheme provided by the invention has a simpler circuit architecture, and the corresponding layout area is smaller, thereby being more beneficial to development.

Description

Successive approximation type analog-digital conversion device
Technical Field
The invention relates to the technical field of analog-to-digital conversion, in particular to a successive approximation type analog-to-digital conversion device.
Background
An analog-to-digital converter (a/D converter, abbreviated as ADC) is an electronic component that converts an analog signal into a digital signal. Among various analog-to-digital converters, the successive approximation analog-to-digital converter SADC is often applied to the fields of wireless sensing nodes, consumer electronics, biomedical and the like because of its low power consumption, medium accuracy and high resolution. In each conversion process, the successive approximation type analog-to-digital converter compares the input analog signal with the analog signal one by traversing all the quantization values and converting the quantization values into the analog values, and finally obtains the digital signal to be output.
The successive approximation analog-to-digital converter SADC includes three parts, namely a digital-to-analog conversion unit DAC, a comparison unit COMP and a logic control unit, wherein the logic control unit is used as a core control component of the SADC. The SADC realizes the analog-to-digital conversion function by adopting a successive approximation mode, the conversion of 1-bit is realized in each SADC clock period through logic control, if the SADC of 10-bits needs to be realized, the analog-to-digital conversion of 10-bits can be realized only by 10 SADC clock periods, and the successive approximation process is shown in figure 1. The logic control unit of the system has the following functions: during the first clock period, the output of the DAC is controlled by the logic control unit to be the reference voltage VREF 1/2, then the input voltage is compared with the reference voltage VREF, if the input is larger than the current DAC output, the comparison unit is in a high level, otherwise, the comparison unit is in a low level. Then the logic control unit of the SADC needs to latch the comparison result of the current comparison unit, and in the next clock cycle, control the output of the DAC to be the reference voltage VREF of 3/4 (if the input voltage is greater than the reference voltage VREF of 1/2 in the first clock cycle) or control the output of the DAC to be the reference voltage VREF of 1/4 (if the input voltage is less than the reference voltage VREF of 1/2 in the first clock cycle) through the logic part, and then compare the input voltage with the current output of the DAC. The above process is repeated until the last bit.
The existing implementation scheme of the successive approximation type analog-to-digital conversion device has a complex circuit architecture and a large layout area corresponding to the circuit architecture, which becomes a problem to be solved urgently.
Disclosure of Invention
The invention provides a successive approximation type analog-to-digital conversion device.
The technical scheme adopted by the invention is as follows:
a successive approximation analog-to-digital conversion device SADC comprises a digital-to-analog conversion unit DAC, a comparison unit COMP and a logic control unit, and is characterized in that:
the device comprises a comparison unit, a clock signal generation unit, a common-mode voltage conversion unit, a clock signal conversion unit, a latch signal generation unit and a control unit, wherein the common-mode voltage is connected to a normal-phase input end of the comparison unit, an inverted-phase input end of the comparison unit is connected to an output end of the digital-to-analog conversion unit, a clock input end of the comparison unit is connected with the clock signal, a reset input end of the comparison unit is connected with a second output end of the comparison unit, a first output end of the comparison unit outputs a comparison result, and a second output end of the comparison unit outputs a latch signal;
the clock input end of the logic control unit is connected with a clock signal, the first input end of the logic control unit is connected to the first output end of the comparison unit, the second input end of the logic control unit is connected to the second output end of the comparison unit, the first output end of the logic control unit outputs a sampling control signal, and the second output end of the logic control unit outputs a digital code;
the sampling input end of the digital-to-analog conversion unit is connected with an analog signal, the first input end of the digital-to-analog conversion unit is connected to the first input end of the logic control unit, and the second input end of the digital-to-analog conversion unit is connected to the second output end of the logic control unit;
the logic control unit comprises a plurality of D triggers DFF, a plurality of two-input OR gates, a three-input AND gate, a two-input NAND gate, an INV inverter AND a delay unit, AND the delay time of the delay unit is 5-10 ns.
Further, the plurality of D flip-flops DFFs specifically include (2n +3) DFFs, all of which are rising edge samples, where (2n +1) DFFs of DFF1< n-1:0>, DFF2< n-1:0>, DFF <2n +3> are with reset terminals, one DFF of DFF <2n +1> is with set terminals, one DFF of DFF <2n +2> is with both set and reset terminals, and the priority of S is greater than the priority of R.
Further, the specific connection manner of the plurality of D flip-flops DFF includes: the S terminal of DFF <2n +1> is connected with the R terminals of DFF1< n-1:0> n DFFs AND is connected to the output of the three-input AND, the R terminals of DFF2< n-1:0> n DFFs are connected together AND are connected to the enable control ADC _ EN of SADC, the D terminals of DFF2< n-1:0> n DFFs are connected together AND are connected to the output COMP _ OUT of the comparison unit, AND the outputs of OR < n-1:0> n ORs respectively correspond to the DAC input of n-bits AND also correspond to the SADC output of n-bits.
Further, the specific connection manner of the plurality of D flip-flops DFF includes: the CK terminal of DFF <2n +1> is connected to the CK terminals of DFF1< n-1:0> n DFFs, and is connected to the clock input ADC _ CLK of SADC, the D terminal of DFF <2n +1> is connected to GND, the Q terminal of DFF <2n +1> is connected to the D terminal of DFF1< n-1>, the Q terminal of DFF1< n-1> is connected to the D terminal of DFF1< n-2>, and is also connected to one terminal of OR < n-1>, the other terminal of OR < n-1> is connected to the Q terminal of DFF2< n-1>, and the CK terminal of DFF2< n-1> is connected to the QN terminal of DFF1< n-1 >.
Further, the specific connection manner of the plurality of D flip-flops DFF includes: one end of OR < n-m > is connected with Q end of DFF1< n-m > and connected with D end of DFF1 in the next stage, one end of OR <0> in the last stage is connected with Q end of DFF1<0>, the other end of OR < n-m > is connected with Q end of DFF2< n-m >, CK end of DFF2< n-m > is connected with QN end of DFF1< n-m >, wherein m is 2-n;
the QN terminal of DFF1<0> is connected to CK terminal of DFF <2n +2>, R terminal of DFF <2n +2> is connected to the output terminal of NAND, AND is connected to the first input terminal of three-input AND, S terminal of DFF <2n +2> is connected to ADC _ EN directly, D terminal of DFF <2n +2> is connected to VDD, AND Q terminal of DFF <2n +2> is corresponding to EOC signal directly.
Further, the specific connection mode of the three-input AND gate includes: the second input end of the three-input AND is connected with the Q end of DFF <2n +3>, AND the third input end of the three-input AND is directly connected with ADC _ EN;
the D terminal of DFF <2n +3> is connected to VDD, the CK terminal of DFF <2n +3> is directly connected to ADC _ START signal, and the R terminal of DFF <2n +3> is directly connected to ADC _ EN.
Further, the specific connection mode of the two-input NAND gate includes: one input end of the NAND with two inputs is directly connected with the ADC _ START signal, and the other input end of the NAND with two inputs is connected with the output end of the INV; the input of INV is connected to the output of a delay cell, which is connected directly to the ADC _ START signal.
The technical scheme of the invention can obtain the following beneficial effects: the implementation scheme provided by the invention has a simpler circuit architecture, and the corresponding layout area is smaller, thereby being more beneficial to development.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the prior art descriptions will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 is a schematic diagram of a successive approximation process;
FIG. 2 is a schematic structural diagram of a successive approximation analog-to-digital conversion device;
FIG. 3 is a schematic diagram of a logic control unit;
FIG. 4 is a schematic structural diagram of a logic control unit in the 10-bits successive approximation analog-to-digital conversion device.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without making any creative effort based on the embodiments in the present invention, belong to the protection scope of the present invention.
Fig. 2 is a schematic structural diagram of a successive approximation analog-to-digital conversion device. The invention provides a successive approximation type analog-to-digital conversion device which comprises a digital-to-analog conversion unit DAC, a comparison unit COMP and a logic control unit.
The common-mode voltage is connected to a positive phase input end of the comparison unit, a negative phase input end of the comparison unit is connected to an output end of the digital-to-analog conversion unit, a clock input end of the comparison unit is connected with a clock signal, a reset input end of the comparison unit is connected with a second output end of the comparison unit, a first output end of the comparison unit outputs a comparison result, and a second output end of the comparison unit outputs a latch signal. The clock input end of the logic control unit is connected with a clock signal, the first input end of the logic control unit is connected to the first output end of the comparison unit, the second input end of the logic control unit is connected to the second output end of the comparison unit, the first output end of the logic control unit outputs a sampling control signal, and the second output end of the logic control unit outputs a digital code. The sampling input end of the digital-to-analog conversion unit is connected with an analog signal, the first input end of the digital-to-analog conversion unit is connected to the first input end of the logic control unit, and the second input end of the digital-to-analog conversion unit is connected to the second output end of the logic control unit.
The logic control unit comprises a plurality of D flip-flops DFF, a plurality of two-input OR gates, a three-input AND gate, a two-input NAND gate, an INV inverter AND a delay unit, wherein the delay time of the delay unit is 5-10 ns, AND FIG. 3 is a schematic structural diagram of the logic control unit. The sampling device comprises (2n +3) DFFs, all of which are rising edge sampling, wherein the DFFs 1< n-1:0>, 2< n-1:0>, 2n +3> and 2n +1 are provided with reset ends, the R is set to be 0 to indicate that the Q end output of the DFF is set to be 0, the DFF <2n +1> and the DFF are provided with set ends, the S is set to be 0 to indicate that the Q end output of the DFF is set to be 1, the DFF <2n +2> and the DFF are provided with set/reset ends at the same time, the S is set to be 0 to indicate that the Q end output of the DFF is set to be 1, the R is set to be 0 to indicate that the Q end output of the DFF is set to be 0, and the priority of S is higher than the priority of R.
The specific connection relationships of the plurality of D flip-flops DFF are as follows:
the S terminal of DFF <2n +1> is connected to the R terminals of DFF1< n-1:0> the n DFFs AND to the output of the three-input AND, the R terminals of DFF2< n-1:0> the n DFFs are connected together AND to ADC _ EN (i.e. the enable control of SADC), the D terminals of DFF2< n-1:0> the n DFFs are connected together AND to COMP _ OUT (i.e. the output of the comparison unit), the outputs of OR < n-1:0> the n ORs correspond to the DAC input of n-bits AND to the SADC output of n-bits, respectively. The CK terminal of DFF <2n +1> is connected to the CK terminals of DFF1< n-1:0> n DFFs, and is connected to ADC _ CLK (clock input of SADC), the D terminal of DFF <2n +1> is connected to GND (i.e. logic "0"), the Q terminal of DFF <2n +1> is connected to the D terminal of DFF1< n-1>, the Q terminal of DFF1< n-1> is connected to the D terminal of DFF1< n-2>, and is also connected to one terminal of OR < n-1>, the other terminal of OR < n-1> is connected to the Q terminal of DFF2< n-1>, and the CK terminal of DFF2< n-1> is connected to the QN terminal of DFF1< n-1 >.
The connection relationship (m takes a value from 2 to n) between DFF1< n-m >, DFF2< n-m > and OR < n-m > can be expressed as follows. One end of OR < n-m > is connected to Q terminal of DFF1< n-m > and connected to D terminal of DFF1 of next stage, one end of OR <0> of last stage is connected to Q terminal of DFF1<0>, the other end of OR < n-m > is connected to Q terminal of DFF2< n-m >, CK terminal of DFF2< n-m > is connected to QN terminal of DFF1< n-m >. The QN terminal of DFF1<0> is also connected to CK terminal of DFF <2n +2>, R terminal of DFF <2n +2> is connected to the output terminal of NAND, AND is connected to the first input terminal of three-input AND, S terminal of DFF <2n +2> is directly connected to ADC _ EN, D terminal of DFF <2n +2> is connected to VDD (logic '1'), AND Q terminal of DFF <2n +2> is directly corresponding to EOC signal. The second input terminal of the three-input AND is connected to the Q terminal of DFF <2n +3>, AND the third input terminal of the three-input AND is directly connected to ADC _ EN. The D terminal of DFF <2n +3> is coupled to VDD (i.e., logic "1"), the CK terminal of DFF <2n +3> is coupled directly to the ADC _ START signal, and the R terminal of DFF <2n +3> is coupled directly to ADC _ EN. One input of the two-input NAND is connected directly to the ADC _ START signal, while the other input is connected to the output of INV. The input of INV is connected to the output of a delay cell, which is connected directly to the ADC _ START signal.
Fig. 4 is a schematic structural diagram of a logic control unit in a 10-bits successive approximation analog-to-digital conversion device, which can be divided into four parts, namely (a), (b), (c) and (d) in fig. 4.
(a) The part is a shift register composed of 11 DFFs, wherein the first DFF is provided with set control S, and the next 10 DFFs are provided with reset control R, so that when the initialization is carried out, the states of Q10-Q0 are "10000000000", and after the initialization is completed, the 10 signals of Q9-Q0 jump from "0" to "1" in sequence and then jump back to "0" from "1" in sequence along with the input of ADC _ CLK clock. Meanwhile, the 10 signals QN 9-QN 0 also jump from "1" to "0" in sequence and then jump back from "0" to "1" in sequence with the input of the ADC _ CLK clock after the initialization is completed.
(b) The section includes 10 sets of DFFs and OR gates for latching the output result of the current comparing unit in each clock cycle of ADC _ CLK, and when QN has a rising edge, the corresponding COMP _ OUT, i.e. the output result of the current comparing unit, is latched, and it can be seen that QN 9-QN 0 will have a transition of rising edge in sequence with the input of ADC _ CLK clock in the whole conversion process of SADC.
(c) The part comprises a DFF, a three-input AND gate, a two-input NAND gate, an INV inverter AND a delay unit, wherein the delay unit delays for 5-10 ns AND is used for performing initialization configuration on the shift register of the first part. When ADC _ EN is equal to 0, the corresponding ADC is not enabled at this time, the output of DFF in this section is "0", the output of AND is also maintained at "0", AND the output state of the shift register corresponding to the first section is maintained at "10000000000". When ADC _ EN then jumps from "0" to "1", if the ADC _ START signal (a high-level pulse signal lasting for one ADC _ CLK) is not detected yet at this time, the output of the DFF remains at "0", so that the output state of the shift register of the first section continues to remain at the initial state. When the CK end of the DFF detects the rising edge of the ADC _ START, the output of the DFF is set to be 1, two input ends of the three-input AND gate are already 1, the last input end generates a low-level pulse signal, the pulse width of the low-level pulse signal is 5-10 ns designed in the delay unit, the last input end of the three-input AND gate is reset to be 1, the output end of the AND gate is reset to be 1, AND the initialization configuration is completed.
(d) And partially completing the correct generation and control of the EOC signal. When ADC _ EN is equal to 0, EOC is set to be 1, then when ADC _ EN jumps from 0 to 1, EOC signal is kept to be 1 until ADC _ START signal is generated, at this time, EOC signal is reset to 0, when rising edge jump of QN0 signal is detected, SADC output of last bit is generated, at this time, EOC signal is reset to 1, until next ADC _ START signal is generated, EOC signal is reset to 0, and next ADC conversion is started.
As will be appreciated by one skilled in the art, embodiments of the present invention may be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable non-transitory storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.

Claims (2)

1. A successive approximation analog-to-digital conversion device SADC comprises a digital-to-analog conversion unit DAC, a comparison unit COMP and a logic control unit, and is characterized in that:
the device comprises a comparison unit, a clock signal generation unit, a common-mode voltage conversion unit, a clock signal conversion unit, a latch signal generation unit and a control unit, wherein the common-mode voltage is connected to a normal-phase input end of the comparison unit, an inverted-phase input end of the comparison unit is connected to an output end of the digital-to-analog conversion unit, a clock input end of the comparison unit is connected with the clock signal, a reset input end of the comparison unit is connected with a second output end of the comparison unit, a first output end of the comparison unit outputs a comparison result, and a second output end of the comparison unit outputs a latch signal;
the clock input end of the logic control unit is connected with a clock signal, the first input end of the logic control unit is connected to the first output end of the comparison unit, the second input end of the logic control unit is connected to the second output end of the comparison unit, the first output end of the logic control unit outputs a sampling control signal, and the second output end of the logic control unit outputs a digital code;
the sampling input end of the digital-to-analog conversion unit is connected with an analog signal, the first input end of the digital-to-analog conversion unit is connected to the first input end of the logic control unit, and the second input end of the digital-to-analog conversion unit is connected to the second output end of the logic control unit;
the logic control unit comprises a plurality of D triggers DFF, a plurality of two-input OR gates, a three-input AND gate, a two-input NAND gate, an INV inverter AND a delay unit, AND the delay time of the delay unit is 5-10 ns;
the specific connection mode of the plurality of D flip-flops DFF includes: the S end of DFF <2n +1> is connected with the R ends of the n DFFs of DFF1< n-1:0> AND is connected to the output of the three-input AND, the R ends of the n DFFs of DFF2< n-1:0> are connected together AND are connected to the enable control ADC _ EN of the SADC, the D ends of the n DFFs of DFF2< n-1:0> are connected together AND are connected to the output COMP _ OUT of the comparison unit, the outputs of the n OR of OR < n-1:0> respectively correspond to the DAC input of the n-bits AND also correspond to the SADC output of the n-bits;
the specific connection mode of the plurality of D flip-flops DFF includes: the CK terminal of DFF <2n +1> is connected to the CK terminals of DFF1< n-1:0> n DFFs and simultaneously connected to the clock input ADC _ CLK of SADC, the D terminal of DFF <2n +1> is connected to GND, the Q terminal of DFF <2n +1> is connected to the D terminal of DFF1< n-1>, the Q terminal of DFF1< n-1> is connected to the D terminal of DFF1< n-2> and also connected to one terminal of OR < n-1>, the other terminal of OR < n-1> is connected to the Q terminal of DFF2< n-1>, and the CK terminal of DFF2< n-1> is connected to the QN terminal of DFF1< n-1 >;
the specific connection mode of the plurality of D flip-flops DFF includes:
one end of OR < n-m > is connected with Q end of DFF1< n-m > and connected with D end of DFF1 in the next stage, one end of OR <0> in the last stage is connected with Q end of DFF1<0>, the other end of OR < n-m > is connected with Q end of DFF2< n-m >, CK end of DFF2< n-m > is connected with QN end of DFF1< n-m >, wherein m is 2-n;
the QN end of DFF1<0> is connected with CK end of DFF <2n +2>, AND R end of DFF <2n +2> is connected with the output end of NAND, AND is connected with the first input end of three-input AND, S end of DFF <2n +2> is connected with ADC _ EN directly, AND D end of DFF <2n +2> is connected with VDD, Q end of DFF <2n +2> is corresponded with EOC signal directly;
the specific connection mode of the three-input AND gate comprises the following steps: the first input end of the three-input AND is connected with the output end of the NAND, the second input end of the three-input AND is connected with the Q end of the DFF <2n +3>, the third input end of the three-input AND is directly connected with the ADC _ EN, AND the output end of the three-input AND is connected with the S end of the DFF <2n +1 >;
d end of DFF <2n +3> is connected with VDD, CK end of DFF <2n +3> is connected with ADC _ START signal directly, R end of DFF <2n +3> is connected with ADC _ EN directly;
the specific connection mode of the two-input NAND gate comprises the following steps: one input end of the two-input NAND is directly connected with the ADC _ START signal, the other input end of the two-input NAND is connected with the output end of the INV, and the output end of the two-input NAND is connected with the R end of the DFF <2n +2 >; the input of INV is connected to the output of a delay cell, which is connected directly to the ADC _ START signal.
2. The successive approximation analog-to-digital conversion device according to claim 1, wherein:
the plurality of D flip-flops DFFs specifically comprise (2n +3) DFFs, all the DFFs are rising edge sampling, wherein the 2n +1 DFFs 1< n-1:0>, 2< n-1:0>, 2n +3> are provided with reset ends, the 2n +1 DFFs are provided with set end positions, the 2n +2 DFFs are provided with set and reset ends at the same time, and the priority of S is greater than that of R.
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