CN116248119A

CN116248119A - Digital-to-analog conversion circuit, chip and electronic equipment for PWM conversion analog output

Info

Publication number: CN116248119A
Application number: CN202211700884.2A
Authority: CN
Inventors: 袁剑涛; 王欢; 于翔
Original assignee: Junying Semiconductor Shanghai Co ltd
Current assignee: Junying Semiconductor Shanghai Co ltd
Priority date: 2022-12-28
Filing date: 2022-12-28
Publication date: 2023-06-09

Abstract

The embodiment of the disclosure provides a digital-to-analog conversion circuit, a chip and an electronic device for PWM conversion of analog output, wherein the digital-to-analog conversion circuit for PWM conversion of analog output comprises: the digital-to-analog conversion circuit comprises a PWM wave generation circuit and a filtering circuit, wherein the PWM wave generation circuit is configured to count a clock signal through a first counter, then generate a PWM wave according to a comparison result of an output value of the first counter and an input digital code value, the bit number of the first counter is the same as that of the input digital code value, and the frequency of a clock signal changes along with the preset conversion frequency of the digital-to-analog conversion circuit and the change of the bit number of the input digital code value; and the filter circuit is configured to filter the PWM wave to obtain an analog output signal. The problem that the existing DAC circuit of the type is low in precision and inconvenient to integrate is solved.

Description

Digital-to-analog conversion circuit, chip and electronic equipment for PWM conversion analog output

Technical Field

Embodiments of the present disclosure relate to the field of integrated circuit technology, and in particular, to a digital-to-analog conversion circuit, a chip, and an electronic device for PWM conversion of analog output.

Background

The digital-to-analog converter (Digital to analog converter, DAC) is also called a digital-to-analog converter. Implementations of the DAC include a variety of, with pulse width modulation (Pulse Width Modulation, PWM) DACs being one common implementation. The PWM DAC can realize the output of different analog levels by inputting the duty ratio of the digital code value control clock. The implementation of a PWM DAC typically includes two processes, PWM wave generation and filtering. Currently, in the implementation of PWM DACs, the generation of PWM waves is mainly divided into two types: one is implemented by an analog comparator, specifically by generating a sawtooth wave (such as by charging a constant current through a capacitor or an RC integrator, etc.) and a dc controllable level to output a PWM wave with an adjustable duty cycle through the comparator, the magnitude of the dc level can be changed to change the duty cycle. However, the analog modulation scheme has larger area and power consumption, and on the other hand, non-ideal factors such as offset of the comparator can influence the modulation precision. The other is realized by an additional MCU chip, in particular, the corresponding PWM wave is obtained by the control of an external MCU chip, but the scheme is not beneficial to integration.

In summary, how to provide a PWM DAC circuit with high precision and convenient integration is needed to be solved.

Disclosure of Invention

The embodiments described herein provide a digital-to-analog conversion circuit, a chip and an electronic device for PWM conversion of analog output, in order to provide a digital-to-analog conversion circuit for PWM conversion of analog output with high precision and easy integration.

According to a first aspect of the present disclosure, there is provided a digital-to-analog conversion circuit of PWM converting an analog output, comprising: the digital-to-analog conversion circuit comprises a PWM wave generation circuit and a filtering circuit, wherein the PWM wave generation circuit is configured to count a clock signal through a first counter, and then generate a PWM wave according to a comparison result of an output value of the first counter and an input digital code value, the bit number of the first counter is the same as that of the input digital code value, and the frequency of the clock signal changes along with the preset conversion frequency of the digital-to-analog conversion circuit and the change of the bit number of the input digital code value; the filter circuit is configured to perform filter processing on the PWM wave to obtain an analog output signal.

Optionally, the PWM wave generating circuit includes: the first counter, a plurality of first exclusive-OR gates, a first trigger and a second trigger, wherein the input end of the first counter is coupled with the clock signal, and each output end of the first counter is coupled with one input end of one first exclusive-OR gate; the other input end of each first exclusive-OR gate is coupled with one bit signal of the input digital code value, the output end of each first exclusive-OR gate is coupled with one input end of the OR gate, and the number of the first exclusive-OR gates is equal to the number of bits of the first counter; the output end of the OR gate is coupled with the clock end of the first trigger, the input end of the first trigger is respectively coupled with the second output end of the first trigger and the reset end of the second trigger, and the reset end of the first trigger is coupled with the reset end of the first counter; the input end of the second trigger is coupled with the power supply voltage, the clock end of the second trigger is coupled with the clock signal, and the first output end of the second trigger outputs the PWM wave.

Optionally, the filtering circuit performs filtering processing on the PWM wave through a combination of an RC low-pass filter and a notch filter, and the filtering circuit includes: the input end of the RC low-pass filter is coupled with the PWM wave, the output end of the RC low-pass filter is coupled with the input end of the notch filter, and the output end of the notch filter outputs the analog output signal.

Optionally, the notch filter includes: the system comprises two ping-pong mode sampling and holding circuits and a sampling clock generation circuit, wherein a first end of the sampling and holding circuit in a first ping-pong mode and a second end of the sampling and holding circuit in a second ping-pong mode are coupled together and are coupled with the output end of the RC low-pass filter; the second end of the sample-and-hold circuit in the first ping-pong mode and the first end of the sample-and-hold circuit in the second ping-pong mode are coupled together to output the analog output signal; the sampling clock generation circuit provides sampling clock signals for two sample hold circuits in ping-pong mode.

Optionally, the sample-and-hold circuit in ping-pong mode includes: the sampling circuit comprises a first switch, a second switch and a sampling capacitor, wherein one end of the first switch is coupled with one end of the second switch, the other end of the first switch is used as a first end of a sampling hold circuit in the ping-pong mode, and the other end of the second switch is used as a second end of the sampling hold circuit in the ping-pong mode; one end of the sampling capacitor is respectively coupled with one end of the first switch and one end of the second switch, and the other end of the sampling capacitor is coupled with the grounding end.

Optionally, the sampling clock generating circuit includes: the device comprises a delay module, a second counter, a second exclusive-OR gate, a plurality of third exclusive-OR gates, a NOR gate, a third trigger and a non-overlapping clock generation circuit, wherein the input end of the delay module is coupled with the clock signal, and the output end of the delay module is coupled with one input end of the second exclusive-OR gate; the other input end of the second exclusive-or gate is coupled with the clock signal, and the output end of the second exclusive-or gate is coupled with the input end of the second counter; the reset end of the second counter is coupled with a reset signal, the reset signal is a signal obtained by delaying an output signal of the reset end of the first counter by one period of the clock signal, each output end of the second counter is coupled with one input end of a third exclusive-OR gate, and the number of bits of the second counter is 1 greater than that of the input digital code value; the other input end of one of the plurality of third exclusive-OR gates is coupled with the ground end, and the other input end of each of the other third exclusive-OR gates is coupled with one bit signal of the input digital code value; the output end of each third exclusive-OR gate is coupled with one input end of the NOR gate; the output end of the NOR gate is coupled with the clock end of the third trigger, the input end of the third trigger is respectively coupled with the second output end of the third trigger and the input end of the non-overlapping clock generating circuit, and the reset end of the third trigger is coupled with the power supply voltage; the output end of the non-overlapping clock generation circuit outputs the sampling clock signal.

Optionally, the sampling clock signal includes a first sampling clock signal and a second sampling clock signal; wherein the first sampling clock signal controls the first switch and the second sampling clock signal controls the second switch.

Optionally, the frequency of the clock signal is 2 of the preset conversion frequency of the digital-to-analog conversion circuit ^N And (2) multiplying, wherein N is the number of bits of the input digital code value.

Optionally, the delay of the delay module is less than half of the period of the clock signal.

According to a second aspect of the present disclosure there is provided a chip comprising a digital to analogue conversion circuit for PWM converting an analogue output according to any one of the first aspects.

According to a third aspect of the present disclosure, there is provided an electronic device comprising the chip of the second aspect.

The digital-to-analog conversion circuit of PWM conversion analog output, the digital-to-analog conversion circuit of PWM conversion analog output in a chip and electronic equipment of the embodiment of the disclosure comprises a PWM wave generation circuit and a filter circuit, wherein the PWM wave generation circuit is configured to count clock signals through a first counter, then generate PWM waves according to a comparison result of an output value of the first counter and an input digital code value, the number of bits of the first counter is the same as that of the input digital code value, and the frequency of a clock signal changes along with the preset conversion frequency of the digital-to-analog conversion circuit and the change of the number of bits of the input digital code value; and the filter circuit is configured to filter the PWM wave to obtain an analog output signal. It can be seen that the PWM wave generating circuit in the digital-to-analog conversion circuit of the PWM conversion analog output of the embodiment of the present disclosure is a pure digital circuit, which can improve the accuracy compared to the implementation of the analog comparator, and in addition, does not use an additional chip such as an MCU, thus facilitating integration.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following brief description of the drawings of the embodiments will be given, it being understood that the drawings described below relate only to some embodiments of the present disclosure, not to limitations of the present disclosure, in which:

FIG. 1 is a schematic block diagram of a digital-to-analog conversion circuit for PWM converting an analog output in accordance with an embodiment of the present disclosure;

fig. 2 is an exemplary circuit diagram of a PWM wave generating circuit of an embodiment of the present disclosure;

FIG. 3 is a graph of output waveforms of respective key signals corresponding to the operation of FIG. 2;

FIG. 4 is a schematic block diagram of a filter circuit of an embodiment of the present disclosure;

FIG. 5 is a schematic block diagram of another filtering circuit of an embodiment of the present disclosure;

FIG. 6 is an exemplary circuit diagram of a sample-and-hold circuit in ping-pong mode according to an embodiment of the present disclosure;

FIG. 7 is an exemplary circuit diagram of a sampling clock generation circuit of an embodiment of the present disclosure;

FIG. 8 is a graph of output waveforms of respective key signals associated with operation of the circuit of FIG. 7;

elements in the figures are illustrated schematically and not drawn to scale.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings. It will be apparent that the described embodiments are some, but not all, of the embodiments of the present disclosure. All other embodiments, which can be made by those skilled in the art based on the described embodiments of the present disclosure without the need for creative efforts, are also within the scope of the protection of the present disclosure.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the presently disclosed subject matter belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the specification and relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. As used herein, a statement that two or more parts are "connected" or "coupled" together shall mean that the parts are joined together either directly or joined through one or more intermediate parts. In addition, terms such as "first" and "second" are used merely to distinguish one component (or portion of a component) from another component (or another portion of a component).

In order to solve the problems that the existing digital-to-analog conversion circuit for converting the analog output by PWM is low in precision and inconvenient to integrate, a novel digital-to-analog conversion circuit for converting the analog output by PWM is provided. The digital-to-analog conversion circuit of the PWM conversion analog output of the present disclosure is described in detail below.

As fig. 1 shows a schematic block diagram of a digital-to-analog conversion circuit 100 for PWM converting an analog output according to an embodiment of the present disclosure, comprising: a PWM wave generating circuit 110, and a filter circuit 120. Wherein the PWM wave generation circuit 110 is configured to count the clock signal CLK1 by the first counter I0 and then to input the digital code value DIN according to the output value of the first counter<N-1:0>The comparison result of the first counter generates PWM wave PWM_OUT, and the bit number of the first counter is compared with the input digital code value DIN<N-1:0>The number of bits of (a) is the same. "according to the output value of the first counter and the input digital code value DIN<N-1:0>The comparison result of (a) generates a PWM wave pwm_out "of: the output value of the first counter and the input digital code value DIN<N-1:0>Comparing the output value of the first counter with the input digital code DIN<N-1:0>When the same happens, the PWM wave PWM_OUT is high, so that the digital code value DIN can be input<N-1:0>During conversion, the high level of the PWM wave PWM_OUT is converted, and the PWM wave with adjustable duty ratio can be obtained. In addition, to meet the requirement, the frequency of the clock signal CLK1 is required to be according to the preset conversion frequency f of the digital-to-analog conversion circuit _out And inputting digital code value DIN<N-1:0>Is set for the number of bits. The clock signal CLK1 has a frequency corresponding to the preset conversion frequency f of the digital-to-analog conversion circuit _out And inputting digital code value DIN<N-1:0>And the number of bits of the number of bits. The specific clock signal CLK1 has a frequency of a preset conversion of the DACFrequency f _out 2 of (2) ^N Multiple of the input digital code DIN<N-1:0>Is a number of bits of (a). The filtering circuit 120 is coupled to the PWM wave generating circuit 110, and the filtering circuit 120 is configured to filter the PWM wave pwm_out to obtain the analog output signal Vout. The specific filter circuit 120 may be a first-order or higher-order RC low-pass filter circuit, and an exemplary diagram of a first-order RC low-pass filter circuit is provided at 121 in fig. 5. Of course, other RC low-pass filter circuits capable of implementing low-pass filtering may be used in practical applications.

Further, as shown in fig. 2, the PWM wave generating circuit 110 includes: first Counter (N-bit Counter) I ₀ A plurality of first exclusive-

OR gates

111, 112, a first flip-flop I ₁ Second trigger I ₂ Wherein the first counter I ₀ The input end of (1) is coupled to the clock signal CLK1, the first counter I ₀ Each output terminal ZOUT of (a)<N-1:0>An input terminal of a first exclusive-or gate 111 is coupled; the other input terminal of each first exclusive-OR gate 111 is coupled to input digital code value DIN<N-1:0>Each of the first exclusive-OR gates 111 has its output coupled to one of the inputs of the OR gates 112, the number of the first exclusive-OR gates 111 and the first counter I ₀ The number of bits is equal; the output end of the OR gate 112 (the output end outputs a signal of COK) is coupled to the first flip-flop I ₁ Is a clock terminal CLK, a first flip-flop I ₁ The input terminals D of (a) are respectively coupled to the first flip-flop I ₁ Is connected to the second output terminal of (2)

Second trigger I ₂ Is +.>

First trigger I ₁ Is +.>

A Reset terminal Reset coupled to the first counter I0; second trigger I ₂ The input terminal D of (1) is coupled to the power voltage VDD, the second flip-flop I ₂ The clock terminal CLK of (1) is coupled to the clock signal CLK1, the second flip-flop IThe first output terminal Q of 2 outputs the PWM wave pwm_out.

The operation principle of the PWM wave generation circuit 110 will be described with reference to the circuit diagram in fig. 2: assume that for a 3-bit digital-to-analog conversion circuit, a digital code value DIN is input<N-1:0>To DIN<2:0>First counter I ₀ For a 3bit counter, the number of first exclusive-or gates 111 is 3, and the frequency of the clock signal CLK1 is 8*f _out . When inputting digital code DIN<2:0>For 3' b001, the first counter I ₀ At the 1 st clock rising edge, 3' b001 is outputted, and the first counter I is outputted through a plurality of first exclusive OR gates 111 ₀ Output value of (a) and input digital code value DIN<2:0>The bit-by-bit comparison is then added by OR gate 112 to generate signal C_OK, which remains at 0 for the 1 st clock cycle and returns to 1 on the rising edge of the 2 nd clock, at which time the first flip-flop I is activated ₁ The t_reset signal is pulled low, pulling the value of pwm_out low on the rising edge of the 2 nd clock cycle. And a first counter I ₀ Will continue to operate until the count is full of 2 ³ After 8 clock cycles, outputting a RESET signal A_RESET of an overall circuit, and outputting I ₀ And I ₁ Reset, pwm_out also goes back high on the rising edge of the 9 th clock cycle, thus cycling through the process, and fig. 3 shows the output waveforms of the respective key signals during 8 clock cycles, in order from top to bottom: waveforms corresponding to CLK1, c_ok, t_reset, pwm_out, a_reset. Similarly, when the code value DIN is inputted<2:0>When switching between 3'b000 and 3' b111, the corresponding high level time of PWM_OUT is also switched, resulting in a duty cycle DIN<2:0>/2 ³ So that the level DIN can be finally obtained<2:0>/2 ³ * The analog output signal Vout of VDD. For N-bit digital-to-analog conversion circuits, only the first counter I needs to be modified ₀ The number of bits of (a) and the number of first exclusive or gates 111, the digital logic remains the same. In addition, it should also be noted that the first flip-flop I in the embodiments of the present disclosure ₁ Second trigger I ₂ The flip-flop with a reset terminal and capable of triggering on the rising edge of a clock, for example, the flip-flop can be the D flip-flop shown in fig. 2, the RS flip-flop, the JK flip-flop and the like can be fullA flip-flop with a reset terminal and capable of triggering on a clock rising edge.

From the above description, it can be seen that the PWM wave generating circuit in the digital-to-analog conversion circuit of the PWM conversion analog output of the embodiment of the present disclosure is a pure digital circuit, which can improve accuracy compared to the manner in which the analog comparator is implemented, and in addition, does not use an additional chip such as an MCU, thus facilitating integration.

Further, for the filtering circuit 120 in the above embodiment, since the circuit obtains the analog level through the first-order or high-order RC low-pass filtering, this scheme may cause the output analog signal to have a large ripple (for example, in fig. 8, rc_out is a schematic waveform obtained by filtering the PWM wave pwm_out based on the RC low-pass filter 121 in fig. 5, a large ripple may be seen), and the setup time is long when the RC has a large value. The embodiment of the disclosure provides a new implementation manner of the filter circuit 120, specifically, the filter circuit 120 performs filtering processing on the PWM wave pwm_out through a combination of an RC low-pass filter and a notch filter to obtain an analog output signal Vout. The PWM wave PWM_OUT is initially subjected to low-pass filtering through an RC low-pass filter, and generally presents a ripple wave similar to a triangular wave after passing through the RC low-pass filter, and the frequency of the ripple wave is the preset conversion frequency f of the digital-to-analog conversion circuit _out It is considered to use a notch filter to reduce the ripple of the analog output signal Vout. Fig. 4 shows an exemplary block diagram of the filter circuit 120 provided by an embodiment of the present disclosure, and as shown in fig. 4, the filter circuit 120 includes: an RC low-pass filter 121, a notch filter 122, wherein an input terminal of the RC low-pass filter 121 is coupled to the PWM wave pwm_out, an output terminal of the RC low-pass filter (an output terminal outputs an rc_out signal) is coupled to an input terminal of the notch filter 122, and an output terminal of the notch filter 122 outputs the analog output signal Vout. Further, as shown in fig. 5, the RC low-pass filter 121 includes a filter resistor R and a filter capacitor C, where the filter resistor R and the filter capacitor C form a first-order RC low-pass filter 121, and perform preliminary filtering processing on the PWM wave pwm_out output from the PWM wave generating circuit 110. It should be noted that the RC low-pass filter 121 in fig. 4 may be another RC low-pass filter structureFig. 5 is only an example, and may be a higher order RC low pass filter structure. As shown in fig. 5, the notch filter 122 includes: two ping-pong mode sample-and-hold circuits 1221, a sample clock generation circuit 1222, wherein a first end of the first ping-pong mode sample-and-hold circuit 1221 and a second end of the second ping-pong mode sample-and-hold circuit 1221 are coupled together and coupled to an output of the RC low-pass filter 121; the second terminal of the first ping-pong mode sample-and-hold circuit 1221 and the first terminal of the second ping-pong mode sample-and-hold circuit 1221 are coupled together to output the analog output signal Vout; the sampling clock generation circuit 1222 supplies the sampling clock signal (f) to the sample hold circuits 1221 of the two ping-pong modes _s 、

). Further, fig. 6 shows an exemplary circuit diagram of two ping-pong mode sample-and-hold circuits 1221. As shown in fig. 6, the sample-and-hold circuit 1221 of the ping-pong mode includes: the sampling circuit comprises a first switch S1, a second switch S2 and a sampling capacitor C0, wherein one end of the first switch S1 is coupled with one end of the second switch S2, the other end of the first switch S1 is used as a first end of a sampling hold circuit 1221 in a ping-pong mode, and the other end of the second switch S2 is used as a second end of the sampling hold circuit 1221 in the ping-pong mode; one end of the sampling capacitor C0 is coupled to one end of the first switch S1 and one end of the second switch S2, respectively, and the other end of the sampling capacitor C0 is coupled to the ground. Specifically, the sampling clock signal includes a first sampling clock signal +>

Second sampling clock signal->

First sampling clock signal f _s And a second sampling clock signal->

Are not overlapped with each other; wherein the first sampling clock signal f _s Control the first switch S1 and the second sampling clock signalNumber->

The second switch S2 is controlled. Sampling clock signal (f _s 、/>

) The sampling frequency of (a) is the preset conversion frequency f of the digital-to-analog conversion circuit _out So that the center frequency of notch filter 122 is f _out The sampling is always carried OUT on the slope of the same side of RC_OUT, so that the DC level shift is reduced, and the ripple is reduced. And by sampling the clock signal (f _s 、/>

) Can ensure that the digital code value DIN is different<N-1:0>The point of each sampling of the lower control corresponds to the middle point of the high level of the PWM_OUT, and finally an analog output signal Vout is obtained, wherein the Vout is of a level DIN<N-1:0>/2 ^N * Analog quantity of VDD.

Further, fig. 7 shows a method for generating a sampling clock signal (f _s 、

) An exemplary circuit diagram of the sample clock generation circuit 1222. As shown in fig. 7, the sampling clock generation circuit 1222 includes: delay module I ₃ Second Counter (N+1) -bit Counter) I ₄ A second exclusive-or gate 12221, a plurality of third exclusive-or gates 12222, a nor gate 12223, a third flip-flop I ₅ Non-overlapping clock generation circuit (Non-overlapping Clock generator) I ₆ Wherein, delay module I ₃ The input end of (1) is coupled to the clock signal CLK1, the delay module I ₃ Is coupled to an input of the second exclusive or gate 12221; the other input terminal of the second exclusive-or gate 12221 is coupled to the clock signal CLK1, and the output terminal (output terminal outputting the clk_d signal) of the second exclusive-or gate 12221 is coupled to the input terminal of the second counter I4; the Reset terminal Reset of the second counter I4 is coupled to the Reset signal A_RESET_D, which is the output of the Reset terminal Reset of the first counter I0The output signal A_RESET delays the signal after one period of the clock signal CLK1, the second counter I ₄ Each output terminal ZOUT of (a)<N:0>Coupled to an input of a third exclusive or gate 12222, a second counter I ₄ Bit ratio of input digital code value DIN<N-1:0>The number of bits is 1; the other input terminal of one third exclusive-OR gate 12222 of the plurality of third exclusive-OR gates 12222 is coupled to the ground GND, and the other input terminal of each of the other third exclusive-OR gates 12222 is coupled to the input digital code value DIN<N-1:0>Is a bit signal of (a); the output of each third exclusive-or gate 12222 is coupled to one input of the nor gate 12223; the output end of the NOR gate 12223 (output end outputting the D_OK signal) is coupled to the third flip-flop I ₅ Is a clock terminal CLK, a third flip-flop I ₅ The input terminals D of (a) are respectively coupled to the third flip-flop I ₅ Second output terminal +.>

Non-overlapping clock generation circuit I ₆ Is input to a third flip-flop I ₅ Is +.>

Coupling to a power supply voltage VDD; non-overlapping clock generation circuit I ₆ Outputs a sampling clock signal (f _s 、/>

). In addition, it should also be noted that the third flip-flop I in the embodiments of the present disclosure ₅ The flip-flop which is provided with a reset terminal and can be triggered on the rising edge of a clock, for example, the flip-flop D shown in fig. 7, the flip-flop RS, the flip-flop JK, and the like can be used as the flip-flop which is provided with the reset terminal and can be triggered on the rising edge of the clock.

The operation principle of the sampling clock generation circuit 1222 will be described with reference to fig. 7: first pass through delay module I ₃ Delaying the clock signal CLK1 for a period of time, then performing exclusive OR on the output result of the delay module I3 and the clock signal CLK1 to generate a double-frequency clock signal CLK_D signal, and then using a second (N+1) -bitCounter I ₄ Counting (where N is the input digital code value DIN<N-1:0>Such as when n=3, the second counter I ₄ Is a 4bit counter). This is done because the middle point of the high level of PWM_OUT is at the (DIN) th of the CLK_D signal after the multiplication of CLK1<N:0>+1) rising edge of clock, second counter I ₄ Is obtained by delaying the previous A_RESET signal by 1 CLK1 cycle, uses the A_RESET_D signal as the second counter I ₄ The 1 st cycle count of clk_d can be skipped to avoid the implementation of +1 circuit (to avoid adding 1 to the original code value, because adding an adder would increase the area consumption if it is needed, the present disclosure adds 1 to the clock, and the same effect is achieved by clock delay, which can reduce the area consumption). It should be noted that, for the delay module I ₃ Depending on the clock rate of CLK1, in particular the delay time may take any value less than 1/2 times the clock period of the clock signal CLK 1. The following circuit principle will be described by taking n=3 as an example, when the second counter I ₄ Output value ZOUT of (2)<3:0>And input digital code value DIN<2:0>After the corresponding, D_OK is high level, at this time I ₅ Is connected to the second output terminal of (2)

Is flipped and waits for the next I ₄ After reset, pass DIN<2:0>After a number of CLK_D cycles, CLKOUT is flipped again, so each time CLKOUT is flipped in the middle of the high level of PWM_OUT, then passed through a non-overlapping clock generation circuit I ₆ I.e. to adaptively generate a sample-and-hold clock signal, i.e. a sampling clock signal (f _s 、/>

). In addition, it should be noted that the digital-to-analog conversion circuit for N-bit only needs to modify the second counter I ₄ The number of bits of (a) and the number of third exclusive-or gates 12222 are identical.

Further, FIG. 8 showsDin=3' b001 sample clock signal (f _s 、

) Output waveforms of the respective key signals in the process are generated. As shown in fig. 8, from top to bottom: CLK1, clk_ D, PWM _out, a_reset_ D, D _ok, f _s 、/>

The waveform diagrams corresponding to the Vout and the RC_OUT are shown, wherein Sampling is taken as a Sampling point, the Sampling is always performed on the slope of the same side of the RC_OUT, the DC level shift is reduced, and compared with the RC_OUT, the ripple wave of the analog output signal Vout is obviously restrained.

From the above description, it can be seen that the filtering stage in the digital-to-analog conversion circuit of PWM conversion analog output according to the embodiments of the present disclosure adds a notch filter to greatly reduce the ripple of the output analog signal. On the basis of the foregoing embodiments, the digital-to-analog conversion circuit for PWM conversion analog output in the embodiments of the present disclosure is a DAC circuit with high precision, easy integration, and small ripple.

The embodiment of the disclosure also provides a chip. The chip includes digital-to-analog conversion circuitry for PWM converting an analog output according to an embodiment of the present disclosure. The chip is, for example, a chip for performing digital-to-analog signal conversion with high accuracy.

The embodiment of the disclosure also provides electronic equipment. The electronic device includes a chip according to an embodiment of the present disclosure. Such as automatic test equipment, and industrial process control equipment.

The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of apparatus and methods according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

As used herein and in the appended claims, the singular forms of words include the plural and vice versa, unless the context clearly dictates otherwise. Thus, when referring to the singular, the plural of the corresponding term is generally included. Similarly, the terms "comprising" and "including" are to be construed as being inclusive rather than exclusive. Likewise, the terms "comprising" and "or" should be interpreted as inclusive, unless such an interpretation is expressly prohibited herein. Where the term "example" is used herein, particularly when it follows a set of terms, the "example" is merely exemplary and illustrative and should not be considered exclusive or broad.

Further aspects and scope of applicability will become apparent from the description provided herein. It should be understood that various aspects of the disclosure may be implemented alone or in combination with one or more other aspects. It should also be understood that the description and specific examples are intended for purposes of illustration only and are not intended to limit the scope of the present disclosure.

While several embodiments of the present disclosure have been described in detail, it will be apparent to those skilled in the art that various modifications and variations can be made to the embodiments of the present disclosure without departing from the spirit and scope of the disclosure. The scope of the present disclosure is defined by the appended claims.

Claims

1. A digital-to-analog conversion circuit for PWM converting an analog output, comprising: a PWM wave generating circuit, a filtering circuit,

the PWM wave generation circuit is configured to count a clock signal through a first counter, and then generate PWM waves according to a comparison result of an output value of the first counter and an input digital code value, wherein the bit number of the first counter is the same as that of the input digital code value, and the frequency of the clock signal is changed along with the preset conversion frequency of the digital-to-analog conversion circuit and the change of the bit number of the input digital code value;

the filter circuit is configured to perform filter processing on the PWM wave to obtain an analog output signal.

2. The digital-to-analog conversion circuit of PWM converted analog output according to claim 1, wherein the PWM wave generating circuit comprises: a first counter, a plurality of first exclusive-OR gates, a first trigger and a second trigger,

wherein the input end of the first counter is coupled with the clock signal, and each output end of the first counter is coupled with one input end of a first exclusive-OR gate;

the other input end of each first exclusive-OR gate is coupled with one bit signal of the input digital code value, the output end of each first exclusive-OR gate is coupled with one input end of the OR gate, and the number of the first exclusive-OR gates is equal to the number of bits of the first counter;

the output end of the OR gate is coupled with the clock end of the first trigger, the input end of the first trigger is respectively coupled with the second output end of the first trigger and the reset end of the second trigger, and the reset end of the first trigger is coupled with the reset end of the first counter;

the input end of the second trigger is coupled with the power supply voltage, the clock end of the second trigger is coupled with the clock signal, and the first output end of the second trigger outputs the PWM wave.

3. The digital-to-analog conversion circuit of a PWM converted analog output according to claim 1, wherein the filter circuit performs a filter process on the PWM wave by a combination of an RC low-pass filter and a notch filter, the filter circuit comprising: an RC low pass filter, a notch filter,

the input end of the RC low-pass filter is coupled with the PWM wave, the output end of the RC low-pass filter is coupled with the input end of the notch filter, and the output end of the notch filter outputs the analog output signal.

4. A digital to analog conversion circuit for PWM converting an analog output according to claim 3, wherein said notch filter comprises: two ping-pong mode sample-hold circuits, a sample clock generation circuit,

the first end of the sample hold circuit in the first ping-pong mode and the second end of the sample hold circuit in the second ping-pong mode are coupled together and are coupled with the output end of the RC low-pass filter; the second end of the sample-and-hold circuit in the first ping-pong mode and the first end of the sample-and-hold circuit in the second ping-pong mode are coupled together to output the analog output signal;

the sampling clock generation circuit provides sampling clock signals for two sample hold circuits in ping-pong mode.

5. The digital to analog conversion circuit of claim 4, wherein said sample and hold circuit in ping-pong mode comprises: a first switch, a second switch, a sampling capacitor,

one end of the first switch is coupled with one end of the second switch, the other end of the first switch is used as a first end of the sample hold circuit in the ping-pong mode, and the other end of the second switch is used as a second end of the sample hold circuit in the ping-pong mode;

one end of the sampling capacitor is respectively coupled with one end of the first switch and one end of the second switch, and the other end of the sampling capacitor is coupled with the grounding end.

6. The digital-to-analog conversion circuit of claim 4, wherein said sampling clock generation circuit comprises: a delay module, a second counter, a second exclusive-OR gate, a plurality of third exclusive-OR gates, a NOR gate, a third trigger and a non-overlapping clock generating circuit,

the input end of the delay module is coupled with the clock signal, and the output end of the delay module is coupled with one input end of the second exclusive-OR gate;

the other input end of the second exclusive-or gate is coupled with the clock signal, and the output end of the second exclusive-or gate is coupled with the input end of the second counter;

the reset end of the second counter is coupled with a reset signal, the reset signal is a signal obtained by delaying an output signal of the reset end of the first counter by one period of the clock signal, each output end of the second counter is coupled with one input end of a third exclusive-OR gate, and the number of bits of the second counter is 1 greater than that of the input digital code value;

the other input end of one of the plurality of third exclusive-OR gates is coupled with the ground end, and the other input end of each of the other third exclusive-OR gates is coupled with one bit signal of the input digital code value; the output end of each third exclusive-OR gate is coupled with one input end of the NOR gate;

the output end of the NOR gate is coupled with the clock end of the third trigger, the input end of the third trigger is respectively coupled with the second output end of the third trigger and the input end of the non-overlapping clock generating circuit, and the reset end of the third trigger is coupled with the power supply voltage;

the output end of the non-overlapping clock generation circuit outputs the sampling clock signal.

7. The digital-to-analog conversion circuit of claim 5, wherein the sampling clock signal comprises a first sampling clock signal and a second sampling clock signal;

wherein the first sampling clock signal controls the first switch and the second sampling clock signal controls the second switch.

8. The digital-to-analog conversion circuit of any one of claims 1-7, wherein the clock signal has a frequency of 2 of a preset conversion frequency of the digital-to-analog conversion circuit ^N And (2) multiplying, wherein N is the number of bits of the input digital code value.

9. A chip comprising a digital-to-analog conversion circuit of a PWM converted analog output according to any one of claims 1-8.

10. An electronic device comprising a chip according to claim 9.