DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. Identical components will be referred to using the same reference numerals. Similar components will be quoted using similar reference numerals. The analog-digital converter according to the present invention to be described below, and the operations performed by the present invention are just described, for example, and various changes and modifications can be made without departing from the spirit of the present invention.
1 is a block diagram illustrating a sensor device according to an exemplary embodiment of the present invention. Referring to FIG. 1, the sensor device 100 includes a sensor unit 110 and a high resolution ADC 120.
The sensor unit 110 detects a change in resistance (R) or capacity (C) which varies according to a change in temperature, humidity, or amount of light and converts it into an electrical signal. The sensor unit 110 may be a current mode ramp integrator that outputs the converted electrical signal in a pulse width. In particular, the sensor unit 110 senses the magnitude of the capacitance (C) voltage that is periodically charged-discharged and includes the sensing information in the pulse width and outputs the sensing information as the first sensing signal SP1. In this case, a switching time for charge-discharge of the capacitor C may be inevitably included in the first sensing signal SP1.
It will be understood that the configuration or function of the sensor unit 110 is not limited thereto. That is, the sensor unit 110 may include any sensors that sense various physical and chemical changes and provide the sensed information in a pulse width.
The high resolution ADC 120 may amplify the first sensing signal SP1 and remove an amplification portion of the switching time that is inevitably included in the structure of the sensor unit 110 from the amplified first sensing signal SP1. Accordingly, the high resolution ADC 120 of the present invention may remove a signal component corresponding to a switching time acting as a noise from the first sensing signal SP1 amplified at high resolution. Therefore, the high resolution ADC 120 is capable of high accuracy and high resolution signal conversion. In order to have such a function, the high resolution ADC 120 may include a pulse divider 121, a clock divider 123, and a pulse subtractor 125.
The pulse divider 121 divides the first sensing signal SP1 which is a pulse signal by 2 n times. Here, divide means to divide the frequency of the pulse signal. Thus, that 2 n times the frequency divider (Divide) pulse means that the period of the pulse 2 n times increase. Increasing the period of the pulse has the meaning of amplify (Amplify) that eventually increases the pulse width of the pulse signal. Therefore, the subsequent division of the pulse should be understood as meaning amplifying the pulse signal.
The pulse divider 121 amplifies the pulse period of the first sensing signal SP1 by 2 n times with reference to the clock signal to generate a pulse division signal SP2 n . For the width of the pulse to the example, the first sensing when the pulse cycle signal (SP1) of (T P1 + T SW), a pulse frequency divider 121 amplifies the pulse width of 2 n (T P1 + T SW) Amplify. Here, the charging time T P1 refers to a time when the capacity C of the sensor unit 110 is charged. Therefore, the charging time T P1 includes sensing information sensed by the sensor unit 110. In addition, the switching time T SW denotes a time for discharging the capacitance C of the sensor unit 110.
A clock divider (123) amplifies the frequency of 2-1 times the pulse frequency divider 121, the clock signal (CLK). The pulse signal amplified by the pulse divider 121 includes a pulse component corresponding to the switching time T SW of the sensor unit 110. The component corresponding to the switching time T SW may also be amplified by the pulse divider 121. The period of the switching time T SW is eventually determined according to the clock signal CLK. The amplified switching time 2 n (T SW ) is equal to the pulse width of the signal obtained by amplifying the clock signal CLK by 2 n-1 times. This relationship will be described in detail through the timing chart described below.
The pulse subtractor 125 obtains a switching time corresponding to 2 n (T SW ) from the pulse division signal SP2 n amplified by the clock divider 121 to 2 n (T P1 + T SW ). Remove That is, the pulse subtractor 125 will remove the clock signal component not including the sensing information from the amplified pulse division signal SP2 n . As a result, the pulse subtractor 125 may remove the switching time component and output the second sensing signal SP_OUT including only the pure sensing component.
Configurations and functions described above have been shown in a simplified manner to describe the technical features of the present invention. Although the clock signal CLK provided to the high resolution ADC 120 and the switching signal provided to the sensor unit 110 are not illustrated, the operation of these signals will be described in detail in the following embodiments.
2 is a block diagram illustrating the sensor device of FIG. 1 according to a first embodiment of the present invention in more detail. Referring to FIG. 2, the sensor device 200 includes a sensor unit 210 and a high resolution ADC 220.
The sensor unit 210 may include a current source 212, a sensing capacitor 214, a switch 216, and a comparator 218. The current source 212 can provide a constant level of charging current Is to charge the sensing capacitor 214. The sensing capacitor 214 may be charged by the charging current Is. In addition, the sensing capacitor 214 may be discharged by the switch 216. The sensing capacitor 214 will be provided with a variable capacitance. That is, the sensing capacitor 214 may be provided in a structure in which the size of the capacitor varies according to physical and chemical changes.
The switch 216 discharges the sensing capacitor 214 in response to the switch control signal SWCNTL. That is, a change in the pattern of the capacitor voltage Vc according to the charging of the sensing capacitor 214 is output as a sensing result. The switch 216 discharges the periodic sensing capacitor 214 to initialize the capacitor voltage Vc. will be. The comparator 218 periodically compares the capacitor voltage Vc and the reference voltage Vref output by charging and discharging. The capacitor voltage Vc may be provided to the negative input terminal (−) of the comparator 218 and the reference voltage Vref may be provided to the positive input terminal (+) of the comparator 128. The comparator 218 outputs the comparison result as the first sensing signal SP1.
By the above-described configuration and function, the sensor unit 210 may be configured in the form of a current mode ramp integrator. That is, the sensing capacitor 214 is charged by the current Is of a predetermined magnitude and is discharged by the switch 216. In addition, the rising and discharging patterns of the capacitor voltage Vc change according to the capacitance change of the sensing capacitor 214, and the sensing result will be output as the pulse width of the first sensing signal SP1.
The high resolution ADC 220 generates a switch control signal SWCNTL for controlling the sensor unit 210 using the start signal Start and the clock signal CLK. The high resolution ADC 220 amplifies the first sensing signal SP1 output as a result of sensing by the sensor unit 210. The high resolution ADC 220 removes the pulse portion corresponding to the switching section generated by the switch 216 from the amplified pulse signal. For this operation, the high resolution ADC 220 includes a pulse divider 221, a first NAND gate 222, a clock divider 223, an inverter 224, an RS flip-flop 225, a counter 226, D The flip-flop 227 may include a second NAND gate 228.
The pulse divider 221 divides the first sensing signal SP1 to have a period having a target resolution (for example, 2 n times). That is, the pulse width of the first sensing signal SP1 is amplified by 2 n times by the pulse divider 221. That is, the pulse divider 221 outputs the pulse division signal SP2 n in which the period of the first sensing signal SP1 is increased by 2 n times. The first sensing signal SP1 includes both a sensing signal component sensed by the sensor unit 210 and a switching signal component for driving the sensor unit 210. As a result, when the first sensing signal SP1 is amplified by the pulse divider 221, both the sensing signal component and the switching signal component will be amplified.
The first NAND gate 222 performs an AND operation on the pulse division signal SP2 n and the clock signal CLK provided from the pulse divider 221. The first NAND gate 222 may transfer the first clock pulse CP1 provided as a result of the operation to the clock divider 223. The first clock pulse CP1, which is an output of the first NAND gate 222, includes a clock signal CLK included in a high period of the pulse division signal SP2 n . The clock signal CLK corresponding to the low period of the pulse division signal SP2 n is removed from the first clock pulse CP1, which is an output signal of the first NAND gate 222.
The clock divider 223 amplifies 2 n-1 times the first clock pulse CP1 provided from the first NAND gate 222. That is, the pulse width of the first clock pulse CP1, which is the output signal of the first NAND gate 222, is increased by 2 n-1 times by the clock divider 223. The clock signal is amplified by 2 n-1 times by the clock divider 223. As a result, the clock divider 223 will output the clock divider signal CP2 n-1 amplified by the clock signal CLK. The inverter 224 inverts the pulse division signal SP2 n provided from the pulse divider 221.
The RS flip-flop 225 receives the inverted pulse division signal SP2 n to the reset input terminal R and the clock division signal CP2 n-1 to the set input terminal S. The RS flip-flop 225 determines the current output state Q (t) according to the state of the reset input terminal R, the state of the set input terminal S, and the previous output state Q (t-1). The switching time 2 n T SW included in the pulse division signal SP2 n may be removed by the RS flip-flop 225. This is because the switching time 2 n T SW included in the pulse division signal SP2 n corresponds to a half period of the clock division signal CP2 n-1 . The first division signal of the second sensing signal (SP_OUT) Effect of removal of (CP2 n) switching times (T 2, SW n) is outputted by the RS flip-flop 225. Here, the RS flip-flop 225 may have any configuration for removing the pulse width corresponding to the half period of the clock division signal CP2 n-1 from the pulse division signal SP2 n . For example, it will be appreciated by those skilled in the art that the RS flip-flop 225 may be comprised of an RS latch that is composed of a combination circuit that is not synchronized to the clock.
The counter 226 may count the pulse length of the pulse width amplified second sensing signal SP_OUT including only the pure sensing component and output the binary data to the binary data column. The pulse count operation of the counter 226 is performed based on the clock signal CLK which is basically provided.
The D flip-flop 227 inverts the first sensing signal SP1 in synchronization with the clock signal CLK. The inverted first sensing signal SP1 is input to the second NAND gate 228 together with the start signal Start. As a result, the switch 216 of the sensor unit 210 may be controlled by the first sensing signal SP1 that is inverted and fed back. However, since the first sensing signal SP1 includes a switching time, the influence of the switching time will not disappear even after the feedback.
In the above description, the sensor device 200 of the present invention amplifies the first sensing signal SP1 output from the sensor unit 210, removes unnecessary switching components included in the amplified pulse signal, and thus, the second sensing signal SP_OUT. Will output When the second sensing signal SP_OUT is counted, only pure sensing components of the first sensing signal SP1 may be generated as digital data.
3 is a timing diagram illustrating an operation of the sensor device 200 of FIG. 2. Referring to FIG. 3, the high resolution ADC 220 amplifies the first sensing signal SP1 output from the sensor unit 210 and removes unnecessary switching components included in the amplified first sensing signal SP1. 2 It is output as the sensing signal SP_OUT. When the second sensing signal SP_OUT is counted, only the sensing component of the first sensing signal SP1 may be output as purely digital data.
First, the sensing capacitor 214 will be charged and discharged periodically by the source current Is in the sensor unit 210. At the time T0, the start signal Start is activated. The sensing capacitor 214 is charged in a period T0 to T1 where the switch control signal SWCNTL is output at a low level. Thus, the capacitor voltage Vc will rise at the set slope. In this period T0 to T1, since the capacitor voltage Vc is lower than the reference voltage Vref, the level of the first sensing signal SP1, which is the output of the comparator 218, will remain logic high. On the other hand, at the time T1, the level of the capacitor voltage Vc reaches the reference voltage Vref. Then, the comparator 218 will output the first sensing signal SP1 having a logic low level. The logic low period of the first sensing signal SP1 corresponds to one period of the clock signal. That is, since the inverted signal of the first sensing signal SP1 is provided as the switch control signal SWCNTL, the switch 216 is turned on in the period T1 to T2, and the sensing capacitor 214 will be discharged. When one cycle of the clock signal elapses, that is, at the time T2, the switch control signal SWCNTL falls back to the low level Low. Then, charging of the sensing capacitor 214 will begin. The operation of the sensor unit 210 will repeat the charge-discharge periodically by the switch control signal SWCNTL. In addition, if the capacitance of the sensing capacitor 214 is changed by the change in the physical and chemical environment, this period is affected, and this effect will be reflected in the pulse width of the first sensing signal SP1.
The high resolution ADC 220 amplifies the first sensing signal SP1. That is, the pulse divider 221 extends the period of the first sensing signal SP1 to the target multiple 2n using a plurality of flip-flops. The first sensing signal SP1 includes both the sensing time T P1 corresponding to the charging period of the sensing capacitor 214 and the switching time T SW irrespective of the sensing time. Therefore, when the pulse width is amplified by the pulse divider 221, both the sensing time T P1 and the switching time T SW will be amplified. By the pulse divider 221, the first sensing signal SP1 is converted into a pulse divided signal SP2 n whose period is amplified by the target multiple 2 n .
When the pulse division signal SP2 n is generated using a plurality of flip-flops, two times (SP2 1 ) division, four times (SP2 2 ) division, for each stage with respect to the input first sensing signal SP1, 8 times (SP2 3 ) dispensing,. In this case, the process will be 2 n times (SP2 n ) dispensed. In this case, in addition to the amplification of the sensing time T P1 at each stage, the switching time T SW will be amplified at the same ratio.
This amplification of the pulse width is similarly performed by the clock divider 223. However, the clock divider 223 amplifies the clock signal CLK by 2 n-1 times in the section corresponding to the high level of the pulse division signal SP2 n . The clock divided signal CP2 n-1 amplified by the clock divider 223 is output in the high period of the pulse divided signal SP2 n in the form shown. Here, it is assumed that n representing the divided multiple is 10.
The inverted pulse division signal / SP2 n is transmitted to the reset input terminal R of the RS flip-flop 225 for generating the second sensing signal SP_OUT. The clock divide signal CP2 n-1 may be provided to the set input terminal S of the RS flip-flop 225.
Referring to the time point T3, before the time point T3, the state of the reset input terminal R may maintain a logic '1', the set input terminal S may have a logic '0', and the output terminal Q may have a logic '0'. However, at time T3, as the inverted pulse division signal / SP2 n transitions to logic '0' and the clock division signal CP2 n-1 maintains logic '0', the output stage Q is set to logic '. Keep 0 '. Therefore, the second sensing signal SP_OUT will maintain a logic '0'.
At the time T4, the state of the reset input terminal R of the RS flip-flop 225 remains logic '0', and the set input terminal S transitions to logic '1'. Thus, at time T4, output stage Q transitions to logic '1'. Therefore, the second sensing signal SP_OUT will transition to logic '1'.
At the time T5, the state of the reset input terminal R of the RS flip-flop 225 remains logic '0', and the set input terminal S transitions to logic '0'. Thus, at time T5, output stage Q maintains a logic '1'. Thus, the second sensing signal SP_OUT will remain at logic '1'. The state of logic '1' of the second sensing signal SP_OUT is maintained until the time point T8 when the reset input terminal R transitions to logic '1'.
As a result, the switching time included in the pulse division signal (SP2 n) by 225 of the RS flip-flop has been described that the same may be eliminated. The component of the switching section T SW 2 n-1 pulse width amplified by the clock division signal CP2 n-1 is removed from the pulse division signal SP2 n .
4 is a block diagram illustrating a sensor device 300 according to a second embodiment of the present invention. Referring to FIG. 5, the sensor device 300 may include a memory unit 330 including a sensor unit 310, a microcontroller unit (MCU) 320, and an ADC algorithm 335.
The sensor unit 310 is substantially the same as the sensor unit 210 shown in FIG. 2. That is, the sensor capacitor 314 is charged by a certain amount of charging current I S provided from the current source 312. The electric charge charged in the sensor capacitor 314 will be periodically discharged by the switch 316 controlled by the switch control signal SWCNTL. The capacitor voltage Vc formed by the periodic charging and discharging of the sensor capacitor 314 may be compared with the reference voltage Vref by the comparator 318 and output as a first sensing signal SP1, which is a signal in the form of a pulse. . The first sensing signal SP1 in the form of a pulse is provided to the MCU 320.
The MCU 320 converts the first sensing signal SP1 provided from the sensor unit 310 into digital data. The MCU 320 may generate a switch control signal SWCNTL for controlling charging and discharging of the sensor unit 320 with reference to the cycle of the clock signal CLK. The MCU 320 performs the function of the high resolution ADC 220 described in FIG. 2. That is, the MCU 320 amplifies the pulse width of the first sensing signal SP1 by the target multiple 2 n to generate the pulse division signal SP2 n . The MCU 320 amplifies the pulse width of the clock signal CLK by 2 n-1 times to generate the clock division signal CP2 n-1 . The MCU 320 may remove the switching component by removing the clock division signal CP2 n-1 from the pulse division signal SP2 n .
That is, the MCU 320 may drive an algorithm corresponding to various components of the high resolution ADC 220 described with reference to FIG. 2. Such an algorithm may be provided through an embedded memory provided in the MCU 320. Alternatively, the ADC algorithm 335 for performing the function of the high resolution ADC 220 described in FIG. 2 may be provided from the memory 330 connected to the outside of the MCU 320.
5 is a block diagram illustrating a sensor device 400 according to a third embodiment. Referring to FIG. 5, the sensor device 400 includes a sensor unit 410 including a variable resistor and a high resolution ADC 420.
The sensor unit 410 may include current sources 412 and 413, a charging capacitor 414, a switch 416, a comparator 418, and a resistance sensor Rvar. The first current source 412 is provided for charging the charging capacitor 414. The second current source 413 provides a constant magnitude of current I S2 flowing through the variable resistor Rvar. Therefore, when the size of the variable resistor Rvar changes by physical and chemical sensing, the reference voltage Vref changes as the size of the current I S2 is kept constant. The change in the reference voltage Vref is eventually sensed. Here, the magnitudes of the currents I S1 and I S2 provided by each of the current sources 412 and 413 may be provided in the same manner. However, it will be appreciated that the magnitudes of the currents I S1 , I S2 may have other values as necessary.
The charging capacitor 414 provides a fixed amount of capacitance, unlike the sensing capacitor 214 of FIG. 2. The charging capacitor 414 may be charged by the first current source I S1 . And the charges charged in the charging capacitor 414 will be discharged by the switch 416. The length of the charging time may be set according to the capacity of the charging capacitor 414.
The switch 416 discharges the charging capacitor 414 in response to the switch control signal SWCNTL. That is, the capacitor voltage Vc according to the charging of the charging capacitor 414 is generated, and the switch 416 periodically discharges the charging capacitor 414 to initialize the capacitor voltage Vc. The comparator 418 compares the capacitor voltage Vc and the reference voltage Vref outputted by the charge-discharge periodically of the charging capacitor 414. The capacitor voltage Vc may be provided to the negative input terminal (-) of the comparator 418, and the reference voltage Vref may be provided to the positive input terminal (+) of the comparator 418. The comparator 418 outputs the comparison result as the first sensing signal SP1.
By the configuration and function described above, the sensor unit 410 may be configured in the form of a current mode ramp integrator. That is, the charging capacitor 414 is charged by the current I S1 having a predetermined magnitude, and is discharged by the switch 416. The rising and discharging patterns of the capacitor voltage Vc change according to the change of the reference voltage Vref caused by the change of the magnitude of the variable resistor Rvar. The sensing result will be output as the pulse width of the first sensing signal SP1.
The high resolution ADC 420 may be provided substantially the same as the high resolution ADC 220 of FIG. 2. The high resolution ADC 420 generates a switch control signal SWCNTL for controlling the sensor unit 410 using the start signal Start and the clock signal CLK. The high resolution ADC 420 amplifies the first sensing signal SP1 output as the sensing result of the sensor unit 410. The high resolution ADC 420 removes the pulse portion corresponding to the switching period generated by the switch 416 from the amplified pulse signal. For this operation, the high resolution ADC 420 may include a pulse divider 421, a first NAND gate 422, a clock divider 423, an inverter 424, an RS flip-flop 425, a counter 426, and a D. A flip flop 427 and a second NAND gate 428 may be included.
The pulse divider 421 divides the first sensing signal SP1 to have a pulse width of a target resolution (for example, 2 n times). The pulse divider 421 will increase the pulse width of the first sensing signal SP1 by 2 n times. That is, the first sensing signal SP1 is amplified by 2 n times by the pulse divider 421 and is output as the pulse division signal SP2 n . The first sensing signal SP1 includes both a sensing signal component sensed by the sensor unit 410 and a switching component for driving the sensor unit 410. As a result, when the pulse width is amplified by the pulse divider 421, both the sensing signal component and the switching component will be amplified.
The first NAND gate 422 performs an AND operation on the pulse division signal SP2 n and the clock signal CLK provided from the pulse divider 421. In addition, the first NAND gate 422 may transfer the first clock pulse CP1 provided as a result of the operation to the clock divider 423. The first clock pulse CP1, which is an output of the first NAND gate 422, includes a clock signal CLK included in the high period of the pulse division signal SP2 n . The clock signal CLK corresponding to the low section of the pulse division signal SP2 n is removed from the first clock pulse CP1, which is an output of the first NAND gate 422.
The clock divider 423 divides the first clock pulse CP1 provided from the first NAND gate 422 by 2 n-1 times. That is, the pulse width of the first clock pulse CP1, which is the output signal of the first NAND gate 422, is increased by 2 n-1 times by the clock divider 423. The clock divider 423 amplifies the clock signal by 2 n-1 times. As a result, the clock divider 423 may output the clock divider signal CP2 n- 1 obtained by amplifying the clock signal CLK. The inverter 424 inverts the pulse division signal SP2 n provided from the pulse divider 421.
The RS flip-flop 425 receives the inverted pulse division signal SP2 n to the reset input terminal R and the clock division signal CP2 n -1 to the set input terminal S. The RS flip-flop 425 determines the current output state Q (t) according to the state of the reset input terminal R, the state of the set input terminal S, and the previous output state Q (t-1). The switching time 2 n T SW included in the pulse division signal SP2 n may be removed by the RS flip-flop 425. This is because the switching time 2 n T SW included in the pulse division signal SP2 n corresponds to a half period of the clock division signal CP2 n -1 . The second sensing signal SP_OUT is removed from the influence of the switching time 2 n T SW from the first divided signal CP2 n amplified by the RS flip-flop 425. Here, the RS flip-flop 425 may be provided in any configuration for removing the pulse width corresponding to the half period of the clock division signal CP2 n -1 from the pulse division signal SP2 n . For example, the RS flip-flop 425 may be composed of an RS latch composed of a combination circuit that is not synchronized to the clock.
The counter 426 may count the pulse length of the second sensing signal SP_OUT including only pure sensing components and output the counted binary data. The pulse count operation of the counter 426 is performed based on the clock signal CLK which is basically provided.
The D flip-flop 427 inverts the first sensing signal SP1 in synchronization with the clock signal CLK. The inverted first sensing signal SP1 is input to the second NAND gate 428 together with the start signal Start. As a result, the switch 416 of the sensor unit 410 will be controlled by the first sensing signal SP1 that is inverted and fed back. However, since the first sensing signal SP1 includes a switching time, the influence of the switching time will not disappear even after the feedback.
The sensor device 400 according to the third embodiment of the present invention described above amplifies the first sensing signal SP1 output from the sensor unit 410 and removes unnecessary switching components included in the amplified pulse signal. The second signal is output as the second sensing signal SP_OUT. When the second sensing signal SP_OUT is counted, digital data in which only a sensing component is purely amplified may be generated. Herein, the sensor unit 410 has been described as including a resistance sensor whose magnitude of resistance changes as a result of sensing. However, it will be appreciated that the sensor unit 410 may be configured as any sensor in the form of a current mode ramp integrator that provides the sensed signal in the form of a pulse. In addition, the high resolution ADCs 220 and 420 of FIGS. 2 and 5 have a simple structure and are easy to lighten, shorten, and low in power, and are suitable to be implemented as semiconductor chips.
6 is a block diagram illustrating a sensor device 500 according to a fourth embodiment of the present invention. Referring to FIG. 6, the sensor device 500 may include a sensor 510, a MCU 520, and a memory 530 including an ADC algorithm 535. Here, it will be understood that the memory 530 having the ADC algorithm 535 may be an embedded memory included in the MCU 520.
The sensor unit 510 is substantially the same as the sensor unit 410 illustrated in FIG. 5. The sensor unit 510 may include current sources 512 and 513, a charging capacitor 514, a switch 516, a comparator 518, and a resistance sensor Rvar. The first current source 512 is provided for charging the charging capacitor 514. The second current source 513 provides a constant magnitude of current I S2 flowing through the variable resistor Rvar. Therefore, when the size of the variable resistor Rvar changes by physical and chemical sensing, the reference voltage Vref changes as the size of the current I S2 is kept constant. The change in the reference voltage Vref is eventually sensed. Here, the magnitudes of the currents I S1 and I S2 provided by each of the current sources 512 and 513 may be provided in the same manner. However, it will be appreciated that the magnitudes of the currents I S1 , I S2 may have other values as necessary.
The charging capacitor 514 provides a fixed amount of capacitance, unlike the sensing capacitor 314 of FIG. 4. The charging capacitor 514 may be charged by the first current source I S1 . And the charges charged in the charging capacitor 514 will be discharged by the switch 516. The length of the charging time may be set according to the capacity of the charging capacitor 514.
The switch 516 discharges the charging capacitor 514 in response to the switch control signal SWCNTL. That is, a capacitor voltage Vc is generated according to the charging of the charging capacitor 514, and the switch 516 periodically discharges the charging capacitor 514 to initialize the capacitor voltage Vc. The comparator 518 compares the capacitor voltage Vc and the reference voltage Vref outputted by the charge-discharge periodically of the charging capacitor 514. The capacitor voltage Vc may be provided to the negative input terminal (−) of the comparator 518 and the reference voltage Vref may be provided to the positive input terminal (+) of the comparator 518. The comparator 518 outputs the comparison result as the first sensing signal SP1.
By the above-described configuration and function, the sensor unit 510 may be configured in the form of a current mode ramp integrator. That is, the charging capacitor 514 is charged by the current I S1 having a predetermined magnitude, and is discharged by the switch 516. The rising and discharging patterns of the capacitor voltage Vc change according to the change of the reference voltage Vref caused by the change of the magnitude of the variable resistor Rvar. The sensing result will be output as a pulse of the first sensing signal SP1. The first sensing signal SP1 in the form of a pulse is provided to the MCU 520.
The MCU 520 converts the first sensing signal SP1 provided from the sensor unit 510 into digital data. The MCU 520 may generate a switch control signal SWCNTL for controlling charging and discharging of the sensor unit 520 with reference to the cycle of the clock signal CLK. The MCU 520 performs the functions of the high resolution ADCs 220 and 420 described with reference to FIGS. 2 and 5. That is, the MCU 520 amplifies the period of the first sensing signal SP1 by the target multiple 2n . The MCU 520 amplifies the period of the clock signal CLK by 2 n-1 times. The switching component added by the sensing operation of the sensor unit 510 may be removed using the amplified clock signal CP2 n −1 from the amplified sensing signal SP2 n .
That is, the MCU 520 may drive an algorithm corresponding to various components of the high resolution ADCs 220 and 420 of FIG. 2 or 5. Such an algorithm may be provided through an embedded memory provided in the MCU 520. Alternatively, the ADC algorithm 535 for performing the functions of the high resolution ADCs 220 and 420 described with reference to FIG. 2 or 5 may be performed through a memory 530 such as a flash memory or a ROM connected to the outside of the MCU 520. It may be provided.
In the above description, the sensor devices 300 and 500 illustrated in FIG. 4 or 6 may be configured in various ways through the MCUs 320 and 520. That is, the high resolution ADCs 220 and 420 in the chip form illustrated in FIGS. 2 and 5 may be implemented in a software program. Most practical ADCs are used in conjunction with the MCU. To develop high resolution ADCs, they may be developed into new chips that require a lot of time and cost. However, in this case, only analog parts such as the sensor units 310 and 510 may be manufactured as chips, and the functions of the high resolution ADCs 220 and 420 of the present invention may be executed by firmware or a logic program. In addition, the ADC algorithms 335 and 535 in the form of firmware to be downloaded to the MCUs 320 and 520 may be implemented by digital codes such as HDL (Verilog, VHDL, C language, etc.), and may be implemented using an FPGA.
The MCUs 320 and 520 may be variously changed or adjusted by the ADC algorithms 335 and 535 provided in firmware. In addition, the clock CLK used for the MCUs 320 and 520 may be supplied from inside or outside the chip of the MCUs 320 and 520. As a result, the present invention consists of only the sensor unit 310, 510 consisting of the current mode lamp integrator in hardware, the rest of the programmable chip (MCU, FPGA, etc.) using the programmable system to the ADC of the desired form Can be configured. ADC algorithm 335 or ADC algorithm 535 may be provided in the form of substantially one or more software modules combined.
FIG. 7 is a flowchart schematically illustrating a method of operating an ADC algorithm operating in the MCUs 320 and 520 of FIG. 4 or 6. Referring to FIG. 7, the amplified switching component may be removed from the pulse width amplified sensing signal by the ADC algorithm 535 driven by the MCU 520. Here, the advantages of the present invention will be described with reference to the MCU 520 of FIG. 6 for convenience of description.
In step S110, the MCU 520 activates a start signal Start to drive the sensor unit 510. Then, the switch control signal SWCNTL will be transmitted to the sensor unit 510. According to the activation period of the switch control signal SWCNTL, the charging capacitor 514 of the sensor unit 510 may be periodically charged and discharged. Then, the capacitor voltage Vc rises with a constant slope and drops to 0V when the switching 516 is turned on. This process will be controlled by the switch control signal SWCNTL. Then, the sensor unit 510 may output the first sensing signal SP1 in the form of a pulse output from the comparator 518.
In step S120, the MCU 520 amplifies the first sensing signal SP1 provided by the sensor unit 510 by 2 n times. That is, the MCU 520 generates the pulse division signal SP2 n amplified by the target amplification ratio 2 n of the period of the first sensing signal SP1.
In step S130, the MCU 520 generates a clock signal CLK corresponding to one pulse period of the pulse division signal SP2 n divided by 2 n times. In addition, the clock signal CLK in one pulse period of the pulse division signal SP2 n may be amplified by 2 n-1 times corresponding to half of the target amplification factor 2 n of the first sensing signal SP1.
In step S140, the MCU 520 removes the clock division signal CP n-1 amplified by 2 n-1 times from the pulse division signal SP2 n . That is, the MCU 520 may remove the switching pulse component included in the pulse signal SP2 n divided by 2 n times using the clock signal.
In step S150, the MCU 520 removes the switching pulse component included in the pulse division signal SP2 n and outputs the second sensing signal SP_OUT. When the pulse length of the second sensing signal SP_OUT is counted, the purely amplified sensing signal is converted into digital data.
In the above, the operation procedure of the ADC algorithm 535 driven by the MCU 520 of the present invention has been briefly described. In general, the output of the sensor unit 510 and the ADC circuit composed of an analog device is provided to the MCU 520 or various DSPs for additional signal processing. However, rather than configuring a separate ADC circuit, it is more flexible to embed the functionality of the ADC circuit in the MCU 520 in the form of firmware. In addition, high-resolution ADC functionality can be provided through software, while reducing the cost of additional semiconductor chips.
8 is a block diagram illustrating a sensor device 600 according to a fifth embodiment of the present invention. Referring to FIG. 8, the sensor device 600 includes a sensor unit 610 and a high resolution ADC 620.
The sensor unit 610 includes a current source 612, a sensing capacitor 614, a switch 616, and a buffer 618. The current source 612 may provide a constant level of charging current Is to charge the sensing capacitor 614. The sensing capacitor 614 may be charged by the charging current Is. In addition, the sensing capacitor 614 may be discharged by the switch 616. The sensing capacitor 614 will be provided with a variable capacitance. That is, the sensing capacitor 614 may be provided in a structure in which the size of the capacitor varies according to physical and chemical changes.
The switch 616 discharges the sensing capacitor 614 in response to the switch control signal SWCNTL. That is, a change in the pattern of the capacitor voltage Vc according to the charging of the sensing capacitor 614 is output as a sensing result. The switch 616 discharges the periodic sensing capacitor 614 to initialize the capacitor voltage Vc. will be.
The buffer 618 may output the short input signal as a pulse signal without using the reference voltage Vref. The buffer 618 outputs the first sensing signal SP1 according to the level of the capacitor voltage Vc. For example, the buffer 618 may output the first sensing signal SP1 to a level of logic '0' when the level of the capacitor voltage Vc is lower than the lower limit threshold. On the other hand, if the level of the capacitor voltage (Vc) is higher than the upper limit threshold, the buffer 618 will output the first sensing signal (SP1) at a level of logic '1'. When using the buffer 618, the complexity of the circuit configuration resulting from using the reference voltage Vref can be eliminated.
By the configuration and function described above, the sensor unit 610 may be configured in the form of a current mode ramp integrator. That is, the sensing capacitor 614 is charged by the current Is of a predetermined magnitude and is discharged by the switch 616. In addition, the rising and discharging patterns of the capacitor voltage Vc change according to the capacitance change of the sensing capacitor 614, and the sensing result may be output as the pulse width of the first sensing signal SP1.
The high resolution ADC 620 generates a switch control signal SWCNTL for controlling the sensor unit 610 using the start signal Start and the clock signal CLK. The high resolution ADC 620 amplifies the pulse width of the first sensing signal SP1 output as the sensing result of the sensor unit 610. The high resolution ADC 620 removes the pulse portion corresponding to the switching section generated by the switch 616 from the amplified pulse signal. For this operation, the high resolution ADC 620 may include a pulse divider 621, a first NAND gate 622, a clock divider 623, an inverter 624, an RS flip-flop 625, a counter 626, and a D. And a flip-flop 627 and a second NAND gate 628. The high resolution ADC 620 may be configured substantially the same as the high resolution ADC 220 described with reference to FIG. 2. Therefore, a detailed description of the high resolution ADC 620 will be omitted.
In the above description, the sensor device 600 of the present invention amplifies the first sensing signal SP1 output from the sensor unit 610, and removes unnecessary switching components included in the amplified signal as the second sensing signal SP_OUT. Output When the second sensing signal SP_OUT is counted, only the sensing component of the first sensing signal SP1 may be amplified and output as digital data. In addition, since the comparator configuring the sensor unit 610 is provided as a simple buffer 618, it is not necessary to use the reference voltage Vref, so that light and small and low power sensing operations are possible.
9 is a block diagram illustrating a sensor device 700 according to a sixth embodiment of the present invention. Referring to FIG. 9, the sensor device 700 includes a sensor unit 710 and an MCU 720 that performs a function of a high resolution ADC.
The sensor unit 710 includes a current source 712, a sensing capacitor 714, a switch 716, and a buffer 718. The current source 712 can provide a constant level of charging current Is to charge the sensing capacitor 714. The sensing capacitor 714 may be charged by the charging current Is. In addition, the sensing capacitor 714 may be discharged by the switch 716. The sensing capacitor 714 will be provided with a variable capacitance. That is, the sensing capacitor 714 may be provided in a structure in which the size of the capacitor varies according to physical and chemical changes. The configuration of the sensor unit 710 may be provided substantially the same as the sensor unit 610 of FIG. 8. Therefore, a detailed description of the sensor unit 710 will be omitted.
The MCU 720 converts the first sensing signal SP1 provided from the sensor unit 710 into digital data. The MCU 720 may generate a switch control signal SWCNTL for controlling charging and discharging of the sensor unit 720 with reference to the cycle of the clock signal CLK. The MCU 720 may perform the function of the high resolution ADC 620 described with reference to FIG. 8. That is, the MCU 720 amplifies the period of the first sensing signal SP1 by the target multiple 2n . The MCU 720 amplifies the period of the clock signal CLK by 2 n-1 times. The amplified clock division signal CP2 n-1 may be removed from the amplified pulse division signal SP2 n to remove the switching component introduced from the sensor unit 710.
The MCU 720 may drive an ADC algorithm 735 corresponding to various components of the high resolution ADC 620 of FIG. 8. Such an algorithm may be provided to the MCU 720 after being stored in an embedded memory provided in the MCU 720. Alternatively, the ADC algorithm 735 may be provided through the nonvolatile memory 730 connected to the outside of the MCU 720.
In the above description, the sensor device 700 of the present invention may include a MCU 720 which performs a function of a high resolution ADC through a software driven with the sensor unit 710 that does not use the reference voltage Vref. When the high resolution ADC's functions are configured with software such as firmware, the amplification factor and various functions can be easily updated at low cost. In addition, the current mode lamp integrator can be configured even though the configuration of the sensor unit 710 is very simple.
10A, 10B, 10C, 10D, and 10E are circuit diagrams showing the shape of the buffer of FIG. 8 or 9. Referring to FIG. 10A, a Schmitter trigger type buffer 718a is shown. The Schmitt trigger type buffer 718a is a buffer having hysteresis characteristics for the input signal Vc. The buffer 718a of the schmitter trigger type determines the logic of the first sensing signal SP1 based on two threshold voltages VIH & VIL with respect to one input voltage Vc. For example, in the rising period of the input voltage Vc, when the level of the input voltage Vc is higher than the upper limit threshold voltage VIH, the first sensing signal SP1 transitions to logic '1'. On the other hand, in the falling section of the input voltage Vc, the first sensing signal SP1 transitions to logic '0' only when the level of the input voltage Vc is lower than the lower threshold threshold voltage VIL. Therefore, the output voltage SP1 of the Schmitt trigger type buffer 718a does not show noise with respect to the input voltage Vc existing between the two threshold voltages VIH and VIL due to hysteresis characteristics.
Referring to FIG. 10B, a buffer 718b in which two inverters are connected in series is shown. The buffer 718b may provide the first sensing signal SP1 with no hysteresis characteristic with respect to the input voltage Vc. 10C shows various logic gates for providing a buffer function. The buffer 718c is a method of generating the first sensing signal SP1 by applying the input voltage Vc to the input terminal of the NAND gate in common, and the buffer 718d is input to the input terminal of the NOR gate NOR. The first sensing signal SP1 is generated by applying the voltage Vc in common. 10d shows a buffer circuit using an operational amplifier (OPAMP).
10A to 10D, the simplified buffer of the one input one output method may be used as an output terminal of the sensor unit 710. Thus, the use of a configuration (eg, a bandgap reference voltage generator) for providing the sensor unit 710 with a reference voltage Vref may be excluded.
11A-11C are block diagrams illustrating sensor devices having a plurality of channels. FIG. 11A shows an example in which a high resolution ADC is composed of hardware such as a semiconductor chip, and FIG. 11B illustrates an example in which the high resolution ADC is embedded as hardware in the MCU. 11C shows an example in which a high resolution ADC is implemented in software running on an MCU.
Referring to FIG. 11A, FIG. 11A illustrates a high-resolution ADC 810 for selecting a plurality of sensing signals to perform pulse width amplification, removing switching components from the amplified signal, converting the converted digital data, and providing the converted data to the MCU 820. Shows. The high resolution ADC 810 may be provided as a separate device from the MCU 820. Therefore, a separate input / output circuit 816 for interfacing with the MCU 820 should be included.
The plurality of channels CH1, CH2, CH3, and CH4 respectively correspond to different kinds of sensing signals. For example, the channel CH1 is provided with a pulse signal sensing temperature, the channel CH2 is provided with a pulse signal sensing humidity, and the channel CH3 is a pulse signal measuring acceleration, and the channel CH4. ) May be provided with a pulse signal sensing various physical and chemical conditions. The control logic 818 then turns on only one of the plurality of switches S1, S2, S3, S4 to provide the ADC 812 with the channel signal of any of these channels as an input signal Vin. You can. Then, the ADC 812 will amplify the selected sensing signal, remove the switching component from the amplified signal, and output the output signal SP_OUT of the pulse waveform. Subsequently, when the counter 814 counts the pulse length and outputs the data as data, the input / output circuit 816 may transfer the data to the MCU 820 according to a specific protocol. The input / output circuit 816 may use an interface of a protocol such as an inter-intergrated circuit (I 2 C) and a serial-peripheral interface (SPI).
Referring to FIG. 11B, FIG. 11B illustrates an MCU 900b for selecting a plurality of sensing signals to perform pulse width amplification, removing switching components from the amplified signal, and converting the converted signal into digital data. Here, it is shown that the high resolution ADC 910 is implemented in hardware but may be included in the MCU 900a. In this case, a separate interface for transmitting the sensing result converted into digital data to the MCU 900a may be removed. The MCU 900a includes a high resolution ADC 910 and a counter 920 for converting the sensing signal SP_OUT into sensing data, and control logic 930 for controlling the operation and selecting a channel thereof. will be.
Referring to FIG. 11C, the functionality of the high resolution ADC 910 of FIG. 11B is provided in software such as the ADC algorithm 925 executed in the MCU 900b. The MCU 900b may select any one channel by controlling the switches S1, S2, S3, and S4 capable of selecting a sensing signal of a plurality of channels. The signal of the selected channel is transmitted to the processor 940b as an input signal Vin. Processor 940b will execute ADC algorithm 925 loaded from memory 920 to amplify at high resolution and remove switching time from the amplified signal. The memory 920 may be an embedded memory embedded in the MCU 900b or may be provided as a memory provided outside the MCU 900b.
In the above, the functions of the sensor devices for selecting and processing any one of the sensing signals of the plurality of channels have been described. Here, the sensor device may be embedded in the MCU, or may be configured as a separate chip from the MCU. In addition, high-resolution ADC functionality may be provided in software such as firmware running on the MCU.
12A and 12B are block diagrams illustrating a differential sensor device 1000 according to an exemplary embodiment of the present invention. The sensor device may be implemented in a differential manner in which sensing is performed through two sensor units 1100 and 1200, and subtraction is performed after converting signals provided from the respective sensor units 1100 and 1200 into digital data. . Differential sensors allow easy removal of common input noise components. 12A shows the first half 1000a of the differential sensor device 1000 and FIG. 12B shows the second half of the differential sensor device 1000. Accordingly, it will be understood by those skilled in the art that the differential sensor device 1000 shown in FIGS. 12A and 12B is one configuration, not a separate configuration.
The first sensor unit 1100 may include a first current source 1102, a first sensing capacitor 1104, a first switch 1106, and a first comparator 1108. The first current source 1102 may provide a first level of the first charging current I s1 to charge the first sensing capacitor 1104. The first sensing capacitor 1104 may be charged by the first charging current I s1 . The first sensing capacitor 1104 may be discharged by the first switch 1106. The first sensing capacitor 1104 will be provided with a variable capacitance. That is, the first sensing capacitor 1104 may be provided in a structure in which the size of the capacitor varies according to physical and chemical changes.
The first switch 1106 discharges the first sensing capacitor 1104 in response to the switch control signal SWCNTL1. That is, a change in the pattern of the capacitor voltage Vc according to the charging of the first sensing capacitor 1104 is output as a sensing result. The first switch 1106 discharges the periodic sensing capacitor 1104 to discharge the capacitor voltage Vc. Will be initialized. The first comparator 1108 periodically compares the first capacitor voltage Vc1 and the reference voltage Vref output by charging and discharging. The capacitor voltage Vc may be provided to the negative input terminal (−) of the first comparator 1108 and the reference voltage Vref may be provided to the positive input terminal (+). The first comparator 1108 outputs the comparison result as the sensing signal SPA1.
The second sensor unit 1200 may be configured in the same manner as the first sensor unit 1100. The second sensor unit 1200 may include a second current source 1202, a second sensing capacitor 1204, a second switch 1206, and a second comparator 1208. The second current source 1202 can provide a second charging current Is s2 to charge the second sensing capacitor 1204. Here, the first sensing capacitor 1204, a second charging current (I s2), the reference voltage (Vref) will be also be configured to be substantially the same as those of the first sensor unit 1100.
The second switch 1206 discharges the second sensing capacitor 1204 in response to the switch control signal SWCNTL2. That is, a change in the pattern of the capacitor voltage Vc2 according to the charging of the second sensing capacitor 1204 is output as a sensing result. The second switch 1206 periodically discharges the second sensing capacitor 1204 to discharge the capacitor voltage. Will initialize (Vc2). The second comparator 1208 periodically compares the second capacitor voltage Vc2 and the reference voltage Vref output by charging and discharging. The second capacitor voltage Vc2 may be provided to the negative input terminal (−) of the second comparator 1208 and the reference voltage Vref may be provided to the positive input terminal (+). The second comparator 1208 outputs the comparison result as the sensing signal SPB1.
The high resolution ADC function of the sensing signals SPA1 and SPB1 provided from the first sensor unit 1100 and the second sensor unit 1200 may be substantially the same as that of the high resolution ADC 220 of FIG. 2. Can be. That is, in order to amplify the sensing signal SPA1 and remove the switching time from the amplified signal, the pulse divider 1110, the NAND gate 1115, the clock divider 1120, the inverter 1125, and RS flip-flop 1130 may be used. The amplified sensing signal SPA_OUT whose switching time is removed by the RS flip-flop 1130 will be output.
In order to amplify the sensing signal SPB1 and remove the switching time from the amplified signal, the pulse divider 1210, the NAND gate 1215, the clock divider 1220, the inverter 1225, and the RS flip. Flops 1230 may be used. The amplified sensing signal SPB_OUT whose switching time is removed by the RS flip-flop 1230 may be output.
Here, the NAND gates 1101 and 1201 and the D flip-flops 1109 and 1209 provide the switching control signals SWCNTL1 and SWCNTL2 to the first sensor unit 1100 and the second sensor unit 1200, respectively. With configurations for, it will be activated in response to the start signal (Start). When activated, the switching control signals SWCNTL1 and SWCNTL2 may control the switches 1106 and 1206 of the first sensor unit 1100 and the second sensor unit 1200 in synchronization with the clock signal CLK.
12B is a simplified block diagram of the second half 1000b of the differential analog-to-digital converter 1000. Referring to FIG. 12B, sensing signals SPA_OUT and SPB_OUT having information in a pulse width are converted into digital data by counters 1140 and 1240, respectively. That is, the magnitude of the pulse width is counted and output as data containing sensing information, and stored in the registers 1150 and 1250. The data stored in the first register 1150 and the second register 1250 are then processed by the N-bit subtractor 1300. As a result, the common mode noise included in each of the two amplified sensing signals SPA_OUT and SPB_OUT from which the switching time is removed may be removed.
13A and 13B are block diagrams illustrating a differential sensor device 2000 according to another exemplary embodiment. Referring to FIG. 13A, even when the clock dividing function is removed from the differential sensor device 1000a of FIG. 12A, the high resolution differential ADC function of the present invention can be performed. That is, in FIG. 13A, the NAND gates 1115 and 1215, the clock dividers 1120 and 1220, the inverters 1125 and 1225, and the RS flip-flops 1130, from the differential sensor device 1000a of FIG. 12A are illustrated. The differential sensor device 2000a is shown with 1230 removed. As a result, the elimination effect of switching time is reduced, but this type can provide an effective filtering function for the noise of the common mode.
FIG. 13B includes a configuration substantially the same as the latter configurations 1000b of the differential analog-to-digital converter 1000 of FIG. 12B. The only difference is that the input signal is the amplified signals SPA2 n and SPB2 n with no switching time removed. Therefore, a detailed description of the components of FIG. 13B will be omitted.
14 is a timing diagram illustrating an operation of the differential sensor device 1000a of FIG. 12A. Referring to FIG. 14, the first sensor unit 1100 and the second sensor unit 1200 will start sensing in response to the same clock signal CLK and a start signal Start. The capacitor voltages Vc1 and Vc2 are formed according to the periodic charging and discharging of the sensing capacitors C1 and C2, and the sensing signals SPA1 and SPB1 are output by the comparators 1108 and 1208. The pulse width amplification by the pulse dividers 1110 and 1210 for the sensing signals SPA1 and SPB1 may be performed and the amplified sensing signals SPA2 n and SPB2 n may be generated. Subsequently, when clock division by the clock dividers 1120 and 1220 and removal of the switching time by the RS flip-flops 1130 and 1230 are performed, the amplified sensing signals SPA_OUT and SPB_OUT will be output.
Counting and differential operations on the amplified sensing signals SPA_OUT and SPB_OUT are not shown in the timing diagram. However, effective filtering of noise is possible by the function of the differential analog-to-digital converter which performs the above-described sensing and pulse width amplification.
As described above, the embodiments are disclosed in the drawings and the specification. Although specific terms have been used herein, they are used only for the purpose of describing the present invention and are not used to limit the scope of the present invention as defined in the meaning or claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.
