JP2011097269A - Analog-digital converter - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an analog-digital converter that suppresses deterioration in characteristics. <P>SOLUTION: The analog-digital converter has a first differentiator 10 that subtracts a feedback signal from an analog input signal to generate a first differential signal, a first integrator 11 that integrates the first differential signals to generate an integral signal, N quantizers 14, 15, and 16 respectively input with each clock having a frequency whose phase is shifted by 2π/N (N is an integer of 2 or more) and respectively quantizing each integral signal, a selector 17 for selecting an output from each quantizer on the basis of the clock, and a digital-analog converter 18 input with the output from the selector 17 and generating the feedback signal asynchronously with the clock. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to an analog-digital converter, and more particularly to a delta-sigma modulation type analog-digital converter.

  A delta-sigma modulation analog-digital converter can realize high-precision analog-digital conversion (hereinafter referred to as AD conversion), and is therefore used as an AD converter for audio, wireless receivers, and the like.

  FIG. 11 is a diagram illustrating an AD converter disclosed in Patent Document 1. In FIG. The AD converter shown in FIG. 11 includes a subtractor 310, an integrator 320, sampling comparators 330 and 340, a switch 350, and a DAC 360. The input signal Sin input to the input terminal 300 is supplied to the subtractor 310. The subtractor 310 subtracts the feedback signal from the current input signal to generate a difference signal, and applies the difference signal to the integrator 320. The integrator 320 adds the difference signal to the sum of the previous difference signals to generate an integration signal, and supplies the integration signal to the sampling comparators 330 and 340.

  Sampling comparators 330 and 340 each quantize the integrated signal into one of two levels, sample the quantized signal in response to a control signal at sampling frequency fs / 2, and sample each value Dout1. , Dout2 are supplied to the output terminals 370 and 380 and the switch 350, respectively. Sampling clock signals supplied to the sampling comparators 330 and 340 are alternately distributed in time. That is, the sampling clock signal supplied to the comparator 330 is an odd-numbered pulse of the sampling clock signal fs, and the sampling clock signal supplied to the comparator 340 is an even-numbered pulse of the sampling clock signal fs.

  The switch 350 receives each of the output signals Dout1 and Dout2 sampled at the frequency of fs / 2, and alternately selects the output signals Dout1 and Dout2 based on the control signal of the frequency fs / 2 supplied from the input terminal 355. Yes. The output of the switch 350 is a signal having a desired sampling frequency fs, but each of the sampling comparators 330 and 340 operates at a frequency of fs / 2. The DAC 360 receives the output signals Dout1 and Dout2 that have passed through the switch and the control signal of the sampling frequency fs, generates a feedback signal based on the output signals Dout1 and Dout2, and outputs the feedback signal to the subtractor 310.

  Patent Document 2 discloses a technique related to an oversampling AD converter that can suppress jitter noise and realize a high S / N ratio. The oversampling AD converter disclosed in Patent Document 2 includes two forward path circuits, a determination circuit, a digital PLL, a selector, and a feedback loop. Each time the phase shift of the digital PLL is executed, a change in the quantization output of the delta-sigma noise shaper is observed depending on whether the phase shift is executed or not. In this observation, if there is a change, the probability that the slope of the analog input signal is steep is high, so the phase shift position is changed, and conversely if there is no change, the probability that the slope of the input signal is gentle is high. Control to enable phase shift is performed.

JP-A-8-265158 JP-A-6-53829

  In the AD converter according to Patent Document 1 shown in FIG. 11, the sampling comparators 330 and 340 are supplied with the sampling frequency fs / 2 whose phase is shifted by 180 degrees, and the quantized signal is sampled based on this frequency. ing. The switch 350 alternately outputs the output signals Dout1 and Dout2 to the DAC 360 by alternately selecting the terminals 350A and 350B to which the output signals Dout1 and Dout2 are supplied based on the control signal of the frequency fs / 2. is doing. Further, the DAC 360 generates a feedback signal from the output signals Dout1 and Dout2 sent from the switch 350 based on the sampling frequency fs.

  As described above, in the AD converter according to Patent Document 1, the sampling comparators 330 and 340 and the switch 350 are driven at the sampling frequency fs / 2, and the DAC 360 is driven at the frequency fs. For this reason, if an error occurs between the drive timing of the switch 350 (driven at the frequency fs / 2) and the drive timing of the DAC 360 (driven at the frequency fs), a timing error occurs between the output signals Dout1, Dout2 and the feedback signal that is the output of the DAC 360. Therefore, there is a problem that the characteristics of the AD converter deteriorate.

  An analog-to-digital converter according to the present invention generates a first difference signal that generates a first difference signal by subtracting a feedback signal from an analog input signal, and generates an integration signal by integrating the first difference signal. A first integrator, a clock having a frequency that is shifted by 2π / N (N is an integer of 2 or more), and N quantizers that respectively quantize the integrated signals; A selector that selects an output from each quantizer based on the clock; and a digital-to-analog converter that receives the output from the selector and generates the feedback signal asynchronously with the clock.

  In the analog-digital converter according to the present invention, since the feedback signal is generated asynchronously with the clock, it is possible to suppress occurrence of a timing error between the output signal from the selector and the feedback signal. Therefore, it is possible to suppress the deterioration of the characteristics of the analog-digital converter.

  According to the present invention, it is possible to provide an analog-digital converter capable of suppressing characteristic deterioration.

1 is a block diagram illustrating an analog-digital converter according to a first embodiment. 3 is a timing chart illustrating an operation of the analog-digital converter according to the first exemplary embodiment. FIG. 3 is a block diagram illustrating an analog-digital converter according to a second exemplary embodiment. 6 is a timing chart illustrating an operation of the analog-digital converter according to the second exemplary embodiment. 6 is a circuit diagram illustrating a configuration example of a DAC circuit of an analog-digital converter according to a second embodiment; FIG. FIG. 6 is a block diagram illustrating an analog-digital converter according to a third embodiment. FIG. 6 is a block diagram illustrating an analog-digital converter according to a fourth embodiment. FIG. 10 is a block diagram illustrating an analog-digital converter according to a fifth embodiment. 10 is a timing chart illustrating an operation when a delay circuit is not provided in the analog-digital converter according to the fifth embodiment and when a delay circuit is provided. It is a timing chart for demonstrating operation | movement of the AD converter which does not use this invention. It is a block diagram which shows the analog-digital converter concerning a background art.

Embodiment 1
Embodiment 1 of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an analog-digital converter (AD converter) according to this embodiment. The AD converter according to the present embodiment includes a difference unit 10, an integrator 11, N (N is an integer of 2 or more) quantizers 14, 15, 16, a selector 17, and a digital-analog converter (DAC) 18. Have

  The difference unit 10 subtracts the feedback signal AO that is the output of the DAC 18 from the analog input signal SIG to generate a difference signal, and outputs this difference signal to the integrator 11. The integrator 11 integrates the difference signal from the differentiator 10, that is, adds the difference signal to the sum of the immediately preceding difference signals to generate an integrated signal. The integrator 11 is, for example, a continuous time type integrator.

  Each of the N quantizers 14, 15, and 16 receives the integration signal from the integrator 11, and quantizes the integration signal. Outputs Q1, Q2, and QN from the quantizers 14, 15, and 16 are input to the selector 17, respectively. The N quantizers 14, 15, 16 are supplied with clocks CLK 1, CLK 2, CLKN having phases shifted by 2π / N, respectively, and based on this timing, the quantizers 14, 15, 16, 16 quantizes the integral signal. In other words, the first quantizer 14 is supplied with the clock CLK1 in which the phase of the clock frequency fos / N is shifted by 0 radians (ie, the phase is not shifted). The second quantizer 15 is supplied with a clock CLK2 in which the phase of the clock frequency fos / N (Hz) is shifted by 2π / N radians. The Nth quantizer 16 is supplied with a clock CLKN with the phase of the clock frequency fos / N shifted by (N−1) × 2π / N radians. Thus, the N quantizers 14, 15, and 16 of the AD converter according to the present embodiment perform an interleave operation.

  The selector 17 receives the outputs Q1, Q2, and QN from the N quantizers 14, 15, and 16, and sets one of these outputs Q1, Q2, and QN to a frequency whose phase is shifted by 2π / N. It selects based on the clocks CLK1, CLK2, and CLKN that it has and outputs it as a digital output DOUT. The digital output DOUT in this case is a signal with a sampling rate of fos (Hz). The output from the selector 17 is also supplied to the DAC 18. The DAC 18 receives the output from the selector 17 and generates a feedback signal supplied to the differentiator 10 asynchronously with the clock. That is, the DAC 18 is not clocked.

  Next, the operation of the AD converter according to this embodiment will be described with reference to FIG. FIG. 2 is a timing chart showing the operation of the analog-digital converter according to the present embodiment. When the analog input signal SIG is input to the differencer 10, the differencer 10 subtracts the feedback signal AO output from the DAC 18 from the analog input signal SIG to generate a difference signal, and outputs this difference signal to the integrator 11. To do. The integrator 11 integrates the difference signal from the difference unit 10 and outputs this integration signal to the N quantizers 14, 15, and 16.

The N quantizers 14, 15, and 16 have rising edges of clocks CLK1, CLK2, and CLKN whose phases are shifted by (N−1) × 2π / N (N is an integer of 2 or more), respectively, as shown in FIG. The quantized signal from the integrator 11 is quantized. That is, the first quantizer 14, an integral signal from the integrator 11 at a timing when the clock CLK1 rises quantized, and generates a digital signal D ₁ is output Q1. The selector 17 selects the output Q1 of the first quantizer 14 (Ch1) at the timing when the clock CLK1 rises, and outputs a digital signal _{D 1} as a digital output DOUT. Further, the DAC 18 generates the feedback signal A ₁ at the timing when the selector 17 outputs the digital signal D ₁ as the digital output DOUT, and outputs this feedback signal to the differentiator 10.

Second quantizer 15, an integral signal from the integrator 11 at a timing when the clock CLK2 rises and quantized, and generates a digital signal D ₂ which is the output Q2. The selector 17 selects the output Q2 (Ch2) of the second quantizer 15 at the timing when the clock CLK2 rises, and outputs a digital signal _{D 2} as a digital output DOUT. Further, the DAC 18 generates the feedback signal A ₂ at the timing when the selector 17 outputs the digital signal D ₂ as the digital output DOUT, and outputs the feedback signal to the differencer 10.

Quantizer 16 of the N is an integral signal from the integrator 11 as the clock CLKN rises quantized, and generates a digital signal D _N is output QN. The selector 17 selects the output QN of the N-th quantizer 16 (ChN) at the timing when the clock CLKN rises, and outputs a digital signal _{D N} as a digital output DOUT. Further, DAC 18 is at the timing at which the selector 17 has output a digital signal _{D N} as a digital output DOUT, and generates a feedback signal _{A N,} and outputs the feedback signal to the differentiator 10.

In the AD converter according to this embodiment, as shown in FIG. 2, digital output signals D ₁ , D ₂ ,..., _DN are output in one cycle of the sampling rate fos (Hz). Here, the operation clock of the N quantizers 14, 15, and 16 is fos / N (Hz), whereas the sampling rate of the digital output DOUT is fos (Hz). Therefore, in the AD converter according to the present embodiment, the N quantizers 14, 15, 16 are interleaved so that the operation clock of the N quantizers 14, 15, 16 is higher than the sampling rate fos. Can be lowered.

In the AD converter according to the present embodiment, the DAC 18 is not controlled by the clock, so the DAC 18 selects one of the outputs Q1, Q2, and QN of the N quantizers 14, 15, and 16 from the DAC 18. Then, feedback signals A ₁ , A ₂ ,..., A _N are generated at the timing of output to the DAC 18. Thus, the digital output signal _{D 1, D 2, ···,} D N and the feedback signal _{A 1,} A 2, · · ·, since there is no fact that the timing error occurs in the _{A N,} the characteristics of the AD converter is degraded That can be suppressed.

FIG. 10 is a timing chart for explaining the operation of the AD converter not using the present invention. In the AD converter in this case, the DAC 18 of the AD converter shown in FIG. 1 is driven by clocks DCLK1, DCLK2,..., DCLKN. As shown in FIG. 10, a first quantizer 14, an integral signal from the integrator 11 at a timing when the clock CLK1 rises quantized, and generates a digital signal D ₁ is output Q1. The selector 17 selects the output Q1 of the first quantizer 14 at the timing of the clock CLK1 rises, and outputs a digital signal _{D 1} as a digital output DOUT. Meanwhile, DAC 18 at the timing of the clock DCLK1 rises, generating a feedback signal _{A 1.} However, for example, when the rise timing of the clock CLK1 and clock DCLK1 is shifted as shown in FIG. 10, (indicated by arrows) the digital output signal D ₁ and the feedback signal A ₁ and the timing error. This timing error causes the characteristic deterioration of the AD converter.

In the AD converter according to the present embodiment, the DAC 18 is controlled asynchronously with the clock in order to suppress the deterioration of the characteristics of the AD converter due to the shift of the rising timing of the clock CLK1 and the clock DCLK1. Therefore, the AD converter according to the present embodiment the digital output signal _{D 1, D 2, ···,} D N and the feedback signal _{A 1,} A 2, · · ·, is not the timing error occurs in the _{A N} Therefore, it is possible to suppress degradation of the characteristics of the AD converter.

Embodiment 2
Next, a second embodiment of the present invention will be described. FIG. 3 is a block diagram showing an analog-digital converter (AD converter) according to this embodiment (in the case of a first-order continuous delta-sigma modulator). The AD converter according to the present embodiment has a configuration when N = 2 in the AD converter described in the first embodiment. That is, the AD converter according to the present embodiment includes a difference unit 20, an integrator 21, two quantizers 24 and 25, a selector 27, and a digital / analog converter (DAC) 28. About each component, since it is the same as that of the case demonstrated in Embodiment 1, the overlapping description is abbreviate | omitted.

  The operation of the AD converter according to this embodiment will be described with reference to FIGS. In the AD converter according to the present embodiment, the clock fos / 2 (Hz) is supplied to the first quantizer 24, and the first quantizer 24 is supplied to the first quantizer 24. And a clock whose phase is shifted by π radians. The first quantizer 24 quantizes the output of the integrator 21 at the rising timing of the clock CLK of fos / 2 (Hz). The selector 27 selects the path (Ch1) of the first quantizer 24 while the clock is at the H level, and outputs the quantized data Q1 to the digital output DOUT.

  On the other hand, the second quantizer 25 quantizes the output of the integrator 21 at the falling timing of the clock CLK (that is, the rising timing of the fos / 2 (Hz) clock whose phase is shifted by π radians). . The selector 27 selects the path (Ch2) of the second quantizer 25 while the clock CLK is at the L level, and outputs the quantized data Q2 to the digital output DOUT. Also in the present embodiment, the two quantizers 24 and 25 of the AD converter perform an interleave operation.

  The output from the selector 27 is also supplied to the DAC 28. The DAC 28 receives the output from the selector 27 and generates a feedback signal supplied to the differentiator 20 asynchronously with the clock. That is, the DAC 28 is not clocked.

  FIG. 5 is a circuit diagram showing a configuration example of the DAC 28 of the AD converter according to the present embodiment. As shown in FIG. 5, the DAC 28 includes constant current sources 60, 61, 63, a switch 62, and an inverter 64. The constant current source 60 is connected to the output of the feedback signal AO and one switch element 62 </ b> A of the switch 62 at the first node 65. The constant current source 61 is connected to the output of the feedback signal AOB (inverted data of AO) and the other switch element 62B of the switch 62 at the second node 66. The switch 62 is connected to the constant current source 63. The switch 62 is supplied with the DOUT signal and the DOUTB signal (inverted data of DOUT). The DOUTB signal can be generated by inverting the DOUT signal using the inverter 64.

  The switch elements 62A and 62B are connected when the signals supplied to the switch elements 62A and 62B are at the H level. When the DOUT signal is at the L level, the switch element 62A is not connected, so that the current + I is supplied from the constant current source 60 to the feedback signal AO. In this case, since the DOUTB signal is at the H level, the switch element 62B is in a connected state, and the feedback signal AOB has a current -I (a value obtained by subtracting '2I' of the constant current source 63 from 'I' of the constant current source 61). ) Is supplied. On the other hand, when the DOUT signal is at the H level, the switch element 62A is in a connected state, and the feedback signal AO has a current -I (a value obtained by subtracting "2I" of the constant current source 63 from "I" of the constant current source 60). Is supplied. In this case, since the DOUTB signal becomes L level, the switch element 62B is not connected, and the current + I is supplied from the constant current source 61 to the feedback signal AOB. As described above, by using the DAC illustrated in FIG. 5, a digital signal can be converted into an analog signal.

  Also in the AD converter according to the present embodiment, by operating the two quantizers 24 and 25 in an interleaved manner, the operation clock of the two quantizers 24 and 25 can be made lower than the sampling rate fos. it can. Also, in the AD converter according to the present embodiment, since the DAC 28 is not controlled by the clock, there is no timing error between the digital output signal DOUT and the feedback signal AO, and the characteristics of the AD converter deteriorate. Can be suppressed.

Embodiment 3
Next, a third embodiment of the present invention will be described. FIG. 6 is a block diagram showing an analog-digital converter (AD converter) according to the present embodiment (in the case of a secondary feedback type continuous delta sigma modulator). In the AD converter according to the present embodiment, N = 2 in the AD converter described in the first embodiment, and the order of the integrator is second order. That is, the AD converter according to the present embodiment includes a first difference unit 30, a first integrator 31, a second difference unit 32, a second integrator 33, and two quantizers 34 and 35. , A selector 37 and a digital-analog converter (DAC) 38. In the present embodiment, the same components as those described in the first and second embodiments are not described repeatedly.

  The first subtractor 30 subtracts the feedback signal AO that is the output of the DAC 38 from the analog input signal SIG to generate a first difference signal, and outputs the first difference signal to the first integrator 31. . The first integrator 31 integrates the first difference signal from the first differentiator 30 to generate an integrated signal. The second subtractor 32 subtracts the feedback signal AO that is the output of the DAC 38 from the integrated signal generated by the first integrator to generate a second differential signal, and the second differential signal is converted into the second differential signal. To the integrator 33. The second integrator 33 integrates the second difference signal generated by the second differentiator 32 to generate an integrated signal. Here, the first and second integrators 31 and 33 are, for example, continuous-time integrators.

  The first quantizer 34 is supplied with the clock fos / 2 (Hz), and the second quantizer 35 is supplied with the clock supplied to the first quantizer 34 and the phase is π radians. A shifted clock is supplied. The first quantizer 34 quantizes the integrated signal generated by the second integrator 33 at the rising timing of the clock CLK of fos / 2 (Hz). The selector 37 selects the path (Ch1) of the first quantizer 34 while the clock is at the H level, and outputs the quantized data Q1 to the digital output DOUT.

  On the other hand, the second quantizer 35 is generated by the second integrator 33 at the falling timing of the clock CLK (that is, the rising timing of the clock of fos / 2 (Hz) whose phase is shifted by π radians). Quantize the integrated signal. The selector 37 selects the path (Ch2) of the second quantizer 35 while the clock CLK is at the L level, and outputs the quantized data Q2 to the digital output DOUT. Also in this embodiment, the two quantizers 34 and 35 of the AD converter perform an interleave operation.

  The output from the selector 37 is also supplied to the DAC 38. The DAC 38 receives the output from the selector 37 and generates a feedback signal supplied to the first and second subtractors 30 and 32 asynchronously with the clock. That is, the DAC 28 is not clocked.

  Also in the AD converter according to the present embodiment, the operation clocks of the two quantizers 34 and 35 can be made lower than the sampling rate fos by interleaving the two quantizers 34 and 35. it can. Also, in the AD converter according to the present embodiment, since the DAC 38 is not controlled by the clock, there is no timing error between the digital output signal DOUT and the feedback signal AO, and the characteristics of the AD converter deteriorate. Can be suppressed.

Embodiment 4
Next, a fourth embodiment of the present invention will be described. FIG. 7 is a block diagram showing an analog-to-digital converter (AD converter) according to the present embodiment (in the case of a secondary feed-forward continuous delta-sigma modulator). In the AD converter according to the present embodiment, N = 2 in the AD converter described in the first embodiment, and the order of the integrator is second order. That is, the AD converter according to the present embodiment includes a difference unit 40, a first integrator 41, a second integrator 42, an adder 43, two quantizers 44 and 45, a selector 47, a digital analog. A converter (DAC) 48 is included. In the present embodiment, the same components as those described in the first and second embodiments are not described repeatedly.

  The difference unit 40 subtracts the feedback signal AO output from the DAC 48 from the analog input signal SIG to generate a difference signal, and outputs the difference signal to the first integrator 41. The first integrator 41 integrates the difference signal generated by the differentiator 40 to generate an integrated signal. The second integrator 42 integrates the integration signal generated by the first integrator 41 to generate an integration signal. The adder 43 receives the integration signal generated by the first integrator 41 and the integration signal generated by the second integrator 42, and generates an output signal. Here, the first and second integrators 41 and 42 are, for example, continuous-time integrators.

  The first quantizer 44 is supplied with a clock fos / 2 (Hz), and the second quantizer 45 is supplied with a clock and a phase of π radians supplied to the first quantizer 44. A shifted clock is supplied. The first quantizer 44 quantizes the output of the adder 43 at the rising timing of the clock CLK of fos / 2 (Hz). The selector 47 selects the path (Ch1) of the first quantizer 44 while the clock is at the H level, and outputs the quantized data Q1 to the digital output DOUT.

  On the other hand, the second quantizer 45 quantizes the output of the adder 43 at the falling timing of the clock CLK (that is, the rising timing of the fos / 2 (Hz) clock whose phase is shifted by π radians). . The selector 47 selects the path (Ch2) of the second quantizer 45 while the clock CLK is at the L level, and outputs the quantized data Q2 to the digital output DOUT. Also in the present embodiment, the two quantizers 44 and 45 of the AD converter perform an interleave operation.

  The output from the selector 47 is also supplied to the DAC 48. The DAC 48 receives the output from the selector 47 and generates a feedback signal supplied to the differentiator 40 asynchronously with the clock. That is, the DAC 28 is not clocked.

  Also in the AD converter according to the present embodiment, by operating the two quantizers 44 and 45 in an interleaved manner, the operation clock of the two quantizers 44 and 45 can be made lower than the sampling rate fos. it can. Also, in the AD converter according to the present embodiment, the DAC 48 is not controlled by the clock, so that a timing error does not occur in the digital output signal DOUT and the feedback signal AO, and the characteristics of the AD converter deteriorate. Can be suppressed.

Embodiment 5
Next, a fifth embodiment of the present invention will be described. FIG. 8 is a block diagram showing an analog-digital converter (AD converter) according to this embodiment (in the case of a first-order continuous delta-sigma modulator). The AD converter according to this embodiment has a configuration in which a delay circuit 59 is added to the AD converter described in the second embodiment. That is, the AD converter according to the present embodiment includes a difference unit 50, an integrator 51, two quantizers 54 and 55, a selector 57, a digital / analog converter (DAC) 58, and a delay circuit 59. About each component, since it is the same as that of the case demonstrated in Embodiment 2, the overlapping description is abbreviate | omitted.

FIG. 9 is a timing chart showing the operation when the delay circuit 59 is not provided in the analog-digital converter shown in FIG. 8 and when the delay circuit 59 is provided. As shown in FIG. 9, when the quantizers 54 and 55 are delayed, the quantizers 54 and 55 output the quantized signals after a predetermined time has elapsed from the timing of the clock CLK. For example, the output Q1 of the first quantizer 54, a predetermined time from the rise timing of the clock CLK (arrow in FIG. 9) with a delay, and outputs the signal D ₂ after quantization. On the other hand, the selector 57 selects Ch1 at the rising timing of the clock CLK and selects Ch2 at the falling timing of the clock CLK.

In this case, the digital output DOUT at the rising edge of the clock CLK, is output D ₀ is the output Q1 of the quantizer 54, D ₂ is the output Q1 of the quantizer 54 is output after delay time has elapsed The As described above, when the quantizers 54 and 55 are delayed, errors (D ₀ , D ₁ , D ₂ , D ₃ ) as shown in FIG. 9 occur, and the characteristics of the AD converter deteriorate.

  In the AD converter according to the present embodiment, by providing a delay circuit 59 that adds a delay to the clock CLK supplied to the selector 57, the timing at which the selector 57 selects the channels Ch1 and Ch2 is determined by the quantizer 54, 55 is synchronized with the output timing of the quantized signal (see FIG. 9). That is, in the AD converter according to the present embodiment, the timing at which the selector 57 selects the channels Ch1 and Ch2 coincides with the timing at which the quantizers 54 and 55 output the quantized signal, This is after the quantizers 54 and 55 output quantized signals. As described above, the timing at which the selector 57 selects the channel and the timing at which the quantizers 54 and 55 output the quantized signal are synchronized using the delay circuit 59, thereby causing the delay of the quantizer. It is possible to suppress the deterioration of the characteristics of the AD converter.

  In the second to fifth embodiments, the case where two quantizers are provided has been described, but more quantizers may be provided.

  Although the present invention has been described with reference to the above embodiment, the present invention is not limited to the configuration of the above embodiment, and can be made by those skilled in the art within the scope of the invention of the claims of the claims of the present application. Needless to say, various modifications, corrections, and combinations are included.

10, 20, 30, 32, 40, 50 Differentiator 11, 21, 31, 33, 41, 42, 51 Integrator 14, 24, 34, 44, 54 First quantizer 15, 25, 35, 45 55 Second quantizer 16 Nth quantizer 17, 27, 37, 47, 57 Selector 18, 28, 38, 48, 58 DAC
59 Delay devices 60, 61, 63 Constant current source 62 Switch 64 Inverter

Claims (8)

A first differentiator that subtracts a feedback signal from an analog input signal to generate a first difference signal;
A first integrator that integrates the first differential signal to generate an integrated signal;
N quantizers that respectively input clocks having frequencies shifted by 2π / N (N is an integer of 2 or more) and quantize the integrated signals,
A selector for selecting an output from each quantizer based on the clock;
A digital-to-analog converter that receives an output from the selector and generates the feedback signal asynchronously with the clock;
An analog-to-digital converter. The analog-digital converter is
A second subtractor that subtracts the feedback signal from the integrated signal generated by the first integrator to generate a second differential signal;
A second integrator that integrates the second difference signal to generate an integrated signal;
2. The analog-to-digital converter according to claim 1, wherein each of the N quantizers quantizes an integrated signal generated by the second integrator. The analog-digital converter is
A second integrator that integrates the integrated signal generated by the first integrator to generate an integrated signal;
An adder for adding the integration signal generated by the first integrator and the integration signal generated by the second integrator;
The analog-to-digital converter according to claim 1, wherein each of the N quantizers quantizes an integrated signal output from the adder.   The nth quantizer among the N quantizers quantizes the integrated signal based on the timing of the nth clock (n is an integer between 1 and N) in the clock, and the nth quantizer 4. The analog-to-digital converter according to claim 1, wherein the selector selects a signal quantized by the n-th quantizer based on the timing of the clock.   The analog-to-digital converter is configured so that a timing at which the quantizer outputs a signal coincides with a timing at which the selector selects an output from the quantizer, or the quantizer outputs a signal. 5. The analog according to claim 1, further comprising a delay circuit that adds a delay to the clock input to the selector so that the selector selects an output from the quantizer later. Digital converter. The digital-to-analog converter is
A first constant current source connected to the first node;
A second constant current source connected to the second node;
A third constant current source connected to the first node or the second node;
A switch for selecting connection between the first node and the third constant current source or connection between the second node and the third constant current source in accordance with an output from the selector; Have
6. The analog-digital converter according to claim 1, wherein currents in the first and second nodes are output as the feedback signal. 7.   The analog-digital converter according to any one of claims 1 to 6, wherein the analog-digital converter is a delta-sigma type analog-digital converter.   The analog-digital converter according to any one of claims 1 to 7, wherein the integrator is a continuous-time integrator.

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