JPH06224764A - A/d converter - Google Patents

Abstract

PURPOSE:To attain high accuracy and high resolution by decreasing number of comparators. CONSTITUTION:An analog input signal Vs is sampled and held for a prescribed period by a sample-and-hold circuit 110 and the result is fed to plural comparators 60-63. Then analog switches 44-47 are sequentially turned on by a control signal phiB2 and different comparison reference voltages are inputted to comparators 60-63 from a voltage divider 81. Holding analog voltages are compared by the comparators 60-63 and the result of comparison is outputted to a position detection logic circuit 120. The output of the position detection logic circuit 120 is coded by a code conversion circuit 100 to obtain a 1st conversion result. Then 2nd-4th conversion results are obtained similarly by control signals phiA2, phiB1, phiA1. The code conversion circuit 100 combines the conversion results and a digital signal having a desired conversion characteristic is outputted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an analog-digital (A / D) converter, and more particularly to a parallel comparison type A / D converter using a two-stage voltage divider. .

[0002]

2. Description of the Related Art A parallel comparison type A / D converter has a reference voltage V
^An analog input voltage Vs is simultaneously applied to 2 ^N −1 comparators with different output voltages of voltage dividers that divide ^N into two as a comparison reference, and the result is encoded to be a digital conversion output. . This parallel comparison method is A /
Assuming that the number of bits of the D converter is N, it has 2 ^N −1 comparators, and as N is increased, the number of bits increases, for example, each time N is increased by 1, the number of comparators is approximately doubled. Need to increase.

FIG. 3 shows an example of the configuration of a conventional parallel comparison type A / D converter in which the number of comparators is reduced, where N = 3. Here, N is the number of bits that the A / D converter has.
In FIG. 3, reference numeral 130 denotes a voltage divider, which includes a plurality of resistors 11
˜15, and the connection points between these resistors form outputs 80-83, respectively. The resistors 11 and 15 are
The resistance value of the resistor 11 can be changed to R / 2 and R, and the resistance value of the resistor 15 can be changed to R / 2 and 0. Moreover, the sum of the resistance 11 and the resistance 15 is variable so that it is always R.

The resistance values of the other resistors 12 to 14 are all R. In addition, the voltage divider 130 has a first reference voltage V _R.
And a second reference voltage GND. Further, the plurality of outputs 80 to 83 of the voltage divider 130 are connected to the comparison reference input terminals of the plurality of comparators 60 to 63, respectively. The position detection logic circuit 120 is composed of a plurality of logic gates 70 to 73, the output of which is connected to the code conversion circuit 100 having digital outputs 510 to 512.

The sampling circuit 110 for sampling the analog input signal Vs operates according to the sampling clock fs. The operation will be described below with reference to FIG. First, the resistances at both ends of the resistor string forming the voltage divider 130, that is, the resistance value of the resistor 11 is set to R / 2, and the resistance value of the resistor 15 is set to R / 2. Next, the analog input signal Vs is sampled by the sampling circuit 110 and held for a certain period, and the held analog voltage is simultaneously applied to the plurality of comparators 60 to 63 each having a different comparison reference.

As a result, the output of the comparator in which the held analog voltage is higher than the comparison reference becomes low level, that is, "0", and conversely, the output of the comparator in which the held analog voltage is lower than the comparison reference is high level, That is, it becomes "1". Therefore, a plurality of comparators 60-63
Are divided into a comparator whose output is "0" and a comparator whose output is "1", depending on the value of the held analog voltage.

Therefore, the position detection logic circuit 120 sets the output of the gate corresponding to the boundary between the comparator whose output is "0" and the comparator whose output is "1" to "1". The output of the position detection logic circuit 120 is used as the code conversion circuit 100.
To obtain the first conversion result having a resolution of 2 bits. The conversion characteristic at this time is (2n-1) / 8 (n = 1,2,3,4) of the analog input as shown in FIG.
The first conversion characteristic changes the digital code at each point.

Next, the resistances at both ends of the resistor string constituting the voltage divider 130, that is, the resistance value of the resistor 11 is set to R, and the resistance value of the resistor 15 is set to 0, respectively. At this time, since the held analog voltage is still applied to the plurality of comparators 60 to 63, the respective comparators 60 to 63 are
Only the comparison criteria of ~ 63 have changed.

In this state, the same conversion characteristic as the previous one is repeated to obtain a second conversion result having a 2-bit resolution. The conversion characteristic at this time is the second conversion characteristic in which the digital code changes at each point of analog (2n) / 8 (n = 1, 2, 3, 4) as shown in FIG. 4B. . The code conversion circuit 100 outputs a 3-bit digital signal having the conversion characteristic shown in c of FIG. 4 to the output terminals 510 to 512 by combining the first conversion result and the second conversion result.

As described above, by varying the resistance values of the resistors 11 and 15 at both ends of the resistor string constituting the voltage divider 130, the number of comparators is 2 ^N -1 while having the same resolution.
The number can be reduced to 2 ^N-1 and about 1/2.

[0011]

In the above-mentioned conventional parallel comparison type A / D converter, the resistance values of the resistors 11 and 15 at both ends of the resistor string forming the voltage divider 130 are variable in two values. The resistor 11 is shown in FIG.
As shown in (b) respectively, a circuit composed of a resistor r having the same resistance value R as the other resistors 12 to 14 and a switch SW is used.

When such a parallel comparison type A / D converter is made into a monolithic integrated circuit, a semiconductor switch is used as the switch SW forming the resistors 11 and 15. However, since the ON resistance of the semiconductor switch is as large as several tens to several hundreds ohms, the resistances 11 and 15 do not become R / 2 accurately because of the ON resistance of the switch.

Therefore, in the conventional parallel comparison type A / D converter, the theoretical characteristics cannot be obtained for the first conversion characteristic and the second conversion characteristic, so that the combined conversion characteristic has a conversion error. There was a problem of causing. Further, if the resolution is increased, there is a problem that many comparators are required. The present invention has been provided in view of the above point, and it is necessary to provide an A / D converter without changing the resistance at both ends of a resistor string that constitutes a voltage divider for supplying a reference voltage. It is an object of the present invention to provide a parallel comparison type A / D converter with high resolution and high accuracy by reducing the number of comparators to be used.

[0014]

According to the present invention, there is provided a first voltage divider comprising a plurality of resistor strings connected in series between a first reference voltage and a second reference voltage, and a third reference voltage divider. Voltage and fourth
A second voltage divider composed of a plurality of resistor strings connected in series with the reference voltage of the second voltage divider and a plurality of outputs of the first voltage divider and the second voltage divider are selectively inputted. A plurality of analog multiplexers that output, a sampling circuit that samples an analog input signal and holds it for a certain period, a signal from the sampling circuit is input to one input terminal, and a signal from the analog multiplexer is input to the other input terminal. A plurality of comparators that compare the magnitudes of the input signal voltages, a position detection logic circuit that receives the outputs from the plurality of comparators as inputs, and the output of this position detection logic circuit that is converted into a digital value. A code conversion circuit is provided, and the comparison reference value from the voltage divider input to the comparator is switched by a plurality of analog multiplexers to perform A / D conversion a plurality of times. The times of the A / D conversion result is obtained to obtain the A / D conversion result by combining the above code conversion circuit.

[0015]

According to the present invention, the number of comparators can be reduced, and since the analog switch which the conventional parallel comparison type A / D converter has is not used, conversion by the on resistance of the analog switch is performed. An error does not occur, and the comparison reference can have a high resolution by using two stages of the voltage divider.

[0016]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows an example of the circuit configuration of the parallel comparison type A / D converter of the present invention, in which N = 3. Where N is A / D
It is the number of bits that the converter has. In FIG. 1, reference numerals 80 and 81 denote voltage dividers, which are composed of a plurality of resistors,
Each of the voltage dividers 80 and 81 is composed of a resistor string of resistors 1 to 9 and resistors 10 to 18. The connections between these resistors are 20-27 and 28-35.

The resistance values of the resistors 10 and 18 are R / 2,
The resistance values of the other resistors 11 to 17 and the resistors 1 to 9 are R, and the resistance values of the entire voltage dividers 80 and 81 are set to 8R. The voltage divider 80 and the voltage divider 81 are connected between the first reference voltage V _R and the second reference voltage GND. Analog switches 40 to 43 and 48 to 51 forming an analog multiplexer are connected to outputs 20 to 27 of the voltage divider 80.

The analog switches 40 and 48, the analog switches 41 and 49, the analog switches 42 and 50, and the analog switches 43 and 51 are multiplexers a and a, respectively.
The multiplexer b, the multiplexer c, and the multiplexer d are configured. The other voltage divider 81 has a multiplexer of exactly the same type, and the voltage dividers 80 and 81 are connected in parallel via the multiplexers, and control signals φ _A1 and φ _A2 and φ _B1 and φ _{B2 are connected.} Is used to selectively output any one of the plurality of inputs.

Also, analog switches 44 and 52, analog switches 45 and 53, and analog switches 46 and 5
4. The analog switches 47 and 55 form a multiplexer e, a multiplexer f, a multiplexer g, and a multiplexer h, respectively. And the multiplexer a
And the output of the multiplexer e is the comparator 60, the outputs of the multiplexers b and f are the comparator 61, the outputs of the multiplexers c and g are the comparator 62, and the outputs of the multiplexers d and h are the comparison reference input terminals of the comparator 63. Respectively connected to.

The outputs of the comparators 60 to 63 are respectively connected to the logic gates 70 to 73 which form the position detection logic circuit 120, and the outputs of the position detection logic circuit 120 are connected to the code conversion circuit 100. A sampling circuit 110 samples the analog input signal Vs, and operates according to the sampling clock fs.

The operation will be described below with reference to FIG. First, the analog input signal Vs is sampled by the sampling circuit 110 and held for a certain period. The held analog signal voltage is applied to each of the plurality of comparators 60 to 63. Next, the analog switch 44 to 47 forming the multiplexer is turned on by the control signal φ _B2 for controlling the on / off of the analog switch to turn on the voltage divider 81.
The different comparison reference voltages output from the above are input to the comparison reference input terminals of the plurality of comparators 60 to 63, respectively.

The held analog voltage is compared with the comparison reference voltage. When the analog voltage is larger, the comparator outputs "0", and when the analog voltage is larger than the comparison reference voltage, the comparator outputs "1". Output. The position detection logic circuit 120 detects the boundary between the comparator that becomes “0” and the comparator that becomes “1”, and determines the output of the gate corresponding to the boundary among the logic gates 70 to 73.

This output is encoded by the code conversion circuit 100 to obtain the first conversion result. The conversion result has a resolution of 2 bits. As shown in A of FIG. 2, this is (4n + 1) / 16 (n = 0, 1, 2,
It becomes the first conversion characteristic in which the digital code changes at each point of 3). Next, the analog switch 4 is controlled by the control signal φ _B2.
4 to 47 are turned off, then the analog signals 40 to 43 are turned on by the control signal φ _A2 , and the comparison reference voltage different from the previous time is applied to the comparators 60 to 63.

At this time, since the held analog voltage does not change, only the comparison reference changes. By repeating the same operation as before,
The conversion result shown in B is obtained. The conversion result has a resolution of 2 bits. This is analog input (4n) /
The second conversion result in which the digital code changes at each point of 16 (n = 0, 1, 2, 3) is obtained.

Then, the same operation as the previous operation is repeated, and the control signal φ _B1 and the control signal φ _A1 are operated to change to C in FIG.
And the conversion result of D is obtained. C is an analog input (4n +
3) / 16 (n = 0,1,2,3), D is the third and third digital code that changes at each point of (4n + 2) / 16 (n = 0,1,2,3) of the analog input. The conversion characteristic is 4.

The code conversion circuit 100 includes the first and second circuits.
By combining the third and fourth conversion results with each other, a 3-bit digital signal having the conversion characteristic shown in E of FIG. 2 is output. By the way, the output is not 3 bits,
It can also be an N-bit integer. At this time, the number of comparators becomes 2 ^N-1 .

[0027]

As described above, according to the present invention, the first voltage divider composed of a plurality of resistor strings connected in series between the first reference voltage and the second reference voltage, and the third reference voltage divider. A second voltage divider composed of a plurality of resistor strings connected in series between the voltage and the fourth reference voltage, and a plurality of outputs of the first voltage divider and the second voltage divider are input. A plurality of analog multiplexers that selectively output, a sampling circuit that samples an analog input signal and holds it for a certain period, a signal from the sampling circuit is input to one input end, and the analog multiplexer is input to the other input end. From a plurality of comparators that receive the signals from the comparators to compare the magnitude of the signal voltage, the position detection logic circuit that receives the outputs from the plurality of comparators as input, and the digital signal that receives the output of this position detection logic circuit. To value And a code conversion circuit for converting, the comparison reference value from the voltage divider input to the comparator is switched by a plurality of analog multiplexers to perform A / D conversion a plurality of times, and the A / D conversion results of the plurality of times are obtained. Since the A / D conversion result is obtained by synthesizing by the code conversion circuit, an analog multiplexer is used instead of the semiconductor switch, and a voltage divider is provided in two stages to achieve high resolution and conversion. Parallel comparison type A / which has features that no error occurs and the number of comparators can be reduced
This has the effect of realizing a D converter.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a parallel comparison type A / D converter according to an embodiment of the present invention.

FIG. 2 is a conversion characteristic diagram of the parallel comparison A / D converter shown in FIG. 1 above.

FIG. 3 is a circuit diagram of a parallel comparison type A / D converter of a conventional example.

FIG. 4 is a conversion characteristic diagram of the parallel comparison type A / D converter shown in FIG.

5 (a) and (b) are conventional parallel comparison type A /
It is a circuit diagram which comprises the variable resistance used for the D converter.

[Explanation of symbols]

 1-18 resistance 40-55 analog switch 60-63 comparator 80,81 voltage divider 100 sign conversion circuit 110 sampling circuit 120 position detection logic circuit

Claims (1)

[Claims] 1. A first voltage divider comprising a plurality of resistor strings connected in series between a first reference voltage and a second reference voltage, a third reference voltage and a fourth reference voltage. A second voltage divider composed of a plurality of resistor strings connected in series between a plurality of resistors, and a plurality of inputs for selectively outputting a plurality of outputs of the first voltage divider and the second voltage divider. An analog multiplexer, a sampling circuit that samples an analog input signal and holds it for a certain period of time, a signal from the sampling circuit is input to one input terminal, and a signal from the analog multiplexer is input to the other input terminal. A plurality of comparators for comparing the magnitudes of voltages, a position detection logic circuit that receives the outputs from the plurality of comparators as inputs, and a code conversion circuit that receives the output of the position detection logic circuit and converts it to a digital value To The comparison reference value from the voltage divider input to the comparator is switched by a plurality of analog multiplexers to perform A / D conversion a plurality of times.
A / D conversion result is obtained by synthesizing the A / D conversion result in the code conversion circuit.
D converter.