JP2001237703A - Arbitrary waveform generator - Google Patents

Abstract

[Problem] To provide an arbitrary waveform generator which is low-cost, has excellent timing accuracy and voltage accuracy, and has a wide-band differential output or a sub-output. A waveform data stored in a waveform data memory is sequentially read out at a timing of a clock signal applied to a clock signal terminal. On a non-inverted signal side, a first DA converter converts digital data into digital data. The signal is converted into an analog signal, amplified by the first amplifier 16 to a desired amplitude, and provided to the output terminal 18 as a non-inverted signal. On the inverted signal side, the sign is inverted by the sign inverting circuit 22 to be converted into digital data, then converted by the second DA converter 24 into an analog signal, and amplified by the second amplifier 26 to a desired amplitude. Then, it is output to the inverted output terminal 28.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a signal generator,
In particular, the present invention relates to an arbitrary waveform generator for generating a differential signal of an analog signal or various sub-output signals.

[0002]

2. Description of the Related Art Generally, an arbitrary waveform generator of an IC tester is used to generate a low distortion signal with high timing accuracy. However, in recent years, with the increase in the speed and the reduction in the voltage of the device, the number of opportunities for requiring a differential output of a signal has been increased. The reason is that if the differential output signal whose polarity is inverted is transmitted through a shielded twisted pair line, the sum of the entire signal becomes almost 0 volt, so that it is resistant to noise. If the difference is taken, the amplitude becomes twice, so that a signal having an amplitude twice as large as the power supply can be sent, which is advantageous for signal transmission.

Conventionally, the following four methods have been considered in order to obtain a differential output for testing a device under test (DUT: Device Under Test) using an IC tester.

[0004] (1) A method using a transformer, (2) A method using an inverting amplifier and a non-inverting amplifier, (3) A method of interlocking arbitrary waveform generators for two channels, and (4) A difference between outputs of a DA converter. A method that uses something with a dynamic output.

[0005] However, these methods have the following problems.

The method (1) will be described with reference to FIG. This method takes non-inverted / inverted outputs from a transformer 104 having a bipolar output connected to the output of a digital-to-analog converter (DAC) 102 and each of the amplifiers (106, 106).
108) to amplify the non-inverting terminal 110 and the inverting terminal 1
12 is a method of outputting a desired signal. In this method, since the transformer 104 does not pass a direct current, there is a lower limit in the usable frequency, and a problem occurs when a signal in which a signal having a lower frequency and a signal having a higher frequency are combined is handled.
Such a limitation is very inconvenient especially for use in testing a mixed-signal IC that has been highly sophisticated in recent years.

The method (2) is disclosed in, for example, JP-A-11-38.
As disclosed in Japanese Patent Application Laid-Open No. 086-086, this is a technique of providing an amplifier having an inverted / non-inverted differential output at the output of the pattern generator. And the accuracy of the amplitude) must be arranged in a wide band, which has a limit that cannot be ignored in performance. In particular, in a frequency region (for example, 100 MHz or more) near the operating limit of the amplifier, it is difficult to improve the inherent characteristics of the amplifier even if the circuit configuration is devised.
It is difficult to make the time equal to or less than sec. In consideration of the delay compensation method, there is no other way than to provide a delay means on the analog output line. However, in this case, as described later, the analog output signal is unavoidably distorted by the delay means. There is a problem as a method.

The method (3) will be described with reference to FIG. This method uses a high-speed large-capacity memory (206,
208) to the clock signal terminal 202.
Converter (DAC) (2) according to the clock signal from
10, 212), and the output thereof is amplified by an amplifier (214, 212).
216) is a two-channel arbitrary waveform generator (222, 224) that obtains a desired output by amplifying the data in each of the two memories (206, 208). The digital data of the signal is stored in advance. According to this method, two sets of expensive arbitrary waveform generators (222, 224) constitute a set of differential output lines, so that an expensive, high-speed, large-capacity memory (20
6, 208), and the cost is doubled. In addition, the time required to program the arbitrary waveform generator is doubled, and the waveform data for two channels must be prepared. Therefore, the time required to create the test program and the time required to load the waveform data during the actual test are reduced. Too costly.

The method (4) will be described with reference to FIG. This method uses both analog signal outputs (304, 304) from a DA converter (DAC) 302 with differential outputs.
306) are amplified by amplifiers (308, 310), respectively, to obtain respective desired analog signal outputs. In this method, since a D / A converter having no differential output cannot be used, the number of D / A converters that can be selected at the time of design is limited, and a desired performance may not be produced. In particular, many D / A converters having a differential output on the market today are not provided with a differential output, but the performance is not symmetrical and one of the output signals is inferior in quality. This is a disadvantage of this method.

In this method, the output of the two signals of the DA converter 302 is applied to each output terminal (312, 31).
The time difference generated due to the difference in cable characteristics up to 4) cannot be corrected. In this case, the DA converter 302
Output from each of the two signals (312, 31
It is conceivable to insert delay means somewhere on the cable up to 4). However, a delay line generally used as a delay means has a drawback that the characteristics of the frequency axis fluctuate when the time axis is operated, and it is very difficult to provide the delay line as a delay means capable of handling a wideband analog signal. Therefore, an effective means for compensating the time difference in this method is difficult to realize and difficult to correct.

[0011] Therefore, while being low-cost, the differential output with high accuracy and high accuracy over a wide band from DC to high frequency, or the sub-output not only limited to the differential output but also having a certain relationship with the main output. There is a need for a resulting signal generator.

[0012]

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems, to provide a low-cost, high-precision and voltage-accurate, wide-band differential output or a differential output. It is an object of the present invention to provide an arbitrary waveform generator having a secondary output having a relationship with the output.

[0013]

An arbitrary waveform generator according to an embodiment of the present invention receives a waveform data memory storing digital data of a waveform, digital data from the waveform data memory, and receives the digital data from the waveform data memory. A first DA converter for converting data into an analog signal and outputting the same, and digital data from the waveform data memory as inputs;
Code conversion means for outputting sign-inverted digital data obtained by inverting the sign of the digital data, and a second DA converter which receives the sign-inverted digital data as input, converts waveform data into an analog signal, and outputs the analog signal And the analog signals output from each of the first and second DA converters have opposite polarities.

In another embodiment, the arbitrary waveform generator comprises: a clock signal terminal for receiving a clock signal;
A first delay unit connected to the clock signal terminal and a clock input of the first DA conversion unit, for delaying the clock signal by a first delay amount and applying the delayed clock signal to the first DA converter; Second delay means connected to the clock input of the second DA conversion means for delaying the clock signal by the second delay amount and providing the delayed clock signal to the second DA converter. Connected to the clock input of

In still another embodiment, the arbitrary waveform generator is characterized in that first and second amplifiers are respectively connected to outputs of the first and second DA converters. And

In still another embodiment, in the arbitrary waveform generator, the sign inverting means includes a complement converting means for the received digital data.

In still another embodiment, in the arbitrary waveform generator, the sign inverting means includes an exclusive OR circuit.

An arbitrary waveform generator according to another embodiment of the present invention has a waveform data memory for storing digital data of a waveform, digital data from the waveform data memory as inputs, and converts the digital data into an analog signal. A first D / A converter for converting and outputting, digital data from the waveform data memory as input, data operation means for performing an operation on the digital data, and outputting the operated digital data; A second DA converter that receives the operated digital data output from the operating means, converts the digital data into an analog signal, and outputs the analog signal;
And an output signal from the output of the second DA converter.

Further, in an arbitrary waveform generator according to another embodiment of the present invention, a clock signal terminal for receiving a clock signal, the clock signal terminal and a clock input of the first DA converter are connected to each other, and the clock signal is supplied to the clock signal terminal. A first delay unit that delays the clock signal by a first delay amount and supplies the first DA converter with the clock signal terminal and a clock input of the second DA converter, and converts the clock signal into a second delay amount And second delay means for providing the delayed signal to the second DA converter, the clock signal terminal being connected to the clock input of the waveform data memory.

Further, in an arbitrary waveform generator according to another embodiment of the present invention, the data manipulating means includes a reconfigurable logic circuit.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG.
This will be described with reference to FIG. According to FIG. 1, an arbitrary waveform generator 10 having a differential output according to the present invention includes a waveform data memory 12, a sign inverting circuit 22, and a first DA converter (DA).
C) 14, second DA converter (DAC) 24, first amplifier 16 and second amplifier 26, clock signal terminal 2
0, a first delay means 30 and a second delay means 32, an output terminal 18 and an inverted output terminal 28. The waveform data stored in the waveform data memory 12 is applied to the clock signal terminal 20 and then, in accordance with the timing of the clock signal transmitted to the clock input of the waveform data memory.
The data is sequentially read as digital data having a bit width (m is a positive integer). On the non-inverted signal side, the digital data having the m-bit width is first converted from the digital data into an analog signal by the first DA converter 14. Next, the signal is amplified to a desired amplitude by the first amplifier 16 and provided to the output terminal 18 as a non-inverted signal. On the other hand, on the inversion signal side, the m-bit width digital data from the waveform data memory 12 is converted into m-bit width digital data whose sign is inverted by the sign inversion circuit 22. Thereafter, the m-bit-width digital data whose sign has been inverted is applied to a second DA converter 24, converted into an analog signal, amplified to a desired amplitude by a second amplifier 26, and inverted. Is output to Here, the first
It is preferable that the and the second DA converter have the same characteristics. In addition, the first and second DA converters adjust the timing of the clock signal applied to the clock input,
It is preferable that the timing of DA conversion can be adjusted.

The waveform data memory 12 stores digital data of a signal waveform, and may be a high-speed and large-scale memory as an example. Digital data output from the waveform data memory 12 is transmitted to the first DA converter 14 and the sign inverting circuit 22 according to the clock supplied to the clock signal terminal 22 and transmitted to the clock input of the waveform data memory. As an example, the data asserted at the output of the waveform data memory 12 at the rise of a certain clock timing t ₁ is the clock timing t _1
At the rise of ₁ + 1, the first DA converter 14 performs digital-analog conversion (DA conversion). In parallel,
The data asserted at the output of the waveform data memory 12 passes through the sign inversion circuit 22 and passes through the clock timing t _1.
The rising edge of +1 also reaches the second DA converter,
It can be configured to be converted.

The sign inverting circuit 22 processes digital data having a given m-bit width to generate digital data with an inverted sign. As an example, when the data code uses a two's complement system, the sign inverting circuit 22 includes an inverting circuit (inverter) 42 as shown in FIG.
And the adder 44. Sign inversion circuit 2
2 will be described with reference to FIG. 2A. The data input line 40 having an m-bit width is inverted by the inverter 42 and output to the adder 44. On the other hand, m-bit width digital data indicating the value 1 is supplied from a "1" data line input 46 to an adder 44, and the adder 44 outputs the digital data obtained by adding the two to an m-bit width data output. Output to line 44.

Referring to FIG. 2 (2) for a more detailed circuit diagram when m = 4 in FIG. 2 (1), the data input line 40 has data d _{0 to} d ₃ (where d ₀ is LSB and d ₃ Is MS
B), and the data output line 4
8 are output as data d' _{0 to} d' ₃ (d' ₀ is LSB and d' ₃ is MSB). The sign inversion circuit 22 is connected to the inverter 42 and the "1" data input line 4 in FIG.
6 is configured as a logic circuit unit 50 in which the adder 44 and the adder 44 are combined. The logic circuit section 50 is a carry-added 1 adder using an exclusive OR circuit. As described above, the sign inversion circuit 22 can be configured not to include the flip-flop, so that the delay can be reduced. As a result, it can be configured to operate in a time much shorter than one cycle of the clock timing. In other words, with such a configuration, the sign inversion circuit 22 can be provided as a low-cost and low-delay circuit. In FIG. 2, the same components as those in FIG. 1 are denoted by the same reference numerals, and description thereof is omitted.

The first D / A converter 14 and the second D / A converter 24 can easily match characteristics such as timing and distortion, and are D / A converters having similar characteristics or the same type. Is preferred. As an example, the first
The D / A converter 14 and the second D / A converter 24 have 500
A DA converter having a band of MHz to 1 GHz is used.

The first and second DA converters (14, 2)
Similar to the DA converter, the characteristics of the first and second amplifiers (16, 26) connected to the output of 4) are similar to each other in order to facilitate uniformity of the characteristics. It is preferable to use an amplifier or an amplifier of the same type. That is, in the prior art as disclosed in Japanese Patent Application Laid-Open No. H11-38083, a pair of amplifiers for generating signals of different polarities from the same input signal is required somewhere on the output signal line. It was difficult in principle to make the characteristics uniform. However, the first in this method
And the second amplifier (16, 26) simply require the same characteristics, so that a good match is easily obtained, and the design and selection are easy.

The first and second delay means (30, 32)
The delay amount of the clock when transmitting from the clock signal terminal 20 to the first and second DA converters (14, 24) is adjusted, and the conversion timing in each DA converter (14, 24) is adjusted. . In addition, a timing shift (skew) due to a cable from each amplifier to a DUT (device under test) can be easily corrected by these two delay means (30, 32).
With this configuration, the conversion timing of the two D / A converters (14, 24) can be adjusted, and the two D / A converters (1 and 24) can be adjusted.
Since there is no need to provide delay means on the output lines of 4, 4), distortion of the output analog signal can be reduced as compared with the conventional method. That is, as compared with the prior art disclosed in FIG. 1 of Japanese Patent Application Laid-Open No. H11-38086, in the present invention, the delay means includes an output signal line (from the first D / A converter 14 to the output terminal 18 and the second D / A conversion). Since it does not enter the inverted output terminal 28) in series from the device 24, signal distortion and phase distortion can be reduced.

Further, as shown in FIG. 6, the sign inverting circuit 22 of the present invention shown in FIG.
Various operations are performed on the data given to the main output terminal 418.
The arbitrary waveform generator 410 having the sub-output terminal 428 that can obtain the sub-output signal related to the main output signal output from the main output signal can be configured. In FIG. 6, the same reference numerals are given to the same components as those in FIG.
The operation is the same as that of FIG.

For example, by configuring the data operating means 422 to pass data signals through, it is possible to obtain an arbitrary waveform generator 410 which can obtain a main output signal for two channels with high quality. Further, by providing a configuration such as a buffer in the data operation means 422, it is possible to easily delay the signal, so that it is possible to obtain an arbitrary waveform generator 410 provided with a function of delaying the sub-output signal by a predetermined amount. . Further, this data operation means 422 is
By configuring the data signal to be processed by various bit operations, for example, an arbitrary waveform generator 410 that masks one or more bits of data or generates a rearranged sub-output signal is obtained. You can also.

The data operation means 422 as described above
By including a logic element that can be easily reconfigured such as a PGA (field programmable gate array) or a circuit including the logic element, it is easy to change or switch the function of the data operation means, and according to the application. It can be flexibly supported.

[0031]

As described above, according to the first embodiment of the present invention, the data inverted by the sign inverting means is sent to the second DA converter. Can be used. Therefore, the timing accuracy and the voltage accuracy of the differential output can be easily and highly matched.

According to the embodiment of the present invention, since the clock timing of each DA converter is adjusted by the delay means, the signal of the output signal line is not deteriorated and the DA conversion is performed. It can also absorb the timing shift due to the cable from the container to the end. Therefore, a differential output with excellent timing accuracy can be provided.

According to the third aspect of the present invention, since each amplifier can be of the same type due to its configuration, it is easy to match the characteristics of both signal lines. Therefore, a differential output with excellent timing accuracy and voltage accuracy can be provided.

According to the fourth and fifth embodiments of the present invention, the sign inverting means can easily generate the sign-inverted data, and provide the differential output with small delay and low cost. Can be. As a result, it is also effective in increasing the speed of the arbitrary waveform generator.

According to the embodiments of the present invention, various output signals not limited to the differential output can be easily obtained by the data operation means, so that the test can be performed flexibly. Can be.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a preferred embodiment of the present invention.

FIG. 2 is a block diagram illustrating a sign inversion circuit in FIG. 1;

FIG. 3 is a block diagram illustrating a differential output using a conventional transformer.

FIG. 4 is a block diagram illustrating a differential output in which generators for two channels according to the related art are linked.

FIG. 5 is a block diagram illustrating a differential output using a DA converter having a differential output according to the related art.

FIG. 6 is a block diagram illustrating another embodiment of the present invention.

[Explanation of symbols]

 10: Arbitrary waveform generator 12: Waveform data memory 14, 24: DA converter 16, 26: Amplifier 18: Output terminal 20: Clock signal terminal 22: Sign inverting circuit 28: Inverted output terminal 30, 32: Delay means 40: Data input line 42: Inverter 44: Adder 46: "1" data input line 48: Data output line 50: Logic circuit section 52, 54, 56, 58: Inverted logic element 60: Inverted logic element 62, 66, 70: Exclusive OR elements 64, 68: OR element 410: Arbitrary waveform generator 418: Main output terminal 422: Data operating means 428: Sub output terminal

Claims (8)

[Claims] A first digital-to-analog (D / A) converter that receives the digital data from the waveform data memory, converts the digital data into an analog signal, and outputs the analog signal; A signal conversion means for inputting the digital data from the waveform data memory and outputting sign-inverted digital data obtained by inverting the sign of the digital data; and A second DA converter that converts the waveform data into an analog signal and outputs the analog signal, wherein the analog signals output from each of the first and second DA converters have opposite polarities. Arbitrary waveform generator. A clock signal terminal for receiving a clock signal; a clock signal terminal connected to the clock signal terminal and a clock input of the first DA converter; and a clock signal for delaying the clock signal by a first delay amount. A first delay unit for providing the first DA converter; a clock signal terminal connected to a clock input of the second DA converter; and a second delay unit for delaying the clock signal by a second delay amount. 2. The arbitrary waveform generator according to claim 1, further comprising: a second delay unit that supplies the clock signal terminal to a clock input of the waveform data memory. 3. 3. The arbitrary waveform according to claim 1, wherein a first amplifier and a second amplifier are connected to outputs of the first and second DA converters, respectively. Generator. 4. The arbitrary waveform generator according to claim 1, wherein said sign inverting means includes a complement converting means for the received digital data. 5. The arbitrary waveform generator according to claim 1, wherein said sign inverting means has an exclusive OR circuit. 6. A first DA converter for receiving a waveform data memory storing digital data of a waveform, inputting the digital data from the waveform data memory, converting the digital data into an analog signal, and outputting the analog signal. A data operation means for receiving the digital data from the waveform data memory as input, applying an operation to the digital data, and outputting the operated digital data; and the operation output from the data operation means And a second D / A converter for converting the converted digital data into an input, converting the converted data into an analog signal, and outputting the analog signal, and generating an output signal from each of the outputs of the first and second D / A converters. . 7. A clock signal terminal for receiving a clock signal, the clock signal terminal being connected to a clock input of the first DA converter, and a clock signal terminal for delaying the clock signal by a first delay amount. A first delay unit for providing the first DA converter; a clock signal terminal connected to a clock input of the second DA converter; and a second delay unit for delaying the clock signal by a second delay amount. 7. The arbitrary waveform generator according to claim 6, further comprising a second delay unit that supplies the clock signal terminal to a clock input of the waveform data memory. 8. The arbitrary waveform generator according to claim 6, wherein said data operation means has a reconfigurable logic circuit.