JPH0362733A - D/a converter - Google Patents

Abstract

PURPOSE:To realize a D/A converter in which distortion is hardly produced by subtracting a value resulting from D/A-converting an inverted digital data from a value resulting from D/A-converting an input digital data. CONSTITUTION:A 1st D/A converter 12 D/A-converts an audio sample data according to a bit clock BK received from a digital filter 10 and a latch enable signal LE and outputs the result as a 1st analog signal LA1 of an L channel. A 2nd D/A converter 11 operated in 4Fs connects to an output of an inverting circuit 14 and D/A-converts an inverted audio sample data according to the bit clock BK received from the digital filter 10 and the latch enable signal LE and outputs the result as a 2nd analog signal LA2 of an L channel. A summing amplifier 18 subtracts the 2nd analog signal LA2 from the 1st analog signal LA1 and the result is outputted as an L-channel analog audio signal LA without any distortion.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a D/A converter, and particularly to a D/A converter with improved distortion factor.

[Conventional technology]

For example, a D/A converter is connected to the output side of the digital filter of a CD player, and a 175-shaku 2C11
The audio line non-purple data strings are D/A converted to form analog audio signals for L and RZ channels.

[Problem to be solved by the invention]

However, in conventional 1)/A converters, for example, when sine wave digital data is manually input, distortion occurs inside the 1)/A converter, and the output is output as an analog signal containing harmonic distortion components. .

For this reason, for example, in Audionste J, (,!,1)
There was a drawback that the sound quality deteriorated when changing to /A.

This invention was made in view of the above-mentioned conventional problems.
Our goal is to provide a D/A converter that is less prone to distortion.

In addition, reducing the cost burden is defined as ``first objective.''

[Means to solve the problem]

The D/A conversion device of the present invention includes an inverting means for inverting human-powered digital data to create inverted digital data, and a first D/A converter for D/A converting input digital data.
/A conversion means, second D/A conversion means for D/A converting the inverted digital data, subtraction means for calculating the difference between the output of the first D/A conversion means and the output of the first r)/A conversion means;
It is characterized by the following.

Further, another D/A conversion device of the present invention includes selective inverting means for inverting manual digital data every other time, and non-inverted digital data outputting every other digital data outputted from the selective inverting means. The data and the inverted data output every other time are separately D/A converted. A D/A conversion means outputs as a second output signal, and a first output signal output from the D/A conversion means. The present invention is characterized by comprising a subtraction means for calculating a difference between the second output signals.

Further, still another D/A conversion device of the present invention includes a data distribution means for distributing human-powered digital data into two systems every other time, and a data distribution means for distributing the data into two systems, and a data distribution &J means for outputting data from the -. 1st D to convert data to D/A
/A converting means, inverting means for inverting the data of the other system output from the data distribution & no means, and 21st) for converting the data output from the inverting means into D/A.
It is characterized in that it has 6i & f stages of A conversion and subtraction means for determining the difference between the outputs of the first D/A conversion means and the eleventh D/A conversion means.

〔Example〕

Next, a first embodiment of the present invention will be described with reference to diagram m1.

FIG. 1 is a block diagram showing a D/A conversion device for a CD player according to the present invention.

1 output from the digital signal processing circuit (not shown)
1. The Rch audio sample data (sampling frequency Fs) is oversampled by 4 times by the digital filter 10 to 4Fs, and the Rch-specific audio sample data L-D is obtained.

It is output as RD from the LO and RO terminals separately.

These audio sample data LD and RD are data strings of serial unit data L D1. L l) 2
゜LD 3. ......, RD,, RD 2.
It consists of RD,... (see Figure 2).

Further, a bit clock BK is output from the BK terminal of the digital filter 10, and a latch enable signal +-E is output from the LE terminal every time one unit of audio sample data LD, RD is output.

The LO terminal of the digital filter 10 is divided into two systems, one of which is directly connected to the first D/A converter 12 that operates at 4Fs.

This first D/A converter 12 includes a digital filter 10
According to the bit clock BK and the latch enable signal LE which are manually inputted from the converter, the audio sample data LD as input digital data is D/A converted and outputted as the Lch first analog signal LA.

Further, an inverting circuit 14 is connected to the other system of the LO terminal of the digital filter 10, and the audio sample data LD is inverted and converted into an inverted audio sample data Ll as inverted digital data (serial unit data string 1- D,, 1.,, D,,...
・It is output as "Karawari".

On the output side of the inversion circuit 14, there is a second D/A that operates at 4Fs.
A converter 16 is connected, and a digital filter 10
According to the input Pino I. Cronk [3K] and the latch enable signal LB, the inverted audio sample data ``1,000'' is D/A converted and output as the second analog signal LA of 1., ch.

The first T)/A converter 12 and the second r)/A converter 16 are
Kamiyari's same D/A weird t? ! The distortion characteristics are also the same.

The non-inverting input terminal (+) and the inverting input terminal (-) of the summing amplifier 18 are connected to the output side of the first D/A converter 12 and the output side of the first D/A converter ■6. , 1st
The second analog signal RI82 is subtracted from the analog signal LA, and is output as the Lch analog audio signal 2,8.

In exactly the same way on the Rch side, the RO terminal of the digital filter 10 is divided into two systems, one of which is directly connected to the first
The other side is connected to the D/A converter 20, and the other side is connected to the second D/A converter 24 via the inverting circuit 22. , converts the audio sample data RD and the inverted audio sample data RD into D/A, and converts the first analog signal RA1.
It is output as a second analog signal RAz.

Then, the first D/A converter 20 and the second D/A converter 24
The output side of is the non-inverting input input terminal of the summing amplifier 26 (
→-) and an inverting input terminal (-), and the second analog signal RA is subtracted from the first analog signal RA+ and output as an Rch analog audio signal RA.

Next, the operation of this embodiment will be explained with reference to the time chart of FIG.

Note that only the Lch will be explained here.

4Fs L c output from digital filter IO
h audio sample data 1. D is divided into two systems, one of which is directly input to the first D/A converter 12 for D/A conversion, and output as the first analog signal L A .

This first analog signal 1-A+ has the same signal polarity as the original audio sample data LD, and
It contains distortion components generated inside the D/A converter 12.

On the other hand, in the other output system of the audio ripple data LD of the digital filter 10, the polarity is first inverted by the inverting circuit I4 to create inverted audio sample data ``Mourning''.

And this inverted audio sample data 1. ! ] is D/A converted by the second D/A converter 16 and output as a second analog signal LA.

The signal polarity of this second analog signal 1-Az is the same as that of the first
It is opposite to the analog signal L A z, and the second D/
It contains distortion components generated inside the A-variant FIA device 16.

In the summing amplifier 18, the first analog signal LA
, the second analog signal 1-A2 is calculated by '/J&.

At this time, since the signal polarities of the first analog signal l-8 and the 27th analog signal LAz are opposite, the signal amplitude becomes twice as large, and the distortion components and the 2 analog signal LA.

Among the distortion components on the , the in-phase component is canceled out, so
The summing amplifier 18 outputs an Lch analog audio signal LA whose distortion components are suppressed relative to the signal components.
is output.

The same holds true for Rch.

According to this embodiment, the audio sample data LD (
RD) as it is to D with the 1st +)/halo exchanger 12 (20)
A first analog signal LA (RA, ) which has been subjected to /A conversion, and a second analog signal LA which has been inverted and then D/A converted by the second D/A converter 16 (24).

(RA, ) is subtracted by the summing amplifier 1B (26), so the signal amplitude from the summing amplifier 1B (26) is doubled, and each of the first D/A converter 12 (20) and the second D/A converter 12 (20),
/A converter +6 L (R) channel analog audio signal LA in which the in-phase component of the distortion component generated by (24) is canceled.
(RA) is output, and a D/A converter with less distortion can be obtained.

Next, a second embodiment of the present invention will be described based on FIG.

FIG. 3 is a block diagram showing 1)/A conversion device of a CD player according to the present invention.

The Rch audio ripple data (sampling frequency Fs) outputted from a digital signal processing circuit (not shown) is oversampled by 4 times by the digital filter 10 to 4Fs, and the Rch-specific audio sample data L D1? D and is output separately from the O terminal and the RO terminal.

These audio sample data I-1,) RD
is a data string L D +, L of serial unit data
D 2゜L D 3. ......,RD,,RD
2. ...... (see Figure 4).

Further, a focus clock BK is output from the digital filter Iom B+< terminal, and a latch enable signal LF is output from the I4E terminal every time one unit of audio sample data LD, RD is output.

The LO terminal of the digital filter 10 is connected to a selection inverting circuit 30 consisting of an exclusive OR circuit, and every other intermediate data of the audio sample data LD is inverted and output.

One input terminal of this selection inversion circuit 30 is connected to the LO terminal of the digital filter 10.

Further, the first timing signal TE is input from the timing circuit 32 to the other input terminal of the selection inversion circuit 30.

This timing circuit 32 is connected to the digital filter 1 (
Launch enable signal input from l - IE to 1/
The latch enable signal LE is inverted and output as a second sample clock S2.

Therefore, the selection inversion circuit 30 outputs the first quiring signal TE to the audio sample data LD shown in FIG.
is the odd-numbered unit data L
D +, L D 3. L D 5. .
,, l-1) ,,.

. . . is output without being inverted.

On the output side of the selection inversion circuit 30, there is a D/D that operates at 2Fs.
An A converter 34 is connected, and the digital data output from the selection inversion circuit 30 is converted into I/A.

This D/A converter 34 has two output terminals 0102, and the digital filter 10 outputs the input signal manually from the digital filter 10.
- According to the clock BK and the latch enable signal LE, among the data manually inputted from the selection inversion circuit 30, the inversion unit data L D , LD 1. L D 5゜・・・
... is D/A converted at 2Fs, and the second
Of the data output as the analog signal LB2 and manually input from the selection inversion circuit 12, unit data L D 2.
L D ,, L D 6. =-・-D at 2Fs
/A, the first analog signal L■ from output terminal 01
Output as 3I.

Here, the second analog signal LB2 changes when each intermediate data is completed, and the first analog signal LB changes when each unit data LD2LD, LD6 . . . . will change when the I' rough amount of human effort is completed.

On the output side of output terminals 01 and 02 of the D/A converter 34,
Sample and hold circuits 36 and 38 are connected to each of them, and the first analog signal LB is sampled and held in accordance with the second sample clock S2 outputted from the timing circuit 32 to remove glitches, and the first analog signal LC, is formed.

Also, the second analog signal LB is sampled and held according to the first sample clock S1 to remove glitches and form the second analog signal LC2.

D/A converter 34, sample/hold circuit 36.38
A D/A converting means 39 is constructed.

The output sides of the sample and hold circuits 36 and 38 are connected to the non-inverting input terminal (+) and 9 inverting input terminal (-) of the summing amplifier 40.
) from the first analog signal LC, to the second analog signal LC,
The analog signal LC2 is calculated and output as the Lch analog audio signal LC.

The Rch side is configured in exactly the same way, and a selection inverting circuit 42, which is an Illll logical OR circuit, is connected to the RO terminal of the digital filter 10, and a timing signal TE manually generated from the timing circuit 32 is connected to the selection inverting circuit 42, which is an Illll logical OR circuit. An exclusive OR of the audio sample data RD is taken,
Digital data in which every other unit data is inverted is output.

On the output side of the selection inversion circuit 42, there is a D/A that operates at 2Fs.
Converter/14 is connected, iP+sawa inversion circuit 42
The digital data output from the converter is D/A converted.

This D/A converter 44 has two output terminals 0102, and according to the pit clock BK and latch enable signal LIE manually inputted from the digital filter 10,
The inversion unit Q';' I? l) ,, Rl) 3. R.D.
.

Convert to D/A at 2 Fs (, output terminal 4
02 as the second analog signal RB 2, and of the data input from the selection inverting circuit 42, the unit data RD 2. RD,, RD6.・・・・・・2
It is D/A converted by Fs and outputted as the first analog signal RB1 from the output terminal 01.

On the output side of output terminals 01 and 02 of the D/A converter 44,
Sample and hold circuits 46 and 48 are connected,
The first analog signal RB is sampled and held according to the second sample clock S2 output from the timing circuit 32 to remove glitches, and the first analog signal R
C+ is formed.

Also, the second analog signal RB, is sampled and held according to the first sample clock S1 to remove glitches and form the second analog signal RC.

D/A converter 44 and sample/hold circuit 4648 constitute D/A conversion means 49.

The output sides of the sample and hold circuits 46 and 48 are connected to the non-inverting input terminal (+) and the inverting column terminal (-) of the ξ puffer amplifier 50, and are connected to the second analog signal RC2 to the first analog signal RC, is subtracted, Rc
h is output as an analog audio signal RC.

Next, the operation of this embodiment will be explained with reference to the chart in FIG.

Note that only Lch will be explained here.

Lc of 4 Fs output from the digital filter 10
The audio sample data LD of h is inputted to the selection inversion circuit 30, and the width (i7 data) is output while being inverted every other one.

The digital data output from the selection inversion circuit 30 is
Inputted to the D/A converter 34, the inverted data L D , ,
L D 3. L D 1. ...... are in order on the 2nd floor.
The second analog signal LB2 is subjected to D/A conversion at step s, and further sampled and held at a sample and hold circuit 38 to remove glitches.

Also, among the digital data output from the selection inversion circuit 30, unit data L D2. l-1) 4. I
-T) 6° .

The first analog signal LC, output from the sample-and-hold circuit 36 is inverted unit data L D .

L D s, L D? The second analog signal L Ct that changes at the end of one word of , . It changes at the end of the l word.

The first analog signal LC has the same signal polarity as the original audio sample data LD, and the D/A converter 3
Contains distortion components generated inside 4.

Further, the second analog signal L C2 has the opposite signal polarity to the original audio sample data LD, and the D/A
It contains distortion components generated inside the converter 34.

In the zaming amplifier 40, the first analog signal LC,
to the second analog signal 1. ．． C, is subtracted.

At this time, the first analog signal LC: + and the second analog signal 1. ．． Since the signal polarities of C and C are opposite, the signal amplitude is doubled, and the distortion components on the first analog signal L C1 and the distortion components on the second analog signal C2 are in phase. Since the components are canceled out, the summing amplifier 40 outputs an L c b analog audio signal LC in which the distortion component is suppressed relative to the signal component.

The same holds true for Rch.

According to this embodiment, audio sample data LD (R
After the unit data of D) is inverted every other unit by the selection inversion circuit 30 (42), the D/A converter 34 (44) converts the inverted unit data "old, r million] L D Sv...・(R
Dl, RD,, RD5. ) and unit data L D ,, L D ,, L D 6.・・・・・・
・l D2. RIL, rlD b, ...), the second analog signal LB2 (
RB2) and the first analog signal LB, (RB,), the sample and hold circuit 36.38 (/16
．． 48) to remove the glitch, and the summing amplifier 40 (50) subtracted the second analog signal LC2 from the first analog signal LC.
The signal amplitude is doubled from the summing amplifier 40 (50), and the L (R) channel analog audio signal L has the in-phase component of the distortion component generated by the D/A converter 34 (44) canceled.
C (RC) will be output, resulting in a D/A with less distortion.
A conversion device is obtained.

Also, the first analog signal LC, and the second analog signal L
Since the change timing of Cz is shifted by 1/2 cycle, the analog audio signal LC output from the summing amplifier 40 (50) is the same as that obtained by D/A converting the audio sample data LD (RD) at 4Fs. They are equivalent, and the operating frequency of the D/A converter 34 (44) can be half that of the digital filter 10, which is advantageous in terms of cost.

In addition, the first analog signal LC+ (RC+) and the second
The first and second sample clocks S1. S2 component is rimming amplifier 40
Since it is canceled by the subtraction by (50), the analog audio signal 0 1, c (r?c) with less noise is HHI.

Next, a third embodiment of the present invention will be described with reference to FIG. 5.

FIG. 5 is a diagram showing a D/A converter for a CD player according to the present invention without showing it.

The Rch audio sample data (sampling frequency Fs) output from a digital signal processing circuit (not shown) is oversampled by a factor of 4 using the digital filter ■0, and is oversampled by a factor of 1 of ζ4Fs. , , Rch-specific audio sample data 1, 1) rl D is output separately from the LO terminal and the RO terminal.

These audio sample data 1. ．． D, l? D is a data string of serial unit data L D , LD
2゜..., rl D,, RD 2.・・・
. . . and output (see Figure 6).

In addition, one bit clock I3K is output from the I'3K terminal r- of the digital filter I0, and one audio sample data L D, I is output from the L T? terminal.
? D is 1! ``Latch enable signal 1-1'' every time one piece of p17 data is output.

is output.

A multiplexer 5■ is connected to the LO terminal and RO terminal of the digital filter 10, and every other data is taken out from the audio sample data LD and RD, and Lch and Rch are arranged at alternating pressure. Two systems of digital data are output.

This multiplexer 5I outputs the unit data from the output terminal K2 of the second system for the audio sample data LD and RD of FIG. Columns LD,, RD,, LD,.

RD 3. L D 5. RD 5. . . . and unit data string L from 1 to the output terminal of the first system.
D,,RD,,LD,.

RD 4. L D 6. RD6. Outputs...

That is, even-numbered unit data 1, D2 . , r? 1
) in (n: integer), unit data RD2. ．． -1. Outputs unit data RD Z-2 from 1 to the output terminal, and outputs odd numbered unit data L
While inputting D, □, , RD2□1 manually, unit data L l) in -1 is output from the output terminal K 2 , and unit data L D , , is output from the output terminal K ].

Therefore, when IJ arrives at L Ch, the audio sample data LD in FIG.
...and even number 11 unit data L D ,, L
D4. L l) , , ......, and if we pay attention to Rch, we will see the audio sample data Rl) in Figure 6, and the order number 110) (i'j
(i7 Dake RD +, RD 3. RD s...
... Even numbered middle data RD 2. R.D.
RD,... J et al. 41. is output.

2 to the output terminal of the multi-player clear '51 is 11.];
A circuit 52 is connected to which the digital data output from 2 to the output terminal is inverted.

Therefore, the inverse +1 transmission digital data output from the inverting circuit 52 is L D +, l? D+, L-1)
x, RD 1. It becomes...

A second D/A converter 54 is connected to the output side of the inverting circuit 52, and according to the input signal from the digital filter 10 and the output signal I, Inverted digital data 1. (.

11 and Rch, 2Fs, I-1),, L
l) 3. L D7. . . . are sequentially D/A converted and the second analog signal L J 2 is output from the output terminal 1-0.
At the same time as outputting RD ,, RD 3 in 2FS
．． RD 5. . . . are converted into D/A in order and a second analog signal RJ is output from the output terminal RO.

Here, the second analog signal L J 2 is each inverted iIt data LD, LD, LL)5. The second analog signal RJ2 changes when the human power of 1 hour and 11 minutes is completed, and the second analog signal RJ2 becomes each inverted unit data RD , , RD , ,
RD 5.・ = −。。。。。。。。。。。。。。。。。。。。。。

In addition, the output terminal K related to the first system of the multiplexer 5I
A first D/A converter 56 as the (r)/halo conversion means is connected to I, and according to the bit clock BK input from the digital filter 10 and the latch enable signal LE, the signal is output from 1 to the output terminal. The digital data to +-c b and Rch are 2Fs, L D
2.1. , D 4+ t, D 6. -.
So, l? 1) ,,RD,,I'? D...
. . . in one song, the first analog signal R, 1 is output from the output terminal RO.

Here, the first analog signals L , J , and each unit data L D 2 . L D ,, L D 6.・・・・・・
・Changes when one sort-minute of manpower is completed, and the first
Analog [1] signal RJ is each rotation unit data RD,, Rl
),, l? 1. ) , , , . . . will change when one word worth of input is completed.

Therefore, the first analog signal L,1 and the second analog signal 11
The analog signal L J z changes at the same time, and the second analog signal R
J + and the second analog signal RJ2 change simultaneously.

The output terminals 1-0 and RO of the 11th)/A converter 56 have
Each sample/halt circuit 58.6 (l) is connected, and according to the timing 1 (■ 1 path 62), the first analog I:I signal LJ is
, and RJ, are delayed by 1/2 round 1 to form delayed first analog signals LJ, ``and RJl°.

1st +) / Halo Exchanger 56, Rimple Holded 1st Road 5
8.60 constitutes the 11th)/A conversion means.

The timing circuit 62 divides the latch enable signal LE input from the digital filter IO by 2/2 to form a sample clock SK.

The output terminal LO of the 20th/A converter 54 and the 4J sample
The output side of the hold circuit 58 is connected to the inverting input terminal (-) and the non-inverting input terminal (-1-) of the zaming amplifier 64, and is connected to the delayed first analog signal 1, Jl'' to the second analog signal L, J, is subtracted and L c h
IL is output as an analog audio signal LJ.

The Rc 11 side is configured in exactly the same way, and the output terminal RO of the second D/A converter 54 and the output side of the sample-and-hold circuit 60 are connected to the inverting input terminal (-) of the amplifier 66, the non-inverting input terminal It is connected to the input terminal (1-), and the second analog signal R,1 is subtracted from the delayed first analog audio signal RJ, and is output as the Rckl analog audio signal RJ.

Next, the operation of this embodiment will be explained with reference to time chart 1- in FIG.

In addition, here I will discuss only theory I regarding L c h! II.

L c of 4Fs output from the digital filter 10
h and Rch audio sample data 1-D and T?
D is a multiplexer 5I that rearranges the data and outputs unit data strings L D , R
D,,LD,,RD3. L l) ,,
L D 5. ... is output, and the output terminal changes from 1 to L.
l) ,, RD 2. LD,, R1),
, L l) , L D , . . . are output.

In addition, in this embodiment, from the multiplexer 51, L D
, and LD2, RD, and RD2, LD1 and ■.

■] 4, . . . are output at the same time.

The digital data outputted from the output terminal K2 of the multiplexer 51 is inverted by the inverting circuit 52, and then converted into inverted digital data and inputted to the ζ21)/A converter 54, which converts the data into 2Fs separately from Lc I+ and Rch. So, l-
D,, L-D,, I-D,, . . . are sequentially D/A converted and output as the second analog signal "QLJ2" from the output terminal LO, and at 2Fs, RD 1.RL),.

7 RD , .

With respect to the audio sample data LD, the second analog signal LJ has the opposite signal pole 11゛, and the 21st
)/A converter 54, distortion components generated inside the converter 54 are superimposed.

In addition, the digital data output from the output terminal KI of the multi-break 4J51 is inputted to the first D/A converter 56, and is input to the Lch and Rcb separately at 2Fs.
,, 1. .
D2. RD,,RDb,... are sequentially D/A converted and output from the output terminal RO to the first analog signal R.
It is output as J.

The first analog signal L J + has the same signal polarity as the audio sample data L D, and the first
The distortion components multiplied inside the D/A converter 56 are superimposed.

21) Second analog signal output from the /A converter 54 1. J2 is the unit data input to the 21st)/A converter 54 by human power.
,...(7) Changes at the end of the l word and becomes -1
Delay 1st output from J pull pole 1 - circuit 5th
Analog signal 14. J" is the middle expansion data RD,,RD:+,rl inputted to the second D/A converter 54
+) ,... changes at the end of the I word.

In the summing amplifier 64, the delay first Arno'r:1
from the second analog cog signal LJ, “to the second analog cog signal LJ2
is subtracted.

At this time, since the signal polarities of the delayed first analog signal LJ, ° and the second analog signal LJ are opposite, the signal amplitude is doubled, and each delayed first analog signal LJ, The distortion component on LJ,' and the second analog signal L
Since the in-phase component among the distortion components on J, is canceled out, the summing amplifier 64 outputs an analog audio signal LJ of 1,,c I+ in which the distortion component is suppressed relative to the signal component. be done.

The same holds true for Rch.

According to this embodiment, audio'rimple data LD
After the unit data of (RD) is divided into two systems of digital data by a multiplexer 51 and divided into two systems, the digital data of one system is inverted by an inverting circuit 52 and further converted into a second D/A conversion D/A conversion. to form the second analog signal Jz (R, J2), and also to form the first D/
A converter 56 converts unit data LD2. LD,,LD,,
・・・・・(RD 2. RD ,, RD ,,・
...) are sequentially D/A converted at 2Fs to obtain the first analog signal y, 1. , +1 (+? J+), and furthermore, a first analog signal 1. ．． J, (RJ,) is sampled and held by the sample and hold circuit 58 (60) and delayed by 1/2 period to obtain a delayed first analog signal LJ,
° (RJ, °) and further delayed by the summing amplifier 64 (66), the first analog signal L J +
"(RJI') to the second analog signal LJ, (R
J,), the summing amplifier 64 (66)
From then on, the signal amplitude is doubled, and the in-phase component of the distortion component generated by the 20th/A converter 54 and the first D/A converter 56 is canceled out. ．．
．． J (RJ) will be output, and a D/A converter with less distortion can be obtained.

Furthermore, since the change point of the delayed 17th analog signal LJ,' such as the second analog signal 1-, J2 is delayed by 1/2 period, the analog audio signal LJ output from the zaming amplifier 64 (66) is , the audio sample data Ll)(I?D) is D/A converted in 411s, and the second D/A converter 54. 1st D/
The operating frequency of the A converter 56 can be half that of the digital filter 10, which is advantageous in terms of cost.

In the example of FIG. 5, if the Kl output (iljl) of the multiplexer 4J is delayed by 1/2 cycle LJ, the sample/hold circuit 58 (60) becomes unnecessary.

〔Effect of the invention〕

According to the D/A converter of the present invention, the inverting means for inverting input digital data to create inverted digital data, the 1f)/A converting means for converting input digital data into D1/A, and the inverted digital data. a second D/A conversion means for D/A converting the first
and subtraction means for calculating the difference between the output of the D/A conversion means and the output of the second D/A conversion means.
Since the distortion component produced by the conversion means can be canceled out by the in-phase component by the distortion component produced by the second +)/A conversion means, it is possible to reduce the distortion factor.

Further, another D/A conversion device of the present invention includes selective inverting means for inverting manual digital data every other data, and non-inverting digital data output for every other digital data outputted from the selective inverting means. The data and the inverted data output every other data are separately D/A converted and converted into the first data. D/A converting means outputs as second output No. 13, and first output No. 13 outputs from the D/A converting means. and a subtraction means for obtaining a difference between the second output signals, the distortion component generated by the D/A conversion means and superimposed on the first output signal is generated by the D/A conversion means and the second output signal is generated by the D/A conversion means. The in-phase component can be canceled out by the distortion component on the output signal, reducing the distortion factor, and the operating frequency of the D/A conversion means can be reduced to 1/2/1IF2, which is 1/2 of the sampling frequency of the human-powered digital data.
:T, because it is possible to use inexpensive D/A conversion means.
This will reduce the burden of strikes.

Further, still another D/A conversion device of the present invention includes a data distribution means for distributing human-powered digital data into two systems every other data, and a digital data distribution system for one system outputted from the data distribution means. A first D/A conversion means for D/A converting data, an inversion means for inverting the data of the other system output from the data distribution means, and a first D/A conversion means for converting the data into D/A, and an inversion means for inverting the data of the other system output from the data distribution means;
/A conversion means, and subtraction means for calculating the difference between the outputs of the first +)/A conversion means and the second D/A conversion means. The distortion component produced by the second D/A conversion means can cancel out the in-phase component, and the distortion rate can be reduced, and the D
/ The operating frequency of the A conversion means is only I/2 of the sampling frequency of human-powered digital data, making it an inexpensive D/
Since A conversion means can be used, there is less increase in cost burden.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a D/A converter according to a first embodiment of the present invention, and FIG. 2 is a time chart illustrating the operation of FIG. 1. A block diagram of the D/A converter according to the second embodiment, FIG. 4 is a time chart 1 for explaining the operation of FIG. 3, and FIG.
FIG. 6 is a block diagram of the D/A converter according to the embodiment, and FIG. 6 is a time chart explaining the operation of FIG. Explanation of main symbols 12゜14゜16゜18゜0 22゜24゜26゜56: 1st D/A converter, 52: Inverting circuit, 54: 2nd D/A converter, 40.50.6/1 .66: Summing amplifier, 30. /12: selection inversion circuit, 39.49: D/A conversion means, 51: multiplexer.

Claims (3)

[Claims] (1) Inverting means for inverting input digital data to create inverted digital data; first D/A converting means for D/A converting the input digital data; and second D/A converting means for D/A converting the inverted digital data. A D/A conversion device comprising: A conversion means; and subtraction means for determining the difference between the output of the first D/A conversion means and the output of the second D/A conversion means. (2) Selective inverting means for inverting every other input digital data; and one of the digital data output from the selective inverting means.
The non-inverted data that is output every other time and the inverted data that is output every other are separately D/A converted to the first and second data.
A D/A converter comprising: a D/A converter that outputs an output signal as an output signal; and a subtracter that calculates the difference between the first and second output signals output from the D/A converter. conversion device. (3) a data distribution means for distributing every other input digital data into two systems; and a first D/A conversion means for D/A converting the data of one system outputted from the data distribution means; an inverting means for inverting the data of the other system output from the data distribution means; and a second D for D/A converting the data output from the inverting means.
A D/A conversion device comprising: /A conversion means; and subtraction means for determining the difference between the outputs of the first D/A conversion means and the second D/A conversion means.