JPS6315532A - D/a converter response test device - Google Patents

Abstract

PURPOSE:To attain the dynamic response test of the D/A converter of a high speed conversion with a comparatively simple constitution by constituting the titled device by a pattern data generator, a comparator comparing a reference voltage with an analog signal converted by a test object D/A converter and a latch circuit holding a discrepancy output of the comparator. CONSTITUTION:A digital pattern data D2 is outputted from a pattern data generator 1 together with a digital pattern data D1 fed to a D/A converter 2, and a prescribed voltage Vr and the full scale output level of the D/A converter 2 are compared by a comparator 3 at a period when the data D2 is at an H level. A latch circuit 7 does not latch a compared output data while regarding that the two signals are coincident when the level of an output signal AS of the converter 2 exceeds the level of the reference voltage Vr, but latches a comparison output data while regarding that the two signals are coincident when the level of the A/S does not reach the level of the Vr. That is, the latch circuit 7 holds the detection signal as the result of malfunction of the D/A converter 2 and it is not required to discriminate the result of comparison of the comparator at every period different from a conventional device.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a D/A converter response test device, and more specifically, to a device suitable for a high-speed D/A converter response test. It is something to leap into.

(Prior Art) FIG. 3 is a block diagram showing an example of a device for testing the response characteristics of a conventional D/A converter. In Figure 3, 1
3 is a pattern generator that generates digital pattern data, and generates digital pattern data D to be added to the pressed (iIjO/A converter (hereinafter referred to as a D/A converter) 2. 3 is a pattern generator that generates digital pattern data. The analog signal AS converted and output from the reference voltage generator 4 and the reference voltage vr output from the reference voltage generator 4
It is a comparator that compares the
It is bolded by 0 and 5. Reference numeral 6 denotes a timing signal generator that outputs timing signals for controlling the operations of each section. That is, the pattern generator 1 generates digital pattern data D according to the timing signal TSo applied from the timing signal generator 6, and the D/A converter 2 generates the digital pattern according to the timing signal TS applied from the timing signal generator 6. The data D+ is converted into an analog signal As, and the flip-flop 5 receives the timing signal T applied from the timing 1j generator 6.
According to S2, the output of comparator 3 at that point in time is held.

FIG. 4 is an imming chart for explaining the operation of FIG. 3. At 1 in Figure 4, (a)
indicates digital pattern data D output from the pattern generator 1 to the D/A converter 2; for example, D
Data X corresponding to the full-scale input of the /A converter 2 and data X' corresponding to the zero input are alternately output in each cycle. These respective data X, X= are applied to the D/A converter 2 from the timing signal generator 6 according to the timing signal T S + shown in (1)).
A predetermined time Tl from the rising edge of S+! Exactly, the D/A converter 2 converts the analog signal A'S as shown in (C) into 9.
will be replaced. This analog signal S is compared with a reference voltage vr outputted from a normal voltage generator 4 by a comparator 3.

The output signal of the comparator 3 is successively held in the flip 70 tube 5 in accordance with the timing signal TS2 shown in FIG. 3(d) applied from the timing signal generator 6. This results in
The output F3 OUT of the flip 70 tube 5 changes every timing signal T S 2 as shown in (e).

(Problem to be solved by the invention) However, according to such a configuration, the flip-flop 5
Since the output signal Q OUT changes to the timing signal TStFJ, it is necessary to constantly monitor the output signal 0tJT of the flip-flop 5 at each timing, and perform a characteristic test of high-speed conversion operation. That is difficult.

The present invention has been made with attention to these points, and its purpose is to provide an 8i system that can perform dynamic response tests of D/A converters that perform high-speed conversion with a relatively simple configuration! It is to serve the purpose.

(Means for Solving the Problems) The present invention, which achieves the above object, includes a pattern data generator that generates digital pattern data to be added to a converter to a D/A converter to be tested, and a D/A converter to be tested. It is characterized by comprising a comparator that compares the analog signal converted by the converter with a reference voltage, and a latch circuit that holds the mismatched output of the comparator.

(Example) Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention, and the same parts as in FIG. 3 are given the same reference numerals. In FIG. 1, along with digital pattern data D+ applied from a pattern data generator 1 to a D/A converter 2,
Digital pattern data D2 is outputted which is applied to the comparator 3 in order to inhibit the operation of comparing either the zero output level or the full scale output level of the /A converter 2 with a predetermined reference voltage vr. Reference numeral 7 denotes a latch circuit that holds an output that does not match a predetermined reference voltage vr with respect to either the zero output level or the full-scale output level of the D/A converter 2 compared with the comparator 3.

FIG. 2 is a timing chart for explaining the operation of FIG. 1. In FIG. 2, (a) shows the digital pattern data D1 output from the pattern generator 1 to the D/A converter 2, and (b) shows the digital pattern data D1 that is applied from the timing signal generator 6 to the D/A converter 2. timing signal TS
+, (C) shows the analog signal As converted and output from the D/A converter 2, and (d) shows the timing signal As. The signal TS2 is shown.(e) is D/
Predetermined reference voltage ■r for the zero output level of A converter 2
pattern data generator 1 to prohibit comparison operation with
Digital pattern data D2 applied to comparator 3 from
It is. That is, in the period in which the digital pattern data D2 is at H level, a comparison operation is performed between the full scale output level and the predetermined reference voltage Vr. (') is the data OtJ latched by the latch circuit 7 and output to the outside.
l' is shown. Here, the latch circuit 7 is
If the level of the analog signal As converted by the D/A converter 2 exceeds the level of the reference voltage r, as in l t +, the two signals are assumed to match and the comparison output data is not latched. However, if the level of the analog signal ΔS converted by the D/A converter 2 has not reached the level of the reference voltage Vr as at time t2, even though the two signals do not match, the comparison output data is Latch. The data OUT thus latched is bolded until a clear signal is applied.

In this way, since the latch circuit 7 holds the detection signal of malfunction of the D/Δ converter 2, it is not necessary to judge the comparison result of the comparator in each station Iff as in the conventional case, and the conversion speed is 100MHz or more. It is also possible to easily perform a dynamic response characteristic test of an l@i speed D/reconverter.

In the above embodiment, the timing signal T S 2 is applied to the latch circuit 7 from the timing signal light temperature 6 once per cycle, so that the output signal of the pattern data generator 1 is used to set the zero of the D/A converter 2. Although an example has been shown in which the comparison operation of the comparator 3 with respect to the conversion output is masked, the timing signal TS applied from the timing signal generator 6 to the latch circuit 7
υ control may be performed so that 2 is added once every two periods.

Furthermore, the comparison effect of the comparator 3 with respect to the full-scale converted output of the D/A converter 2 may be masked.

(Effects of the Invention) As explained above, according to the present invention, the relatively simple I11
%1M composition, it is possible to realize a D/A converter response test equipment that can perform dynamic response tests of D/A converters that perform high-speed conversion, and the practical effects are great.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a timing chart for explaining the operation of FIG. 1, FIG. 3 is a block diagram showing an example of a conventional device, and FIG. 4 is a timing chart for explaining the operation of FIG. 3. FIG. DESCRIPTION OF SYMBOLS 1... Pattern data generator, 2... D/A converter, 3... Comparator, 4... Reference voltage generator, 6...
Timing signal generator, 7... latch circuit. Fig. 1 Fig. 2 Fig. 3 Fig. 4 Fig. θLIT

Claims (1)

[Claims] A pattern data generator that generates digital pattern data to be applied to the D/A converter under test, a comparator that compares the analog signal converted by the D/A converter under test with a reference voltage, and a mismatch output from the comparator. 1. A D/A converter response test device comprising: a latch circuit that holds the D/A converter response test device.