SU1654807A1 - Device for synchronization pulse generation - Google Patents

Abstract

The invention relates to computing, automation and telemechanics and can be used in devices for discrete information processing and control. A distinctive feature of the device is that it allows to generate rectangular pulses of a variable (set by the operator) duration and follow-up period within the number of gradations of a previously known number in the digital binary code (for eleven such such number 2048 gradations). The aim of the invention is to expand functionality by providing a variable period and the duration of the output pulses. 4 il. with s

Description

The invention relates to computing, automation and telemechanics and can be used in devices for discrete information processing and control.

The purpose of the invention is to expand the functionality by providing a variable period and the duration of the output pulses.

Fig „1 shows the scheme of the device; figure 2 - diagram of the Converter code - time; FIG. 3 shows an example of the implementation of registers; PA figure 4 is a temporary diagram of the operation of the device.

The device contains a mode setting unit 1, registers 2,3, groups of 4.5 elements AND, element OR 6, with dynamic output, groups 7, 8 elements AND, blocks 9, 10 of the code-time conversion, generator 11 pulses.

Blocks 9, 10 conversion code - time contain converters 12

the code is the time, the element OR 13, the element 14 of the delay, the generator of the linear voltage 15, the trigger 16, the comparator 17. Fig. 3 shows the register 18.

The device works as follows

Initially, in block 1, the key Kis of the output of block 1 is pressed, a brief pulse Va is removed (Fig. 3), which is fed to the write enable input of registers 2 and 3 and resets them to zero. Then the key Ј is pressed (on block 1) and a signal is output from block 1, which is fed to the group of 5 elements I. After that, the keys 0,1,2, ... 9 are successively pressed in accordance with the required duration of the generated pulses (for example, 129, which corresponds to 129 not). In block 1, the number from the decimal number system is converted to digital

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the binary code, which is sent to register 2 via the information bus group AND 4, because the key was pressed before this, Then the key T was pressed, and the converted number typed by the keys 0,1,2, ".., 9, from the decimal notation into the digital binary code through a group of 5 elements And is written into register 3.

After dialing on block 1 the required duration of the generated pulses and the period of their repetition, the S key is pressed, and from the output of block 1, the signal Ug is fed to the driver 11. This driver is designed to form a short-term pulse ir, which from the output of block 1 leads to the first input of the element OR b, from the output of which this pulse goes to the second inputs of groups 7 and 8 of the elements I. As a result, the contents of register 2 through group 7 of the elements I the inputs of the converter 9-code is the time from the output of which the output pulse is taken) (the duration of cortic corresponds to the number in register 2.

Blocks 9 and 10 work as follows.

The code (and, in the converter, the code voltage fd - UQ is converted to voltage U2. Code | a is fed to the OR element with a delay in which it is delayed by a time greater than or equal to the transient time in the code - voltage. From the output of the element OR, with delay and dynamic output, pulse 0 is removed, which is applied to the first input of the linear voltage generator G. And starts it. From the output of the generator G, the voltage Ug is released, which increases linearly. The pulse U is supplied to input S of trigger T and bust yvaet in its state equivalent edinitseo

The voltages U and Uj are respectively connected to the first and second inputs of the comparator (analogue comparison circuit). At the point in time when the voltage U becomes equal to the voltage U, the pulse U is removed from the output of the analog comparison circuit, which transfers the trigger T to its initial state. The trigger pulse Uftblx is removed from the trigger output,

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whose duration is proportional to the input number Ја | in digital binary code.

At the same time, the contents of register 3 through a group of 8 elements I are fed to the inputs of block 10, and a pulse U is removed from the output of block 10 (Q, the duration of which corresponds to the number in register 3. The output of block 10 is connected to the second input of the element OR 6. Rear edge pulse U, 0 passes through the element OR 6, the output of which removes the pulse U, adequate to pulse Up, and the process of converting the contents of registers 2 and 3 in blocks 9 and 10 is repeated. This process continues until at block 1 the R key will be pressed, Registers 2 and 3 is transmitted to zero, and the process of generating rectangular pulses with a duration of Ј and a period of T is stopped.

The invention

A device for generating clock pulses, containing the first register and the first group of AND elements, the outputs of the first register being combined with the first inputs of the AND elements of the group, characterized in that, in order to expand the functionality of the device by providing a variable period and duration of the output pulses, Two code conversion units are introduced into it — time, three groups of AND elements, a second register, an OR element, a pulse shaper, a mode setting unit, the first output of the mode setting unit being connected to the enable inputs for recording the first and second registers, the second output of the mode setting block is connected to the input of the pulse former, the output of which is connected to the first input of the OR element, the second input of which is connected to the output of the first conversion unit g code - time, the group of information inputs of which are connected to the outputs of the elements And the second group, the first inputs of which are connected to the outputs of the second register, the second inputs of the AND elements of the first group are connected to the output of the OR element and to the second inputs of the AND elements of the second group, output dy elements And the first group are connected to the information inputs of the second unit

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Conversion code - time, output of the elements of the AND block of the third group of connector is the output of the device, the yen with the information inputs the first group of outputs of the block of setting the registrar register, the outputs of the elements And even

connected to the input groups of elements of the third and fourth groups, the inverted group - with the information inputs of the second register.

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Claims (1)

SUMMARY OF THE INVENTION A device for generating clock pulses comprising a first register and a first group of AND elements, the outputs of the first register being connected to the first inputs of the AND elements of the group, characterized in that, in order to expand the functionality of the device by providing a variable period and duration of output pulses , two code conversion blocks are introduced into it - time, three groups of AND elements, a second register, an OR element, a pulse shaper, a mode setting block, and the first block output is set mode I is connected to the recording permission inputs of the first and second registers, the second output of the mode setting unit is connected to the input of the pulse shaper, the output of which is connected to the first input of the OR element, the second input of which is connected to the output of the first conversion unit g code - time, group of information inputs which is connected to the outputs of the AND elements of the second group, the first inputs of which are connected to the outputs of the second register, the second inputs of the AND elements of the first group are connected to the output of the OR element and to the second inputs of the AND elements Ora group elements and the first group of outputs coupled to data inputs of the second unit moves the third group of AND INTERCONNECTING · yen to data inputs of the first register, and outputs elements of the fourth group - with data inputs of the second register. -1654807 'conversion code is the time whose output is the output of the device, the group of outputs of the mode setting unit is connected to the groups of inputs of the elements of the third and fourth groups, Fig.1 Figure 2 VI I V3 Vh * V5 ΐ - g Of 02 81 ¹ W ^{1 1} rz 02 Information HE 03 national 05 04 entrances About 18 05 07 06 · .. ε- b 08 Q7 08 -—Ί > C -! > And Information Outputs Fig.Z Ur 1 7 ..._____ η 1 π π .. gee Ufo g from............ U ₆ 1 J 1 i -------1- Fi. 4