JPH0829500A - Semiconductor testing device - Google Patents

Abstract

PURPOSE:To provide a semiconductor testing device which tests at high speed and high accuracy a mixed-signal IC (LCD driver IC) to be tested having a multi-channel pulse width modulation. CONSTITUTION:In the semiconductor testing device in which a reference clock 30 controlling the semiconductor testing device, a timing generator 40, and a pattern generator 50 are provided as a control stage 100, and a multiplexer stage 60, an AD converter 70, an acquisition memory 72 and a digital processor 73 are provided as a testing stage 200, and which tests a mixed signal IC 1 to be tested having a multi-channel pulse width modulation, an analog integrating stage 90, to which the pulse width modulation signal of the mixed-signal IC (LCD driver IC) to be tested having a multi-channel pulse width modulation is input, provides inputs to the multiplexer stage 60 from analog integrators 91, 92, M, and is provided with several hundred channels of analog integrators 91, 92, M.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mixed signal IC under test (LCD) having multiple channels and pulse width modulation.
The present invention relates to a semiconductor test device that tests a driver IC) at high speed and with high accuracy.

[0002]

2. Description of the Related Art Conventionally, a mixed signal IC under test (LCD driver I) having multiple channels and pulse width modulation is used.
FIG. 5 shows a block diagram of an embodiment in which C) is measured and tested by a generally known data acquisition circuit. Mixed signal under test with multi-channel pulse width modulation I
A semiconductor test apparatus for testing a C (LCD driver IC) includes an IC under test (LCD driver IC) 1, a test stage 300, and a control stage 100. A plurality of pulse width modulation circuit outputs 21, 22 and m built in the IC under test (LCD driver IC) 1 are connected to a multiplexer stage 60 composed of a plurality of multiplexers in the test stage 300, and the multiplexer stage 60 is a sample &
Connected to the hold 80, the test stage 300 includes a multiplexer stage 60, a sample & hold 80, an AD converter 70, an acquisition memory 72, and a digital processor 73. The control stage 100 includes a pattern generator 50 for applying a pattern signal to the IC under test (LCD driver IC) 1, a timing generator 40, and a reference clock 30. Prior art low bit, 4
Bit 16 gradation class device (LCD driver I
In the C) test, the test using a generally known data acquisition circuit as shown in FIG. 5 has no particular problem in terms of output voltage accuracy and operating speed in terms of liquid crystal panel performance.

[0003]

Higher gradation 6-bit 64 gradations to 8-bit 256 gradations (close to full color)
In the case of a device (LCD driver IC), the LCD driver IC is required to have output voltage accuracy and operating speed that are extremely severe and close to the limit. Therefore, the performance improvement of the LCD driver IC test device becomes a problem, which is a conventional test method. In the data acquisition circuit, the instantaneous value is sampled by sample & hold, so accurate measurement cannot be performed. In the method of measuring the repetition time of pulse width modulation (PWM) on all channels with a pulse width time measuring device, 6 bits 64 gradations or more The LCD driver IC under test has several hundred channels, and the configuration of the pulse width time measuring device becomes enormous. In the data acquisition circuit as shown in FIG. 5, accurate measurement for sampling the instantaneous value by sample & hold requires very many samplings and integration by digital operation. AD
Since a converter is required and a large amount of test time is required for calculation, it is difficult to measure a high-gradation device, for example, an LCD driver IC having 6-bit 64 gradations or higher with high accuracy. Further, in the test method using the pulse width time measuring instrument for measuring the pulse width, it is necessary to prepare a high precision time measuring instrument having a resolution of 1 nsec or less and operating at several tens of MHZ for several tens to several hundreds of channels. There was a drawback that the test equipment became large and expensive. The pulse width modulation signal of the pulse width modulation circuit built in the LCD driver IC under test is processed by the analog integrator regardless of the conventional data acquisition circuit configuration or the method using the pulse width time measuring device. By selecting the method of transmitting directly to the AD converter, the L for mixed signal under test with multi-channel pulse width modulation
The present invention provides a new semiconductor test device capable of testing a CD driver IC at high speed and with high accuracy.

[0004]

In order to achieve the above object, a new mixed signal IC under test (LCD driver IC) 1 having multiple channels and pulse width modulation of the present invention can be tested at high speed and with high accuracy. FIG. 1 is a block diagram showing the different structure and means. In the semiconductor test apparatus, the analog integration stage 90 has independent analog circuits corresponding to the number of pulse width modulation circuits so that the number of pulse width modulation circuits 21, 22, and m of the device under test (LCD driver IC) 1 can be controlled. An IC to be tested (LCD driver), which is provided with integrators 91, 92, and n, integrates according to an integration mode, sequentially takes out an analog integrator output by a multiplexer stage 60 including a plurality of multiplexers, and transmits it to an AD converter 70 provided next. (IC) 1 is provided with a pattern generator 50 for giving a pattern signal, a timing generator 40, and a control stage 100 composed of a reference clock 30. The control stage 100 is provided so as to control the entire semiconductor test apparatus, and the IC under test (LCD) The pulse width modulation signal from the driver IC) 1 is directly mounted on the semiconductor test equipment. Multiplexer stages of the analog integrator output to input signal to the analog integrator stage 90 test stage 200 6
The test stage 200 for inputting a signal to 0 comprises a multiplexer stage 60, an AD converter 70, an acquisition memory 72 and a digital signal processor 73. As a result of adopting a method in which each pulse width modulation signal is directly input to the integration stage 90 from the pulse width modulation circuits 21, 22, m of the IC under test (LCD driver IC) 1,
The mixed signal IC under test (LCD driver IC) 1 having multiple channels and pulse width modulation can be tested at high speed and with high accuracy.

[0005]

The present invention relates to an IC under test (LCD driver I
C) When each pulse width modulation signal is directly input from the pulse width modulation circuit 21, 22, m of 1 to the integration stage 90, each integrator 91, 92, n is operated by the semiconductor test apparatus control stage 10.
It operates by the action of 0 to perform each integrated output, and each integrated output is sequentially AD by the action of the multiplexer stage 60.
The AD converter 70 that is input to the converter 70 operates and outputs a signal to the next stage.

[0006]

1 is a block diagram of an embodiment of a semiconductor test apparatus for a mixed signal IC under test (LCD driver IC) 1 having multi-channel pulse width modulation according to the present invention. In order to test the IC under test (LCD driver IC) 1, the analog integration stage 90, the control stage 100, and the analog stage 90 for inputting the signals of the pulse width modulation circuits 21, 22, m built in the IC under test (LCD driver IC) 1 are tested. It is composed of a stage 200. Analog integration stage 90
Is provided with the same number of analog integrators as the pulse width modulation circuits 21, 22, m built in the IC under test (LCD driver IC) 1, that is, the analog integrators 91, 92, M are provided with several hundred channels. IC under test (LCD driver IC)
The control stage 100 is composed of a pattern generator 50 for giving a pattern signal to 1, a timing generator 40, and a reference clock 30. The control stage 100 controls the entire semiconductor test apparatus. The integrated output integrated by the analog integration stage 90 is input to the multiplexer stage 60 of the test stage 200 and sequentially processed by the test stage 200. The test stage 200 is the multiplexer stage 6
0, AD converter 70, acquisition memory 72, and digital processor 73.

A timing chart of FIG. 2 is shown. When a prescribed A signal is applied to a device (IC under test) for testing the IC under test (LCD driver IC) 1 (reference clock, digital signal, latch signal), each pulse width modulation circuit 21, 22 built in the device , N, the signal of the PWM output B is output from each pulse width modulation circuit. When the integration mode is integrated for two cycles, each analog integrator 91, 9
2, M outputs the signal of the integrated value D, each multiplexer of the multiplexer stage 60 indicated by E sequentially performs channel switching to ch1, ch2, ch3, ch4. The AD converter 70 performs AD conversion according to the signal of the sampling clock F. Converter digital output G is CH1, C
Test stage 200 with H2, CH3, and CH4
The output G is input to the acquisition memory 72 of FIG.

Another embodiment is shown in FIG. In order to test the IC under test (LCD driver IC) 1, the analog integration stage 90, the control stage 100, and the analog stage 90 for inputting the signals of the pulse width modulation circuits 21, 22, m built in the IC under test (LCD driver IC) 1 are tested. It consists of a stage 400. The analog integration stage 90 is an LC to be tested.
Pulse width modulation circuits 21, 22 with a built-in D driver IC 1,
The same number of analog integrators as m are provided, that is, hundreds of analog integrators 91, 92 and M are provided. The control stage 100 is composed of a pattern generator 50 that gives a pattern signal to the IC under test (LCD driver IC) 1, a timing generator 40, and a reference clock 30. The control stage 100 controls the entire semiconductor test apparatus. The integrated output integrated by the analog integration stage 90 is directly input to the AD converters 77, 78, N of the test stage 400. The AD converters 77, 78, N and the analog integrators 91, 92, M are provided in a pair. The input integrated signal is processed by the test stage 400.
D converters 77, 78, N and acquisition memory 72
And a digital processor 73.

FIG. 4 shows another embodiment. For testing the IC under test (LCD driver IC) 1, the multiplexer stage 60, the analog integration stage 90, and the test stage for receiving the signals of the pulse width modulation circuits 21, 22, m built in the IC under test (LCD driver IC) 1 5
00 and control stage 100. The multiplexer stage 60 is an IC under test (LCD driver I
C) The AD converters 77, 78, n and the analog integrators 91, 92, n for processing the signals of the pulse width modulation circuits 21, 22, m built in 1 and sequentially sending them to the analog integration stage 89 in the test stage 500 are Provide in a pair. The input integrated signal is processed by the test stage 500. The test stage 500 includes AD converters 77, 78, n, an acquisition memory 72 and a digital processor 73. A pattern generator 50 for giving a pattern signal to the IC under test (LCD driver IC) 1 and a timing generator 4
The control stage 100 includes 0 and a reference clock 30, and the control stage 100 controls the entire semiconductor test apparatus.

[0010]

Since the present invention is constructed as described above, it has the following effects. The pulse width modulation circuits 21, 22 and m built in the IC under test (LCD driver IC) 1 are directly connected to the analog integration stage 90. Since the analog integration output is input to the multiplexer stage 60, it has multi-channel pulse width modulation. The LCD driver IC1 for mixed signal under test can be tested at high speed and with high accuracy. The analog integration stage 90 for inputting the signals of the pulse width modulation circuits 21, 22, m built in the IC under test (LCD driver IC) 1 is paired with the analog integrators 91, 92, M and the AD converters 77, 7 respectively.
By providing 8 and N, analog integration can be performed immediately, so that high-speed and high-accuracy testing is possible. IC under test (LC
D driver IC) 1 built-in pulse width modulation circuit 21, 2
2, m, and a multiplexer stage 61 provided between the analog integration stage 90 and the pulse width modulation circuit 21, 2
2, m is connected to the multiplexer stage 60, and the number of analog integrators is reduced by the individual arrangement of the multiplexer stages 61, so that the apparatus cost is reduced.

[Brief description of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention.

FIG. 2 is a timing chart thereof.

FIG. 3 is a block diagram of another embodiment.

FIG. 4 is a block diagram of another embodiment.

FIG. 5 is a block diagram of an example of a conventional semiconductor test apparatus.

[Explanation of symbols]

 1 IC under test (LCD driver IC) 11, 12, D digital input terminal 20 control input 21, 22, m pulse width modulation circuit 30 reference clock 40 timing generator 50 pattern generator 60, 61 multiplexer stage 70, 77, 78, n, N AD converter 72 Acquisition memory 73 Digital signal processor (DSP) 80 Sample and hold 89, 90 Analog integration stage 91, 92, M, n Analog integrator 100 Control stage 200, 300, 400, 500 Test stage

Claims (3)

[Claims] 1. A semiconductor test apparatus for testing an IC under test (1) which outputs a multi-channel pulse width modulation signal, and a timing and a pattern generator (50) for applying a pattern signal to the IC under test (1). A plurality of control stages (100) each comprising a generator (40) and a reference clock (30) and a plurality of output terminals of the IC under test (1) for outputting a multi-channel pulse width modulation signal. Analog integrators (91, 92, M), an analog integrator stage (90), a multiplexer stage (60) for selecting the outputs of the plurality of analog integrators (91, 92, M), and an AD converter ( 70) and acquisition memory (72)
And a test stage (200) comprising a digital processor (73). 2. A semiconductor test apparatus for testing an IC under test (1) which outputs a multi-channel pulse width modulation signal, wherein a timing and a pattern generator (50) for applying a pattern signal to the IC under test (1). A plurality of control stages (100) each comprising a generator (40) and a reference clock (30) and a plurality of output terminals of the IC under test (1) for outputting a multi-channel pulse width modulation signal. Analog integrators (91, 92, M), and a plurality of AD converters (7) input corresponding to the outputs of the plurality of analog integrators (91, 92, M).
7, 78, N), acquisition memory (72), and digital processor (73) test stage (400)
A semiconductor testing device comprising: 3. A semiconductor tester for testing an IC under test (1) which outputs a multi-channel pulse width modulation signal, and a timing and a pattern generator (50) for applying a pattern signal to the IC under test (1). A control stage (100) consisting of a generator (40) and a reference clock (30), and a plurality of outputs for selecting the pulse width modulated signal of the IC under test (1) for outputting the pulse width modulated signal of multiple channels. Multiplexer stage (6
1) and a plurality of analog integrators (91, 91) for inputting a pulse width modulation signal corresponding to the multiplex stage (61).
92, n) and an analog-to-digital converter (77, 78, 92) for input corresponding to each of the plurality of analog integrators (91, 92, n).
n), an acquisition memory (72), and a test stage (500) including a digital signal processor (73).