JPS60232721A - Testing device for digital/analog converter - Google Patents

Abstract

PURPOSE:To simplify the constitution of a testing device and to test the whole operating range by generating a digital signal successively changed in each least significant bit (LBS) from a digital signal generating means and supplying the digital signal to a D/A converter to be tested. CONSTITUTION:A clock signal is generated from a clock generator 10 in the digital signal generating means 14 of a D/A converter testing device and counted up by an UP counter 12 and a digital signal successively increased in each LBS is generated. The digital signal is converted into an analog signal by the D/A converter 16 to be tested and the analog signal is inputted to a sample holding circuit 18 and the 1st comparator 20. On the other hand, the signal outputted from the converter 16 is offset of a negative direction by an offset means 22 and applied to the 2nd comparator 24. The output of the circuit 18 is applied to the comparators 20, 24 respectively and the outputs of the comparators 20, 22 are inputted to a logical gate means 26. The output of the means 26 is applied to a data input of an FF28. On the other hand, the clock signal is inverted by an inverter 30 and applied to the circuit 18 and said inverted signal is inverted again by an inverter 32 and then applied to the FF28 to decide the legality of the converter 16.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a test device for determining the quality of a digital-to-analog converter.

[Prior art and its problems]

Digital-to-analog (D/A) converters are widely used as interfaces between digital and analog circuits. In order to ensure that electronic equipment using a D/A converter operates correctly, it is necessary to test the D/A converter to determine its acceptability.

One of the conventional test devices for D/A converters is Japanese Patent Application Laid-Open No. 58-1
It is disclosed in Japanese Patent No. 72560. This conventional test device counts clock signals using a counter, and supplies the counted output to the D/A converter under test as a digital signal that changes in units of least significant bits (LSBs). sample·
The hold (S/H) circuit samples and holds the analog signal of the D/A converter delayed by one clock. A differential amplifier calculates the difference between the output signals of the D/A converter and the S/H circuit, and uses this difference signal as a reference analog/digital (A/D) signal.
Supplied to the converter. The quality of the υD/A converter is determined based on the digital output signal from the A/D converter. However, in this conventional test equipment, the differential amplifier provides ILS over the entire range of the output signal of the D/A converter.
It is necessary to accurately amplify the difference between the analog signals corresponding to B, that is, the dynamic range of the differential amplifier must be wide, making it expensive.

Additionally, a reference A/D converter was also required, making the test equipment more expensive and complex.

Other conventional D/A converter test equipment is
It is disclosed in Japanese Patent No. 4928. This conventional test equipment is equipped with two S/'H circuits at the output of the D/A converter under test, and each S/H circuit operates only when an input signal is applied to a specific bit of the digital signal. (for example, 1000 or 0100) and the D/A converter output signal when input signals are given to all bits lower than a specific bit of the digital signal (for example, 0111 or 0011). Holds the converter output signal. A differential amplifier calculates the difference between the output signals of the two S/H circuits, and a window comparator determines whether this difference signal corresponds to the LSB.
The quality of the D/A converter is determined. However, even with this conventional test equipment, the differential amplifier has a wide range of ILS
It is necessary to accurately amplify the difference between the analog signals corresponding to H, that is, a differential amplifier with a wide dynamic range is required, which is expensive. Also, this test equipment
Since the test was performed only partially within the operating range of the A converter, the quality of the D/A converter was not guaranteed over the entire operating range.

[Purpose of the invention]

It is therefore an object of the present invention to provide a D/A converter which is simple and inexpensive in construction and which tests over the entire operating range of the D/A converter.
The purpose is to provide test equipment for converters.

[Summary of the invention]

According to the test device of the present invention, the digital signal generating means generates a digital signal that sequentially changes in units of least significant bits,
Supplied to the D/A converter under test.

The S/H circuit samples and holds the analog signal from the D/A converter before the digital signal changes bit by bit. The first comparator compares the output signals of the D/A converter and the S/H circuit, and determines which output signal is larger. That is, when the digital signal is changing in the increasing (or decreasing) direction, it is determined whether the analog output signal of the D/A converter is also changing in the increasing (or decreasing) direction. The second comparator offsets one of the analog output signal of the D/A converter and the output signal of the S/H circuit by a predetermined voltage.

The detected signal and other signals are compared to determine which signal is thicker. That is, the second comparator determines whether the output signal of the D/A converter changes by a predetermined voltage in response to a change in the digital signal. Then, the logic gate means integrates the judgment results of the first and second comparators, and
The quality of the converter is determined.

[Embodiments of the invention]

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

(First Embodiment) FIG. 1 is a block diagram of a preferred first embodiment of the present invention. A clock generator 10 generates a clock signal, and an amplifier/counter 12 counts the clock signal and calculates the LSB.
Generates a digital signal that increments sequentially in units. These clock generator 10 and counter 12 constitute digital signal generating means 14. The D/A converter 16 under test is a color/
Convert the digital signal from RI 12 into an analog signal,
It is directly supplied to the S/H circuit 18 and the inverting (-) input terminal of the first comparator 200. Further, the analog signal from the D/A converter 16 is offset by a predetermined voltage in the negative direction by a battery 22 serving as an offset means, and then supplied to the non-inverting (+) input terminal of the second comparator 24 . Note that the voltage of the battery 22 is a voltage corresponding to approximately 2L'SB of the digital signal. S
The output signal of the /H circuit 18 is supplied to the ten input terminals of the first comparator 20 and one input terminal of the second comparator 24. Comparator 2
0 and 24 are wired-OR connected, that is, comparator 20
and 24 are supplied to a wired-OR gate 26, which is a logic gate means, and the output signal is supplied to a D input terminal of a D flip-flop 28. On the other hand, the clock signal from the clock generator 10 is supplied to the S/H circuit 18 via a buffer 30 as a sample control signal, and is further supplied via a buffer 32 to the clock terminal of the D Frisage flop 28. Buffer 30 compensates for the propagation delay time of counter 12 and D/A converter 16, and buffer 32 compensates for the propagation delay time of S/H circuit 18 and comparators 20 and 24. These buffers 30 and 32 may be delay circuits (delay lines). The reset terminal R of the D flip-flop 28 is connected to the positive power supply through a switch 34, and the Q output terminal is connected to the base of a transistor 36. The emitter of transistor 36 is grounded, and the collector is connected via light emitting diode 38 to a positive voltage source.

To test D/A converter 16, first reset flip-flop 28 by temporarily closing switch 34. Therefore, the Q output signal of flip-flop 28 is at a "low" level, transistor 36 is turned off, and light emitting diode 38 does not emit light. The S/H circuit 18 samples and holds the analog signal from the D/A converter 16 before the digital signal changes in LSB units. Therefore, even if the digital signal from the counter 12 changes, the output of the S/H circuit 18 will always be higher than the output signal of the D/A converter 16.
This is an analog signal that is lower by ILSB. Since the digital signal is changing in an incremental direction, if the output signal of the D/A converter 16 is also changing in an incremental direction, the voltage at one input terminal of the first comparator 20 will be more similar to the voltage at the tenth input terminal. is always high.

Therefore, the output level of the first comparator 20 is also always "low". However, if the output signal of the D/A converter 16 does not increase in response to changes in the digital signal, for example, if the output signal of the D/A converter 16 decreases, the voltage at the input terminal of the comparator 20 becomes higher than the voltage at one input terminal, and the output level of the comparator 20 becomes "high". Therefore, the output signal of OR gate 26 is also high, and the clock signal causes the Q output signal of flip-flop 28 to also be high. Therefore, transistor 36 turns on and light emitting diode 38 emits light, indicating an incremental abnormality in D/A converter 16. That is, by the first comparator 20, the D/A
Incremental anomalies in the transducer 16 can be detected.

On the other hand, one input terminal of the second comparator 24 normally receives the output signal of the D/A converter 16 before the digital signal changes;
That is, a voltage lower by ILSB than the current output signal is applied. In addition, the ten input terminal of the second comparator 24 has a D/
A voltage subtracted by 2LSB from the current output signal of the A converter 16 is applied.

Therefore, if the amount of change in the D/A converter 16 is normal, the second
The voltage at one input terminal of the comparator 24 is higher than the voltage at the tenth input terminal, and its output level is "low". However, D/
If the amount of change in the A converter 16 is larger than a predetermined value (2LSB or more), the output level of the second comparator 24 is "high".
When the output level of the OR gate 26 is also "high", the light emitting diode 38 emits light. That is, the second comparator 24 is D/
An abnormality in the amount of change in ILSB of the A converter 16 is detected. The above operation is performed for each bit over the entire operating range of the D/A converter 16, and an abnormality in the D/A converter 16 is indicated by light emission from the light emitting diode 38. It should be noted that the comparators 20 and 24 only need to determine the magnitude of the voltages at the + and - input terminals, and there is no need to accurately amplify the difference between them.

(Second Embodiment) FIG. 2 is a block diagram of a second preferred embodiment of the present invention. Since this embodiment is similar to the embodiment of FIG. 1, like blocks or elements will be designated with the same reference numerals and only differences will be described. In this second embodiment, up e
An up-down counter 40 is used in place of the counter 12, and its carry output terminal C and borrow output terminal B are connected to the R input terminal and S output terminal of an R-S flip-flop 42, respectively. The Q output signal of is supplied to the amplifier down control terminal U/D of the counter 40 to control whether the counting output of the counter is increasing or decreasing. Electronic switches 44 and 46 switch D/A converters 12 and S according to the Q output of flip-flop 42.
The output signal of the /H circuit 16 is selectively applied to the - of the first comparator 20.
and 10 input terminals. A battery 48, which is the same as battery 22, is connected in parallel with battery 22 with opposite polarity, and electronic switch 50 selects battery 22 or 48 depending on the Q output of flip-flop 42. Electronic switches 52 and 54 selectively provide the output signals of S/H circuit 16 and electronic switch 50 to the - and - input terminals of second comparator 24 in response to the Q output of flip-flop 42 . Note that the electronic switch 44
．． 46.50. Note that '52 and 54 may be a single analog multiplexer combining five electronic switches.

When counter 40 generates a borrow signal from terminal B, the Q output of flip-flop 42 goes to a "high" level.

Therefore, the counter 40 is in the up mode and the digital signal changes bit by bit in the increasing direction. Also, due to this "high" level Q output, electronic switches 44 and 46 select D/A converter 12 and S/H circuit 16, respectively, electronic switch 50 selects battery 22, and electronic switch 52 selects battery 22.
and 54 select the S/H circuit 16 and the electronic switch 50. That is, the selected state of the electronic switch is as shown in the figure. Therefore, in this state, the operation is the same as in the case of FIG. 1, and the embodiment of FIG. 2 operates in the same manner as described in FIG.

When the count value of counter 40 reaches its maximum value and generates a carry signal from terminal C, flip-flop 42 is reset and its Q output is inverted to a "low" level. Therefore, the counter 40 is not in the down mode and the digital signal changes bit by bit in the decreasing direction. The selection states of the electronic switches 44, 46, 50, 52 and 54 also change. Therefore, if the decreasing direction of the analog output signal of the D/A converter 12 is normal, the voltage at one input terminal of the first comparator 20 is higher than the voltage at the tenth input terminal, and its output is at a "low" level. . On the other hand, the output level of the electronic switch 50 is D/
Since it is 2 LSB higher than the analog output signal of the A converter 12, if the amount of change for each bit of the D/A converter 12 is normal, the voltage at one input terminal of the second comparator 24 will be 2LSB higher than the analog output signal of the A converter 12. voltage, its output is at a "low" level. Therefore, in this second embodiment, the D/A converter can be tested with a digital signal that changes in increasing and decreasing directions.

(Third Embodiment) FIG. 3 is a block diagram of a third preferred embodiment of the present invention, which is applied to a microprocessor (μP) system. In this embodiment, the same reference numerals are used for the same blocks and elements as in the embodiment of FIG. 1, and only the differences will be described. The μP system includes a μP 58 connected to a bus 56, and a read-only memory (ROM) that stores programs.
60, a random access memory (RAM) 6 as a temporary storage device, a keyboard 64 as an input device,
It includes a display 66 and electronic circuitry 68 such as a meter or signal generator. The D/A converter 16 supplies analog signals to the electronic circuit 68 to perform various controls.

The data signal on bus 56 changes in response to the address signal. Therefore, decoder 70 generates a clock signal in response to changes in the address signal from bus 56 and supplies it to buffer 30. The latch circuit 72 latches the data signal from the bus 56 in response to the clock signal from the decoder 70 and supplies it to the D/A converter 16. The input terminal of tristate driver 74 receives the output signal of OR gate 26 and its output terminal is connected to bus 56. Driver 74 is also controlled by tristate control signals from bus 56.

When the self-diagnosis mode of the μP system is started by a command from the keyboard 64 or automatically by turning on the power, the μP system self-diagnosis mode is started by the self-diagnosis program in the ROM 60.
P58 sets the driver 74 to normal mode (operates as a mere buffer). Further, the μP 58 generates a digital signal that sequentially increases in units of least significant bits as a data signal, and supplies it to the D/A converter 16 via the launch circuit 72. Then, the same operation as in the embodiment shown in FIG. 1 is performed. The μP58 drives the driver 74 every time the data signal changes.
The output level of the D/A converter 16 is monitored, and if the output level is always "low", it is determined that the D/A converter 16 is normal. Also, when the output level of the driver 74 becomes "high", the μP58 outputs the D/A
It is determined that the converter 16 is abnormal, and the display 66 displays this fact. When the test of the D/A converter 16 is completed, the μP58
tri-states the driver 74 (high output impedance state) and eliminates the influence on the bus 56. In this embodiment, the digital signal generating means is μP58.

(Changes to Embodiments) Although the preferred embodiments of the present invention have been described above, various changes can be made without departing from the gist of the present invention.

For example, the logic gate means can use various logic gates such as an AND gate and a NOR gate instead of a wired OR, taking into consideration the polarities of the input and output terminals of the first and second comparators. Further, in the embodiment, the output signal of the D/A converter is offset by a predetermined voltage, but the output signal of the S/H circuit may also be offset. Furthermore, this offset may be performed by a voltage adder using a constant voltage diode, an ordinary diode, an operational amplifier, etc. instead of a battery. Further, the voltage to be offset may be slightly higher or lower than the ILSB, taking tolerance into account. In this case, it should be noted that the output level of the second comparator differs depending on whether it is high or low. In addition, two comparators are used as the second comparator, and one of the output signals of the D/A converter or S/H circuit is set at a voltage slightly higher and a voltage slightly lower than the ILSB considering tolerance. The other output signal of the D/A converter or S/I (circuit) is supplied to one input terminal of each of the two second comparators with an offset in two. In this case, by supplying the output signals of the two second comparators to the logic gate, the amount of change in the D/A converter can be both positive and negative. It can be determined whether or not it is within the allowable range.Furthermore, a scissor or the like may be driven by the output signal of the logic gate means to indicate a defect in the D/A converter.

〔Effect of the invention〕

As described above, the present invention does not require the use of a reference A/D converter or a high-precision differential amplifier with a wide dynamic range, and simply uses a comparator that compares the magnitude, so the configuration is simple and inexpensive. Become. Furthermore, since the entire operating range of the D/A converter is tested in LSB units, the test results are reliable.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a first preferred embodiment of the present invention;
The figure is a block diagram of a second preferred embodiment of the present invention, and FIG. 3 is a block diagram of a third preferred embodiment of the present invention. In the figure, reference numeral 4 indicates a digital signal generation means, 16 indicates a digital-to-analog converter under test, 18 indicates a sample/hold circuit, 20 indicates a first comparator, 22 indicates an offset means, 2
4 is a second comparator, and 26 is a logic gate means.

Claims (1)

[Claims] digital signal generating means for supplying a digital signal that sequentially changes in the least significant bit unit to the digital-to-analog converter under test; and an analog signal from the digital-to-analog converter under test before the digital signal changes in the bit unit. a sample-and-hold circuit that samples and holds a signal; a first comparator that compares the analog signal from the digital-to-analog converter under test and the output signal from the sample-and-hold circuit; and the digital-to-analog converter under test. a second comparator for comparing the analog signal from the converter and the output signal from the sample-and-hold circuit with a signal obtained by turning off one signal by a predetermined voltage and the other signal; logic gate means for receiving an output signal and an output signal from the second comparator;
A test device for digital-to-analog converters, characterized by determining the quality of analog converters.