JP3167537B2 - DA converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a D
It relates to the A converter.

[0002]

2. Description of the Related Art In recent years, DA converters have been widely used not only for signal processing but also for adjusting IC circuits. Hereinafter, a conventional DA converter will be described. FIG. 5 is a configuration diagram of a conventional m-bit n-channel DA converter, wherein 1 is a serial / parallel conversion / address decoder circuit, 2 is a data latch circuit, 3 is an analog conversion circuit, 4 is an adjustment circuit group inside the IC, 11 is a serial data input terminal, 12 is a clock pulse input terminal,
13 is a load pulse input terminal, 41 to 4 n are adjustment circuits inside the IC, 81 to 8 n are test pads, 211 to 21 m
Is parallel data output from the serial / parallel conversion / address decoder circuit 1, 221 to 22n are address designation pulses, 311 to 3nm are latched parallel data, and 401 to 40n are outputs from the analog conversion circuit 3.

The operation of the DA converter configured as described above will be described below. First, the serial / parallel conversion / address decoder circuit 1 receives serial data from a terminal 11, a clock pulse from a terminal 12, and a load pulse from a terminal 13 in the case of a three-wire input. The input serial data is converted into m-bit parallel data by a serial / parallel converter / serial / parallel converter of the address / decoder circuit 1, and an n-channel address is output by the address decoder unit of the serial / parallel converter / address decoder 1. A designated pulse is created. Next, the aforementioned parallel data 211 to 21m are input to all the channels of the data latch circuit 2, and the addressing pulses 221 to 22n corresponding to the respective channels are input. The parallel data 211 to 21m are latched by the data latch circuit 2 on the channel specified by the addressing pulses 221 to 22n. Parallel data 311-3 latched in data latch circuit 2
nm is input to each corresponding channel of the analog conversion circuit 3 and converted into an analog voltage, and the output 401 to 40n of the analog conversion circuit 3 controls the adjustment circuit 4 inside the IC.
Adjustment of 1 to 4n is enabled.

[0004]

However, in the above-described conventional configuration, when the linearity or monotonic increase of each channel of the adjusting DA converter provided inside the IC is inspected, an external device is provided for each channel. There is a disadvantage that the number of terminals or test pads 81 to 8n must be increased. In IC, external terminal pads or test pad
Is much larger than the elements that make up the circuit ,
To install additional external terminal pad or test pad, such as described above
If that becomes the area expansion of the IC to invited Kukoto, it becomes a factor in the cost of the IC.

The present invention solves the above-mentioned conventional problems, and provides a DA converter capable of inspecting a single output of each channel of a DA converter by adding or not adding one external terminal or test pad. The purpose is to do.

[0006]

Means for Solving the Problems] DA converter according to claim 1, Siri for converting serial data into parallel data
And al-parallel converter, the address and the address decoder to create a specified pulse, the serial-to-parallel converting unit or <br/> et al outputted parallel data addressing pulse data latch circuit for latching each designated channel by And latched for each channel of the data latch circuit
An analog conversion circuit that converts parallel data to analog voltage for each corresponding channel, and a conversion for each channel
Output of the analog conversion circuit
A plurality of IC internal adjustment circuits, a first transistor to which an output of the analog conversion circuit is input to a base;
It has the same polarity as the transistor and is diode-connected
The second transistor and the first and second transistors;
Switching control of current supply to the common connection point of the transmitter
The differential circuit constituted by the third transistor
Provided for each channel of the analog conversion circuit.
Connecting the bases of the first and second transistors in common
A test switch circuit for extracting an output signal from the
And an external terminal for outputting the output signal of the test switch circuit.
The third transistor provided for each channel
Chino one was allowed to conduct the addressing pulses, and wherein the Turkey to output the output of the analog conversion circuit of the specified channel to the external terminal.

[0007] The DA converter according to claim 2 is a serial data converter.
Serial / parallel conversion to convert data to parallel data.
Switching unit and an address decoder for creating an addressing pulse.
And the parameters output from the serial / parallel converter.
Real data is stored in the channel specified by the addressing pulse.
A data latch circuit for latching each channel, and a data latch circuit.
Parallel data latched for each channel of the
Analog to convert to analog voltage for each corresponding channel
Analog conversion circuit for each channel
A plurality of ICs to which the output of the conversion circuit is inputted correspondingly
The output of the internal adjustment circuit and the analog conversion circuit
The first transistor being activated, the same as the first transistor
Second transistor, unipolar and diode connected
And a source connected to the ground line and the first, second
Current supply to the common emitter connection point of
It is constituted by a third transistor for controlling the switching.
The first differential circuit and the same polarity as the first transistor
And the fourth transistor in which the output of the IC internal circuit is connected to the base.
A transistor having the same polarity as the first transistor and having a
The fifth transistor, which is connected in ode, and the source is
A gate connected to a ground point and having a gate for the first differential circuit;
Fourth and fifth transistors connected to the line
Control of current supply to common emitter connection point
The second differential constituted by the sixth transistor
And a first differential circuit of the analog conversion circuit.
A second track is provided corresponding to each channel.
Base of transistor and base of fifth transistor
That the output signal is taken out from the connection point where
Output signal of the test switch circuit and the test switch circuit.
And a gate of a sixth transistor.
The potential of the input and the ground line for the first differential circuit is
High level voltage at all times and low level voltage during inspection
It is characterized by setting so that.

A DA converter according to a third aspect of the present invention is the DA converter according to the second aspect , wherein the data is latched by a data latch circuit.
One of the parallel data is used as the mode signal
High level during normal operation and low level during inspection.
A voltage applied to the gate input of the sixth transistor
I can get it.

[0009]

SUMMARY OF] According to the first aspect, the output of the analog conversion circuit of the channel designated by the addressing pulse is selected by the test switch circuit, one (test
Output to an external ( dedicated) terminal . Therefore , one pad is added compared to when not checking the output of the analog conversion circuit.
By the characteristics of each channel of the DA converter
Can be inspected .

Further, according to the configuration of the second aspect, the fourth aspect
Input the output of the IC internal circuit to the base of the transistor,
A mode signal for switching between the normal mode and the inspection mode is input to the gate of the sixth transistor, and the inspection switch is
When the switch circuit is activated,
When the de-signal is input, it outputs the output of the internal circuit of the IC to the external terminal. And the level of the inspection mode
When a mode signal is input , the output of the analog conversion circuit of the channel specified by the addressing pulse is output.
Output to the same external terminal . Accordingly, because it serves the external terminals for inspection and one terminal of the internal circuit of the IC, outside pin for inspection only is not required, that Do requires input terminal of the mode signal. As a result, a mode signal input terminal is provided.
The characteristics of each channel of the DA converter
Can be inspected .

Further, according to the third aspect of the present invention, one of the parallel data outputs of the data latch circuit is used as a mode signal .
When used as an inspection switch
Circuit operation switches between normal operation and inspection operation
It is, the input terminal for the mode signal is that Do not required. This
Thus, each channel of the D / A converter can be inspected without increasing the number of inspection pads.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First, FIG.
This will be described with reference to a plane. FIG. 1 shows a first embodiment of the present invention.
Examples include any number of bits and any number of channels,
1 shows a configuration diagram of an m-bit n-channel DA converter
Things. In FIG. 1, reference numeral 1 denotes a serial / parallel conversion.
Address / decoder circuit, 2 is a data latch circuit, 3
Is an analog conversion circuit, 4 is an adjustment circuit group inside the IC, 5 is
Inspection switch circuit, 6 is output buffer circuit, 7 is output
11 is a serial data input terminal, and 12 is a
A lock pulse input terminal, 13 is a load pulse input terminal,
41 to 4n are adjustment circuits inside the IC, and 211 to 21m are systems.
Output of real / parallel conversion / address decoder circuit 1
Parallel data, 221 to 22n are serial / parallel
Of the output of the address conversion / address decoder circuit 1
Pulses, 311 to 3 nm are latched parallel data
And 401 to 40n are outputs of the analog conversion circuit 3.
You. In the inspection switch circuit 5, M₁~ M_n
Is NMOSFET, Q _A1~ Q_An, Q_B1~ Q_Bn, Q_P1, Q
_P2Is a transistor, R₁~ R_nIndicates a resistance.

A serial data input terminal 11, a clock pulse input terminal 12, and a load pulse input terminal 13 are connected to a serial / parallel conversion / address decoder circuit 1 for receiving parallel data 211 to 21m of the serial / parallel conversion / address decoder circuit 1. The output is sent to all channels of the data latch circuit 2,
Address designation pulses 221 to 221 of the address decoder circuit 1
The output of 22n is, for example, 221 if the data latch circuit 2
CH1 and NMOSFET M of the inspection switch circuit 5
_First gate, the so on 222, if the data latch circuit 2 of CH2 and the gate of NMOSFET · M ₂ of the test switch circuit 5, NMOSFET · M channel and the test switch circuit 5 to the corresponding data latch circuit 2
_{1 to Mn} are connected to corresponding gates.

The output of the parallel data 311 to 3 nm of each channel of the data latch circuit 2 is, for example, 311 to 311.
If it is 1m, CH1, 321-32m of the analog conversion circuit 3
Then, it is connected to each corresponding channel of the analog conversion circuit 3, such as CH2 of the analog conversion circuit 3,
Outputs 401 to 40 of each channel of the analog conversion circuit 3
n is, for example, 401, the base of the transistor Q _A1 of the adjustment circuit 41 inside the IC and the inspection switch circuit 5;
Then, the ICs are connected to the adjustment circuits 42 to 4n inside the IC and the bases of the transistors Q _{A1 to} Q _An of the inspection switch circuit 5, respectively, such as the adjustment circuit 42 inside the IC and the base of the transistor Q _A2 of the inspection switch circuit 5. ing.

The NMOSF of the inspection switch circuit 5
The source of the ET · M ₁ ~M _n is grounded, and the drain respectively connected to the emitter of the transistor Q _A1 to Q _An emitter and Q _B1 to Q _Bn through each resistor R ₁ to R _n, the transistors Q _A1 ~ The collector of Q _An is connected to the collector and base of Q _P1 , and the collectors and bases of transistors Q _{B1 to} Q _Bn are connected to the collector of transistor Q _P2 and output from test switch circuit 5 via output buffer circuit 6. And is connected to the output terminal 7.

The DA of this embodiment configured as described above
The operation of the converter will be described below. First,
Serial data is input from the terminal 11 to the serial / parallel conversion / address decoder circuit 1, a clock pulse is input from the terminal 12, and a load pulse is input from the terminal 13 in the case of a three-wire input. The input serial data is sent to the serial / parallel conversion / address decoder circuit 1
The data is converted into m-bit parallel data by a parallel conversion unit, and is converted into a serial / parallel conversion / address decoder circuit 1.
The n-channel address designating pulse is generated by the address decoder section of FIG. Next, the above-described parallel data 211 to 21m are applied to all the channels of the data latch circuit 2, and the addressing pulses 221 to 22 corresponding to the respective channels.
n is input. The parallel data 211 to 21m are supplied to the data latch circuit 2 by the addressing pulses 221 to 21m.
Latched to the channel designated by 22n. The parallel data 311 to 3 nm latched in the data latch circuit 2 are input to the corresponding channels of the analog conversion circuit 3 and are converted into analog voltages. The output circuits 401 to 40n of the analog conversion circuit 3 control the adjustment circuit inside the IC. The adjustment of 41 to 4n is enabled.

Further, in this embodiment, for example, at the time of checking the analog conversion circuit output of CH1, the addressing pulse 22
1, ie, NMOSFET M of the inspection switch circuit 5
Gate ₁ goes high and addressing pulse 2
22 to 22n, that is, NMOS of the inspection switch circuit 5
The gate of the FET · M ₂ ~M _n becomes a low level, transistor Q _A1, Q _B1 is turned on, Q _A2 ~Q _An and Q _B1 ~
Q _Bn is turned off, and the base voltage of the transistor Q _A1 , that is, the analog conversion circuit output 401 of CH 1 is output to the output terminal 7 via the current mirror circuit of the transistors Q _P1 and Q _P2 and the output buffer circuit 6. Similarly, at the time of checking the output of the analog conversion circuit of CH2,
Is output to the output terminal 7 and the analog conversion circuit output 40n of CHn is output to the output terminal 7 when the output of the analog conversion circuit of an arbitrary number of channels CHn is checked. In this embodiment, when serial data, a clock pulse, and a load pulse are input from terminals 11 to 13 for adjustment or the like even when inspection is not performed, the output of the analog conversion circuit of the specified channel is output to output terminal 7. However, during normal use after adjustment, nothing is input to the terminals 11 to 13, so that the output terminal 7
Does not output anything.

As described above, according to this embodiment, the inspection switch circuit 5 is provided, and the address designation pulses 221 to 22 of the serial / parallel conversion / address decoder circuit 1 are provided.
n, the addressing pulses 221-2 of the serial / parallel conversion / address decoder circuit 1 are used.
Since the analog conversion circuit outputs 401 to 40n of the channel designated by 2n are selected by the inspection switch circuit 5 and output to one output terminal 7, the output of the output terminal 7 is smaller than when the analog conversion circuit output is not inspected. By adding only one pad, it is possible to inspect only the output of each channel of the DA converter.

In this embodiment, the output terminal 7 is an independent output terminal for testing the output of the analog conversion circuit. However, the output terminal 7 may also be used as another arbitrary output. This will be described as an example. FIG. 2 shows a second embodiment of the present invention.
1 is a block diagram of a DA converter having an arbitrary number of bits, an arbitrary number of channels, and an m-bit n-channel, and portions corresponding to those in FIG. 1 are denoted by the same reference numerals. In the inspection switch circuit 5 of FIG.
Is an arbitrary terminal output, 52 is a mode signal input terminal, M ₀ is an NMOSFET, Q _A0 and Q _B0 are transistors, and R ₀ is a resistor.

The NMOSFET of the inspection switch circuit 5
Gate and M ₁ ~M _n sources low level during inspection of M _0, is usually connected to a mode signal input terminal 52 to provide a high level at the time, the drain of the NMOSFET · M ₀ through a resistor R ₀ of the transistor Q _A0 Emitter and Q
Are connected to _B0 of the emitter, the base of the transistor Q _A0 is connected to any terminal output 51, the collector of the transistor Q _A0 is connected to the collector of Q _A1 to Q _An, to the collector and base of Q _P1, the transistor Q _B0 Are connected to the collectors and bases of the transistors Q _{B1 to} Q _{Bn and} the collector of the transistor Q _P2 , and to the output terminal 7 via the output buffer circuit 6 as the output of the inspection switch circuit 5. The output terminal 7 is also used as another arbitrary output. Except for the above, the configuration is the same as that of FIG.

In FIG. 2, a high-level voltage is applied to the mode signal input terminal 52 during normal operation,
Since also the source of M ₁ ~M _n becomes high level, the gate voltage, ie addressing pulse 221~22n of high-level NMOSFET · M ₁ ~M _n of the test switch circuit 5, the transistors Q _A1 ~ regardless low level Q _An ,
Q _B1 to Q _Bn is turned off, the voltage of the Q _A0, Q _B0 is turned on any terminal output 51 is output to the output terminal 7. Since a low-level voltage is applied to the mode signal input terminal 52 at the time of inspection, the analog conversion circuit output 401 of CH1 is output to the output terminal 7 at the time of the analog conversion circuit output of CH1, as in the case of FIG. Any number of channels C
At the time of the Hn analog conversion circuit output test, the CHn analog conversion circuit output 40n is output to the output terminal 7.

In the DA converter shown in FIG. 2, the output terminal 7 is also used as another arbitrary output. However, since the mode signal input terminal 52 is newly required, the output terminal 7 is one bit smaller than when the output of the analog conversion circuit is not inspected. With the addition of pads, DA
It is possible to check the output of each channel of the converter alone, but if there is a terminal that is always at a high level voltage at any other terminal of the IC,
By using that terminal also as the mode signal input terminal 52, it is possible to inspect the output of each channel of the DA converter alone without adding an external terminal or a test pad as compared with the case where the output of the analog conversion circuit is not inspected. .

Next, a third embodiment of the present invention will be described with reference to the drawings. FIG. 3 shows a configuration diagram of an m-bit n-channel DA converter as a third embodiment of the present invention with an arbitrary number of bits and an arbitrary number of channels. In FIG. 3, 1 is a serial / parallel conversion / address decoder circuit, 2 is a data latch circuit, 3 is an analog conversion circuit, 4 is an adjustment circuit group inside the IC, 5 is a switch circuit for inspection, 6 is an output buffer circuit,
7 is an output terminal, 11 is a serial data input terminal,
12 is a clock pulse input terminal, 13 is a load pulse input terminal, 41 to 4n are adjustment circuits inside the IC, and 211 to 2
1 m is the parallel data output from the serial / parallel conversion / address decoder circuit 1, 221 to 22 n are the address designation pulses of the output from the serial / parallel conversion / address decoder circuit 1, 311 to 3 nm are the latched parallel data, and 401 to 40 n Is an analog conversion circuit output. Further, in the test switch circuit 5, 51 arbitrary pin output, M ₀ ~M _n is NMOSFET, Q _A0 ~
Q _An , Q _B0 -Q _Bn , Q _P1 , Q _P2 are transistors, R _0-
R _n denotes the resistance.

The serial data input terminal 11, the clock pulse input terminal 12, and the load pulse input terminal 13 are connected to the serial / parallel conversion / address decoder circuit 1, and receive the parallel data 211 to 21m of the serial / parallel conversion / address decoder circuit 1. The output is sent to all channels of the data latch circuit 2,
Address designation pulses 221 to 221 of the address decoder circuit 1
The output of 22n is, for example, 221 if the data latch circuit 2
CH1 and NMOSFET M of the inspection switch circuit 5
_First gate, the so on 222, if the data latch circuit 2 of CH2 and the gate of NMOSFET · M ₂ of the test switch circuit 5, NMOSFET · M channel and the test switch circuit 5 to the corresponding data latch circuit 2
_{1 to Mn} are connected to corresponding gates.

Of the parallel data output of each channel of the data latch circuit 2, 311 to 3n (m-1) are, for example, CH1 and CH3 of the analog conversion circuit 3 for 311 to 31m.
21~32m If the so on CH2 of the analog conversion circuit 3 is connected to a channel corresponding each of the analog conversion circuit 3, 3 nm is connected to the gate of the source and NMOSFET · M ₀ of NMOSFET · M ₁ ~M _n I have.

If the output 401 to 40n of each channel of the analog conversion circuit 3 is, for example, 401, the adjustment circuit 41 in the IC and the base of Q _A1 of the inspection switch circuit 5, 402
Then, they are connected to the adjustment circuits 41 to 4n inside the IC and the bases of Q _{A1 to} Q _An of the inspection switch circuit 5, respectively, such as the adjustment circuit 42 inside the IC and the base of Q _A2 of the inspection switch circuit 5. .

Also, the NMOSF of the inspection switch circuit 5
The source of ET · M ₀ is grounded and NMOSFET · M ₀
Drain of ~M _n is connected to each emitter of the emitter and Q _B0 to Q _Bn of each through the resistor R ₀ to R _n transistors Q _A0 to Q _An, the collector of the transistor Q _A0 to Q collector of _An is Q _P1 And bases, and the collectors and bases of transistors Q _B0 -Q _Bn
It is connected to the collector of _P2 and to the output terminal 7 via the output buffer circuit 6 as the output of the inspection switch circuit 5. The output terminal 7 is also used as another arbitrary output.

The DA of this embodiment configured as described above
The operation of the converter will be described below. First,
Serial data is input from the terminal 11 to the serial / parallel conversion / address decoder circuit 1, a clock pulse is input from the terminal 12, and a load pulse is input from the terminal 13 in the case of a three-wire input. The input serial data is sent to the serial / parallel conversion / address decoder circuit 1
The data is converted into m-bit parallel data by a parallel conversion unit, and is converted into a serial / parallel conversion / address decoder circuit 1.
The n-channel address designating pulse is generated by the address decoder section of FIG. Next, the above-described parallel data 211 to 21m are applied to all the channels of the data latch circuit 2, and the addressing pulses 221 to 22 corresponding to the respective channels.
n is input. The parallel data 211 to 21m are supplied to the data latch circuit 2 by the addressing pulses 221 to 21m.
Latched to the channel designated by 22n. Of the parallel data latched in the data latch circuit 2, 311 to 3n (m-1) are analog conversion circuits 3
, And is converted into an analog voltage, and the adjustment circuits 41 to 4n inside the IC can be adjusted by the respective outputs 401 to 40n of the analog conversion circuit 3.

Further, in this embodiment, the data latch circuit 2
In the parallel data latched in the above, an arbitrary data of 3 nm is used as a mode signal, and serial data is input from a terminal 11 so as to have a high level voltage during normal operation and a low level voltage during inspection. high-level voltage is applied to the source and the gate of M ₁ ~M _n of NMOSFET · M ₀ of the test switch circuit 5, NMOSFET · M ₀ of the test switch circuit 5
~ _Mn gate voltage, ie addressing pulse 221
Transistors Q _{A1 to} Q _An and Q _{B1 to} Q _Bn are turned off, Q _A0 and Q _B0 are turned on irrespective of the high level and low level of 〜22n, and the voltage of any terminal output 51 is output to the output terminal 7. You.

At the time of inspection, the NMO of the inspection switch circuit 5
SFET ・ M₀Gate and M₁~ M_nTo the source of
-Level voltage is applied, for example,
At the time of the log conversion circuit output inspection, the addressing pulse 22
1, ie, NMOSFET M of the inspection switch circuit 5
₁Becomes high level and the addressing pulse 2
22 to 22n, that is, NMOS of the inspection switch circuit 5
FET ・ M_Two~ M_nGate goes low,
Transistor Q_A1, Q_B1Turns on and Q_A0, Q_A2~ Q _Anand
Q_B0, Q_B1~ Q_BnTurns off and the transistor Q_P1, Q_P2of
Via the current mirror circuit and the output buffer circuit 6
And Q_A1Base voltage, ie, CH1 analog conversion circuit
The road output 401 is output to the output terminal 7. And so on
Therefore, when checking the output of the analog conversion circuit of CH2,
Of the analog conversion circuit is output to the output terminal 7.
Output of an analog conversion circuit of an arbitrary number of channels CHn
At the time of inspection, the CHn analog conversion circuit output 40n is output.
Output to the force terminal 7.

As described above, according to this embodiment, the inspection switch circuit 5 is provided, and only when the mode signal 3 nm using one of the parallel outputs of the data latch circuit 2 is in the state at the time of the inspection, the serial switching is performed. By using the addressing pulses 221 to 22n of the parallel conversion / address decoder circuit 1, the analog conversion circuit output 40 of the channel specified by the addressing pulses 221 to 22n of the serial / parallel conversion / address decoder circuit 1
1 to 40n are selected by the inspection switch circuit 5, and when the mode signal is in a normal state, it is output to one output terminal which also serves as an arbitrary output terminal of the IC internal circuit. Compared with the case where the circuit output is not inspected, the individual output of each channel of the DA converter can be inspected without adding external terminals or test pads.

At this time, the number of bits of the CHn analog conversion circuit using one of the parallel outputs as a mode signal is reduced to m-1 bits. A so-called serial mode control function that uses some of the parallel outputs 311 to 3 nm of the data latch circuit 2 as some other mode signals, such as switching between a recording mode and a reproducing mode, in the case of an IC for a reproducing apparatus. Therefore, CHn of the data latch circuit 2 may be a channel dedicated to serial mode control. FIG. 4 shows an embodiment (fourth embodiment) in which CHn of the data latch circuit 2 is a channel dedicated to serial mode control. In FIG. 4, C of the data latch circuit 2
Since Hn is a channel dedicated to serial mode control, the number of channels of the analog conversion circuit 3 and the number of adjustment circuits of the adjustment circuit group 4 inside the IC are n-1. The inspection switch circuit 5 also has a configuration corresponding thereto. The other configuration is the same as that of the third embodiment shown in FIG. 3, and the description is omitted.

As described above, according to the first to fourth embodiments, the output of the analog conversion circuit is compared with the case where the output is not inspected.
Te, only the pads for or test pad for an external terminal
One additional to, or without adding their pads, it is possible to check each channel of the DA converter, the increase in IC area due to an increase in the pad, it is not to without increasing the cost, the inspection Thus, an excellent DA converter whose performance can be guaranteed can be realized.

[0034]

DA converter according to claim 1 according to the present invention, the output of the analog conversion circuit of the channel designated by the addressing pulse is selected by the test switch circuit, 1
Output to two (examination-only) external terminals . Therefore , compared to when the output of the analog conversion circuit is not inspected,
By adding one, the characteristics of each channel of the DA converter can be inspected .

Furthermore, DA converter according to claim 2, the
Input the output of the IC internal circuit to the base of transistor 4
Then, a mode signal for switching between the normal mode and the inspection mode is input to the gate of the sixth transistor, and the inspection switch is input.
When the switch circuit is activated, the level
When the mode signal is input, it outputs the output of the internal circuit of the IC to the external terminal. And a level indicating the inspection mode.
When the mode signal of the channel is inputted, the output of the analog conversion circuit of the channel designated by the address designation pulse is outputted to the same external terminal . Accordingly, because it serves the external terminals for inspection and one terminal of the internal circuit of the IC, outside pin for inspection only is not required, that Do requires input terminal of the mode signal. As a result, the mode signal input terminal
By providing, for each of the DA converter channels
Characteristics can be inspected .

Further, in the DA converter according to the present invention, when one of the parallel data outputs of the data latch circuit is used as a mode signal, the inspection switch is operated by the mode signal.
Switch circuit operation between normal operation and inspection.
Instead of being, an input terminal for the mode signal is that Do not required. this
Accordingly, each channel of the D / A converter can be inspected without increasing the number of inspection pads.

Therefore, it is possible to realize an excellent D / A converter capable of guaranteeing the performance by inspection without increasing the area of the IC due to a large increase in the number of external terminals or test pads, and without increasing the cost.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a DA converter according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram of a DA converter according to a second embodiment of the present invention.

FIG. 3 is a configuration diagram of a DA converter according to a third embodiment of the present invention.

FIG. 4 is a configuration diagram of a DA converter according to a fourth embodiment of the present invention.

FIG. 5 is a configuration diagram of a conventional DA converter.

[Explanation of symbols]

Reference Signs List 1 serial / parallel conversion / address decoder circuit 2 data latch circuit 3 analog conversion circuit 4 adjustment circuit group inside IC 5 inspection switch circuit 6 output buffer circuit 7 output terminal 11 serial data input terminal 12 clock pulse input terminal 13 load pulse input terminals 41 to 4n IC internal adjustment circuit 51 any pin output 52 mode signal input terminal 211~21m parallel data 221~22n addressing pulse 311~3nm latched parallel data 401~40n analog conversion circuit output M ₀ ~M _n NMOSFET Q _{A0 to} Q _An , Q _{B0 to} Q _Bn , Q _P1 , Q _P2 Transistor R _{0 to} R _n Resistance

────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Mitsuhiko Otani 1006 Kazuma Kadoma, Kazuma, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (56) References JP-A-5-188113 (JP, A) JP-A-5-188 29938 (JP, A) JP-A-6-94085 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H03M 1/00-1/88 G01R 31/28

Claims (3)

(57) [Claims] And 1. A serial-to-parallel converter for converting serial data to parallel data designated, and an address decoder for creating an address pulse, the parallel data output from the serial-to-parallel converting unit by the addressing pulse a data latch circuit for latching each channel that is, path said latched each channel to a data latch circuit
An analog conversion circuit for converting the parallel data into an analog voltage for each corresponding channel, and an output of the analog conversion circuit for each channel.
A plurality of IC internal adjustment circuits in which force is input correspondingly
And an output of the analog conversion circuit is input to a base.
And the same polarity as the first transistor
A second transistor, diode-connected,
To the common emitter connection point of the first and second transistors.
A third transistor for switching control of current supply;
The differential circuit constituted by
Provided for each channel, and the second
Output signal from the connection point where each base of transistor is connected in common
Test circuit from which the signal is taken out, and an external terminal for outputting an output signal of the test switch circuit
And the third transistor provided for each channel.
One of them is made conductive by the addressing pulse.
Te, DA converter, wherein the benzalkonium to output the output of the analog conversion circuit of the designated channel to the external terminal. 2. Converting serial data into parallel data
A serial-to-parallel converter, an address decoder that creates an addressing pulse, and a parallel-to-parallel output from the serial-to-parallel converter.
The data is stored in the channel specified by the addressing pulse.
A data latch circuit that latches for each channel, and a latch that latches for each channel of the data latch circuit.
Converts parallel data to analog voltage for each corresponding channel
An analog conversion circuit for conversion, and an output of the analog conversion circuit converted for each channel.
A plurality of IC internal adjustment circuits in which force is input correspondingly
And an output of the analog conversion circuit is input to a base.
Transistor having the same polarity as the first transistor
A second diode-connected transistor; and
A source is connected to a ground line and the first and second transistors are connected to each other.
Switch the current supply to the common emitter connection point of the transistor.
Constituted by a third transistor for controlling
A first differential circuit having the same polarity as the first transistor;
And the fourth transistor in which the output of the IC internal circuit is connected to the base.
A transistor having the same polarity as the first transistor
A diode-connected fifth transistor and a saw;
And the gate is connected to the first differential circuit.
And the fourth and fifth
Switch the current supply to the common emitter connection point of the transistors.
A sixth transistor for controlling the switching.
A second differential circuit, wherein the first differential circuit is
The analog conversion circuit is provided for each channel.
And each base and the front of the second transistor.
The connection point where the bases of the fifth transistor are connected in common
Test switch circuit from which an output signal is taken out, and an external terminal for outputting an output signal of the test switch circuit
And the gate input of the sixth transistor and the first
Normally, the potential of the ground line for the differential circuit is set to high level.
Set to low level voltage during inspection
A DA converter characterized by the above-mentioned . 3. A parallel latch latched by a data latch circuit.
Using one of the data
Sometimes high level, low level during inspection
To the gate input of the sixth transistor
3. The DA converter according to claim 2, wherein: