JPS6122292Y2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a logic analyzer, and more particularly to a logic analyzer in which a digital input signal applied to a comparator, a reference voltage and a comparator output can be observed on a cathode ray tube.

The cathode ray tube display waveform in a logic analyzer is determined by comparing the digital input signal under test with a reference voltage or threshold level (hereinafter simply referred to as Vref) applied to a comparator in the logic analyzer. ” was determined. If the voltage level of the digital input signal to be measured differs, Vref must be set accordingly. Therefore, understanding and setting the digital input signal level to be measured and the optimum Vrref is essential for using the logic analyzer. If the circuit under test is composed of elements with a known voltage level, such as ECL or TTL, the Vref in the logic analyzer can be set to the optimum value by switching and selecting it with a changeover switch, etc. There is no problem as it can be configured. However, if the voltage level of the digital input signal under test is unknown, it is necessary to determine the input signal level using an oscilloscope or other level detection means before setting the variable voltage source in the logic analyzer to a predetermined Vref. There were flaws.

Furthermore, in a logic analyzer equipped with a cathode ray tube (hereinafter referred to as CRT), by providing a switching means that automatically switches between the memory output and Vref, the threshold level within the logic analyzer can be adjusted.
A signal observation device that allows observation on a CRT (Japanese Patent Laid-Open No. 52-2354) has been proposed. According to this device, if the minimum droplet Vref to be set for each digital input signal to be measured is known, it has the limited effect of being able to set Vref without using an oscilloscope or voltmeter, but it has the opposite effect. However, when the level of the digital input signal to be measured and the optimum Vref for that signal are unknown, an oscilloscope is still required.

Therefore, the object of the present invention is to develop a new logic that allows the digital input signal to be measured applied to the comparator, the reference voltage applied for comparison, and the comparator output to be alternately applied to the CRT, thereby allowing them to be displayed and observed on the CRT, either alone or simultaneously. The purpose is to provide an analyzer.

An embodiment of the logical analyzer of the present invention will be described in detail below with reference to the drawings.

Figures 1A to 1D show digital input signals and
This is an example in which the mutual relationship of Vref is displayed on a CRT. In Figure 1A, the digital input signal is changing in the "high" and "low" level ranges, so the digital input signal is displayed as a line in the vertical axis direction, as shown in A, and since Vref is at a DC level, it is displayed as a line in the vertical axis direction, as shown in B. Displayed as a dot. If the optimum Vref is set at this time, the comparator output is displayed as a line in the vertical axis direction, as shown in C, according to the digital input signal. Now, if Vref B is set to a voltage higher than the "high" level of the digital input signal A or lower than the "low" level of the digital input signal A, the comparator output C will be at the low or high level points as shown in Figure 1 G and H. becomes. At this time, while observing the CRT tube surface so that the comparator output C is displayed as a line in the vertical axis direction as shown in Figure 1A.
Vref can be adjusted. Furthermore, Figure 1E
As shown in and F, if the digital input signal A is a DC voltage at a "low" or "high" level, the comparator output C also remains at a "high" or "low" level. By observing such a state, it can be determined whether there is a poor contact between the circuit under test and the logic analyzer or whether the circuit under test is not in an operating state, so that the circuit under test can be efficiently measured. Figures B and D show the digital input signals of each channel.
This is another embodiment in which Vref B and comparator output C are arranged and displayed in the horizontal direction, and FIG. 1C is similar to FIGS.
This is another embodiment in which the output of the memory circuit is displayed together with the display as shown in FIG.

FIG. 2 is a simplified block diagram showing an embodiment of a logic analyzer in which first and second selection circuits are added to a conventional logic analyzer. However, it goes without saying that an additional character signal generation circuit is required to display numbers.

In FIG. 2, the first selection circuit 28 is connected to the input terminal 2, 4, 6, 8 of each channel by a signal from the control circuit 20 (the timing of operation is determined by the output of the clock generator 24). digital input signal, Vref set by variable resistor 12 (one case is shown;
(The same number as the number of channels may be prepared) and the output voltage of the comparator 10 are selected. The second selection circuit 30 is connected to the first selection circuit 28 by a signal from the control circuit 20.
and the output voltage of the parallel-to-parallel conversion circuit 16 are selected. Therefore, in order to display a display as shown in FIGS. 1A and 1B on a CRT, the first selection circuit 28 alternately selects the digital input signal of each channel, Vref, and the output voltage of the comparator 10, and selects the second selection circuit 28 alternately. circuit 3
0 selects the output voltage of the first selection circuit 28 and applies it to the vertical positioning circuit 32. Vertical positioning circuit 3
2 generates a vertical positioning signal, and a second selection circuit 3
It is superimposed on the output voltage of 0 and applied to the vertical axis deflection plate of the CRT26. At this time, the horizontal positioning circuit 22, which has the function of generating either a horizontal positioning signal or a horizontal sweep signal, generates a horizontal positioning signal.
Add to the horizontal deflection plate of CRT26. When displaying as shown in Figure 1A, the vertical and horizontal positioning signals are each set to staircase wave voltages, and when displaying as shown in Figure 1B, the horizontal positioning signal is set to staircase wave voltage, and the vertical positioning signal is set to DC voltage. It may be a voltage.

Furthermore, in order to display the display as shown in FIG. Parallel with 16-
It is serially converted and applied to the second selection circuit 30. The second selection circuit 30 alternately selects the output voltage of the first selection circuit 28 and the output of the parallel-to-serial conversion circuit 16 and applies them to the vertical positioning circuit 32 . The vertical positioning circuit 32 generates a vertical positioning signal, superimposes it on the output of the second selection circuit 30, and applies it to the vertical axis deflection plate of the CRT 26. The horizontal positioning circuit 22 generates a horizontal positioning signal when the second selection circuit 30 selects the output of the first selection circuit 28;
When it selects the output of the parallel-to-serial converter circuit 16, it generates a sawtooth wave signal and applies it to the horizontal axis deflection plate of the CRT 26. In this way, the logic analyzer of the present invention does not lose the functions of conventional logic analyzers, but by adding a simple circuit, it can perform other functions, making it an extremely effective device in practice. becomes.

As mentioned above, according to the logical analyzer of the present invention,
By alternately displaying the digital input signal applied to the comparator applied to this logic analyzer, the reference signal of the comparator, and the output signal of the comparator on the CRT 26, the relationship between the signal level under measurement and the reference voltage of the comparator is displayed. Since it can be observed, it is possible to easily and quickly set the optimum Vref, and measurement errors can be reliably removed, which has a remarkable effect in practice. Furthermore, even when the signal level to be measured is unknown, an attached level display means is no longer necessary for optimal Vref setting.
Furthermore, by simultaneously displaying the interrelationship between the unprocessed digital signal to be measured, the reference voltage Vref to the comparator, and the output voltage of the comparator on the CRT in an analog manner, the relationship between the three signals mentioned above becomes clear at a glance. Measurement errors can be prevented.

The above is a detailed description of the preferred embodiment of the present invention, and it will be obvious to those skilled in the art that various modifications and changes can be made without departing from the spirit of the present invention.

For example, the logic analyzer of the present invention is not limited to 4 input channels, but can also be applied to 8 channels, 16 channels, and other various channels.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an example of displaying digital input signals, threshold levels, and comparator outputs on a CRT using the logic analyzer of the present invention;
The figure is a block diagram showing one embodiment of the logical analyzer of the present invention. 2, 4, 6 and 8 are input terminals for each channel, 10 is a comparator, 12 is a variable resistor for adjusting Vref, 14 is a memory circuit, 16 is a parallel-to-serial conversion circuit, 18 is a trigger circuit, and 20 is a control circuit, 22
24 is a clock generator, 26 is a CRT, and 28 is a horizontal positioning circuit that generates a horizontal positioning signal.
30 is a first selection circuit, 30 is a second selection circuit, and 32 is a vertical positioning circuit.

Claims (1)

[Scope of utility model registration request] A comparator that compares a digital input signal with a reference voltage, a memory circuit that stores the output of the comparator, a cathode ray tube that displays the output of the memory circuit, and controls the display of the cathode ray tube and the operation of the memory circuit. a first selection circuit that alternately selects the digital input signal, the reference voltage, and the output of the comparator; and the first selection circuit provided between the storage circuit and the cathode ray tube. A logic analyzer comprising: a second selection circuit that selects the output of the first selection circuit or the output of the storage circuit; and the output of the second selection circuit is displayed on the cathode ray tube.