JPH01227525A - D/a converter - Google Patents

D/a converter

Info

Publication number
JPH01227525A
JPH01227525A JP5396988A JP5396988A JPH01227525A JP H01227525 A JPH01227525 A JP H01227525A JP 5396988 A JP5396988 A JP 5396988A JP 5396988 A JP5396988 A JP 5396988A JP H01227525 A JPH01227525 A JP H01227525A
Authority
JP
Japan
Prior art keywords
converter
digit
low order
resistance
voltage divider
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5396988A
Other languages
Japanese (ja)
Inventor
Yasuhiro Yokozawa
横沢 靖弘
Michiko Koukata
甲方 道子
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC IC Microcomputer Systems Co Ltd
Original Assignee
NEC IC Microcomputer Systems Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC IC Microcomputer Systems Co Ltd filed Critical NEC IC Microcomputer Systems Co Ltd
Priority to JP5396988A priority Critical patent/JPH01227525A/en
Publication of JPH01227525A publication Critical patent/JPH01227525A/en
Pending legal-status Critical Current

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  • Analogue/Digital Conversion (AREA)

Abstract

PURPOSE:To correctly measure the resistance connected in series of a low order digit D/A converter without being influenced with a noise, etc., by providing a switching element to impress a bias potential to the resistance voltage divider of the low order digit D/A converter. CONSTITUTION:The title converter is equipped with a high order digit D/A converter 3 and a low order digit D/A converter 4 to have a high order digit decoder 1 and a low order digit decoder 2 to decode digital data to be inputted and resistance voltage dividers composed of the series connection of plural unit resistances to prepare an analog data value according to the data to be decoded, and with a switch 8 for impressing the bias potential to the resistance voltage divider of the low order D/A converter 4. Consequently, when a signal is given from a test control circuit Q1 so as to turn on the switch 8, the voltage is impressed from a bias power terminal 5 to resistances r1-r256 of the resistance voltage divider of the low order side D/A converter 4. Thus, the accuracy of the resistance can be easily and correctly measured without being influenced by the noise, etc.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、D/A変換装置に関し、特に抵抗分圧方式の
D/A変換装置に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a D/A converter, and particularly to a D/A converter using a resistive voltage division method.

〔従来の技術〕[Conventional technology]

従来、この種の抵抗分圧方式のD/A変換装置は、入力
されたデジタルデータを上位桁と下位桁に分割し、夫々
異なるD/A変換器に入力して、夫々のD/A変換器の
抵抗分圧器によりデジタルデータに応じたアナログデー
タな得て、上位桁と下位桁のアナログデータの相対比を
とった上で加算し、1つのアナログデータを出力させて
いた。
Conventionally, this type of resistive voltage division type D/A converter divides input digital data into upper digits and lower digits, inputs them to different D/A converters, and performs respective D/A conversions. Analog data corresponding to the digital data was obtained using a resistance voltage divider in the device, and the relative ratio of the upper and lower digits of the analog data was calculated and added to output one analog data.

第2図に従来の抵抗分圧方式の16bit  D/A変
換装置を示す、AO〜A15は、デジタルデータの入力
端子であり、入力端子AO〜A7に入力されたデジタル
データは下位桁デコーダに入力され、入力端千人8〜A
15に入力されたデジタルデータは上位桁デコーダに入
力される。下位桁デコーダ2と上位桁デコーダ1はそれ
ぞれ8bitのデジタル入力をデコードする為、それぞ
れ21=256本の出力信号線を持ち、下位桁デコーダ
2の出力信号線256本は、下位桁D/A変換器4に接
続され、上位桁デコーダ1の出力信号線256本は、上
位桁D/A変換器3に接続される。
Figure 2 shows a conventional 16-bit D/A converter using a resistor voltage division method. AO to A15 are input terminals for digital data, and the digital data input to input terminals AO to A7 is input to the lower digit decoder. and input end 1,000 people 8~A
The digital data input to 15 is input to the upper digit decoder. Since the lower digit decoder 2 and the upper digit decoder 1 each decode 8-bit digital input, they each have 21=256 output signal lines, and the 256 output signal lines of the lower digit decoder 2 are used for lower digit D/A conversion. 256 output signal lines of the upper digit decoder 1 are connected to the upper digit D/A converter 3.

上位桁D/A変換器3のアナログ出力と下位桁D/A変
換器4のアナログ出力は加算器6に接続され、その加算
された出力は、出力端子B1に接続される構成となって
いた。
The analog output of the upper digit D/A converter 3 and the analog output of the lower digit D/A converter 4 were connected to an adder 6, and the added output was connected to the output terminal B1. .

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来のD/A変換装置の下位桁D/A変換器4
のフルスケールの値は、上位桁D/A変換装置3の約1
 [:LSBE分である。
Lower digit D/A converter 4 of the conventional D/A converter described above
The full scale value of is approximately 1 of the upper digit D/A converter 3.
[: LSBE.

例えば、バイアス電源5が、5〔v〕の場合には、上位
桁D/A変換器3の1 (:LSB)は、下位桁D/A
変換器4のフルスケールに等しく、この値は、5〔V〕
÷2”;19CmV]である。
For example, when the bias power supply 5 is 5 [V], 1 (:LSB) of the upper digit D/A converter 3 is the lower digit D/A converter 3.
Equal to the full scale of converter 4, this value is 5 [V]
÷2”; 19CmV].

一方、下位桁D/A変換器4の1 (LSB〕は19[
:mV]÷2”#76(μV〕となる。従って、下位桁
のD/A変換器4の直列抵抗の精度を、測定する場合に
、1 [:LSB:]が76〔μV〕と極めて小さい為
、ノイズ等の影響を受は易く、正確な値を測定し難いと
共に、測定に時間がかかるという欠点を有する。
On the other hand, 1 (LSB) of lower digit D/A converter 4 is 19[
: mV] ÷ 2"#76 (μV). Therefore, when measuring the accuracy of the series resistance of the D/A converter 4 of the lower digit, 1 [:LSB:] is extremely 76 [μV]. Since it is small, it is easily affected by noise, etc., and has the disadvantage that it is difficult to measure accurate values and it takes time to measure.

本発明は、下位桁D/A変換器の直列接続された抵抗を
、ノイズ等の影響を受けずに正確に測定することが出来
るD/A変換装置を提供することを目的とする。
SUMMARY OF THE INVENTION An object of the present invention is to provide a D/A converter that can accurately measure series-connected resistances of lower-digit D/A converters without being affected by noise or the like.

〔課題を解決するための手段〕[Means to solve the problem]

本発明のD/A変換装置は、入力されたデジタルデータ
なデコードする上位桁デコーダ及び、下位桁デコーダと
、複数の単位抵抗の直列回路からなる抵抗分圧器によっ
てこれらデコーダによってデコードされたデータに応じ
たアナログデータ値を生成する上位桁D/A変換器及び
、下位桁D/A変換器と、これら、上位桁D/A変換器
と、下位桁D/A変換器のアナログ出力を加算する加算
器と、上位桁および下位桁D/A変換器の抵抗分圧器か
らなる直列回路と下位桁D/A変換器の抵抗分圧器とに
バイアス電位の印加を切り換えるスイッチング素子と、
スイッチング素子の0N10FFを制御する制御回路と
を有している。
The D/A converter of the present invention uses an upper digit decoder for decoding input digital data, a lower digit decoder, and a resistive voltage divider consisting of a series circuit of a plurality of unit resistors to respond to data decoded by these decoders. an upper-digit D/A converter and a lower-digit D/A converter that generate analog data values, and addition that adds the analog outputs of the upper-digit D/A converter and lower-digit D/A converter. a switching element that switches the application of a bias potential to a series circuit consisting of a resistance voltage divider of the upper digit and lower digit D/A converters, and a resistance voltage divider of the lower digit D/A converter;
It has a control circuit that controls 0N10FF of the switching element.

本発明によれば、デコーダによりデコードされたデジタ
ルデータに応じたアナログデータな生成する抵抗分圧器
と、その抵抗分圧器の所定の抵抗接続点と所定の電圧端
子との間に接続されたスイッチとを具備するD/A変換
装置も得られる。
According to the present invention, a resistor voltage divider that generates analog data according to digital data decoded by a decoder, a switch connected between a predetermined resistance connection point of the resistor voltage divider and a predetermined voltage terminal; A D/A conversion device including the following can also be obtained.

〔実施例〕〔Example〕

次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図に、本発明の一実施例を示す。AO〜A15は、
デジタルデータの入力端子であり、入力されたデジタル
データなデコードする上位桁デコーダ1及び、下位桁デ
コーダ2とこれらデコーダによって、デコードされたデ
ータに応じたアナログデータ値を生成する複数の単位抵
抗の直列接続によって構成される抵抗分圧器を有する、
上位桁D/A変換器3及び、下位桁D/A変換器4とこ
れら上位桁D/A変換器3と、下位桁変換器4のアナロ
グ出力を加算する加算器6と、前記下位D/A変換器4
の抵抗分圧器にバイアス電位を印加する為のスイッチ8
とスイッチ8を制御する為のテスト制御回路Q1から構
成されている。
FIG. 1 shows an embodiment of the present invention. AO to A15 are
It is an input terminal for digital data, and includes an upper digit decoder 1 that decodes the input digital data, a lower digit decoder 2, and a plurality of unit resistors connected in series to generate an analog data value according to the decoded data by these decoders. having a resistive voltage divider configured by connecting
The upper digit D/A converter 3, the lower digit D/A converter 4, the adder 6 which adds the analog outputs of these upper digit D/A converters 3 and the lower digit converter 4, and the lower digit D/A converter 4, A converter 4
switch 8 for applying a bias potential to the resistive voltage divider of
and a test control circuit Q1 for controlling the switch 8.

前記、本発明の回路は、従来例、第2図の回路と全く同
じ、動作をし、かつ、テスト制御回路Q1よりスイッチ
8がONするように信号を加えれば、下位側D/A変換
器4の抵抗分圧器の抵抗(rl−r2−・・・−]25
5−]256)にバイアス電源端子5より電圧が印加さ
れ、ノイズ等の影響を受けずに容易に抵抗の精度を正確
に測定することが出来る。
The circuit of the present invention operates exactly the same as the conventional example, the circuit shown in FIG. 4 resistance voltage divider resistance (rl-r2-...-]25
5-] 256) from the bias power supply terminal 5, the accuracy of the resistance can be easily and accurately measured without being affected by noise or the like.

また、上位側D/A変換器3の抵抗分圧器の抵抗の測定
を行なう場合にはテスト制御回路Qlによりスイッチ8
をOFFとして、従来通り上位桁および下位桁D/A変
換器の抵抗分圧器からなる直列回路(r 1−r 2−
”−r 256−R1=−R255−R256)にバイ
アス電位が印加される。
In addition, when measuring the resistance of the resistance voltage divider of the upper side D/A converter 3, the test control circuit Ql controls the switch 8.
is turned OFF, and a series circuit (r 1-r 2-
A bias potential is applied to ``-r256-R1=-R255-R256).

又、実使用時においては、スイッチ8は、不用意に、下
位桁D/A変換器4に電圧が印加されることを防止する
入力保護機能を兼ねている。
Further, during actual use, the switch 8 also serves as an input protection function to prevent voltage from being inadvertently applied to the lower digit D/A converter 4.

〔発明の効果〕 以上説明したように、本発明によれば、下位桁D/A変
換器の両端にバイアス電圧を印加することにより、下位
桁D/A変換器のフルスケールをバイアス電圧まで拡大
することが出来る。この為下位桁D/A変換器の抵抗精
度を高精度で測定することか出来る。
[Effects of the Invention] As explained above, according to the present invention, by applying a bias voltage to both ends of the lower digit D/A converter, the full scale of the lower digit D/A converter can be expanded to the bias voltage. You can. Therefore, the resistance accuracy of the lower digit D/A converter can be measured with high precision.

又、D/A変換器の特性を調べる場合、本発明を用いて
まず下位桁D/A変換器の直線性を測定し、それから下
位桁D/A変換器と上位桁D/A変換器の相対精度を測
定し、上位桁D/A変換器の直線性を測定することによ
って、より高精度な特性の測定が可能になる。
Furthermore, when investigating the characteristics of a D/A converter, first measure the linearity of the lower digit D/A converter using the present invention, and then measure the linearity of the lower digit D/A converter and the higher digit D/A converter. By measuring the relative accuracy and measuring the linearity of the upper digit D/A converter, it is possible to measure the characteristics with higher precision.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明のD/A変換装置の一実施例、第2図は
従来のD/A変換装置である。 AO〜A15・・・・・・デジタルデータ入力端子、B
1・・・・・・アナログデータ出力端子、R1へR25
6゜r1〜r256・・・・・・抵抗、Ql・・・・・
・テスト制御回路、1・・・上位桁デコーダ、2・・・
・・・下位桁デコーダ、3・・・・・・上位桁D/A変
換器、4・・・・・・下位桁D/A変換器、5・・・・
・・バイアス電源端子、6・・・・・・加算器、7・・
・・・・MOS)ランジスタ、8・・川・スイッチ。 代理人 弁理士  内 原   音 81図
FIG. 1 shows an embodiment of a D/A converter according to the present invention, and FIG. 2 shows a conventional D/A converter. AO~A15...Digital data input terminal, B
1...Analog data output terminal, R1 to R25
6゜r1~r256...Resistance, Ql...
・Test control circuit, 1... Upper digit decoder, 2...
...lower digit decoder, 3...upper digit D/A converter, 4...lower digit D/A converter, 5...
...Bias power supply terminal, 6...Adder, 7...
...MOS) transistor, 8... river switch. Agent Patent Attorney Uchihara Oto 81

Claims (1)

【特許請求の範囲】[Claims] デジタルデータをデコードするデコーダと、該デコーダ
によりデコードされたデジタルデータに応じたアナログ
データを生成する電源間に直列に接続された複数の抵抗
を有する抵抗分圧器と、該抵抗分圧器の所定の中間接続
点と、所定電圧端子との間に接続されたスイッチ手段と
を具備することを特徴とするD/A変換装置。
A resistor voltage divider having a plurality of resistors connected in series between a decoder that decodes digital data, a power supply that generates analog data according to the digital data decoded by the decoder, and a predetermined intermediate point between the resistor voltage divider. 1. A D/A converter comprising a switch connected between a connection point and a predetermined voltage terminal.
JP5396988A 1988-03-07 1988-03-07 D/a converter Pending JPH01227525A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5396988A JPH01227525A (en) 1988-03-07 1988-03-07 D/a converter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5396988A JPH01227525A (en) 1988-03-07 1988-03-07 D/a converter

Publications (1)

Publication Number Publication Date
JPH01227525A true JPH01227525A (en) 1989-09-11

Family

ID=12957487

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5396988A Pending JPH01227525A (en) 1988-03-07 1988-03-07 D/a converter

Country Status (1)

Country Link
JP (1) JPH01227525A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0786949A (en) * 1993-09-09 1995-03-31 Nec Corp Digital/analog converter
US6879174B2 (en) 2000-09-29 2005-04-12 Sharp Kabushiki Kaisha Testing method and testing device for semiconductor integrated circuits
JP2008236301A (en) * 2007-03-20 2008-10-02 Nec Electronics Corp D/a converter

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0786949A (en) * 1993-09-09 1995-03-31 Nec Corp Digital/analog converter
US6879174B2 (en) 2000-09-29 2005-04-12 Sharp Kabushiki Kaisha Testing method and testing device for semiconductor integrated circuits
JP2008236301A (en) * 2007-03-20 2008-10-02 Nec Electronics Corp D/a converter

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