JP2663845B2 - Digital to analog converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital-to-analog converter, and more particularly to a resistor string type digital-to-analog converter.

[0002]

2. Description of the Related Art Referring to FIG. 6, which shows a configuration of a conventional resistor string type digital / analog converter, the conventional resistor string type digital / analog converter is connected in series between a reference power supply VREF and ground. 2 ⁿ resistors R, and 2 terminals each having one terminal connected to one end of the resistors R
of ⁿ Suchitchi ^{S (1) ~S (2 n} ), a decoder 60 for conducting one switch from among the switches S (1) to S (2 ⁿ⁾ by the digital input signal VIN, the switch S (1 ) To S (2 ⁿ ) and a buffer amplifier 64 which has the other terminal in common and a non-inverting input. The resistors R1 and R2 adjust the minimum value and the maximum value of the analog output V0 level, respectively, and may be omitted. Also, switches S (1) to S (2 ⁿ )
Is usually composed of MOS transistors, and the output of the decoder 60 is connected to the gate of each switch. Further, the number of resistors R and switches is determined in accordance with the number n of digital input bits.
In the case of 0 bits, 2 ¹⁰ = 1024 resistors R and switches are required.

[0003]

[Problems that the Invention is to Solve The conventional resistance string type digital-to-analog converter, since the number of resistors R and Suchitchi the increase of the digital input bi <br/> Wattage increases, an integrated circuit Is generally arranged as shown in FIG.

That is, as shown in FIG. 7, a resistor network 1 (32 in FIG. 7) in which several tens of resistors are arranged in series and switches (the number of which is the same as the number of resistors constituting the resistor network ). In FIG. 7, 32
) Are repeatedly arranged in the column direction to obtain a resistor and a switch of a desired scale.

As a result, the resistance network is connected to the end of the resistance network 1, that is, the turnback electrode 3 A, so that the parasitic resistance is added in series. The conversion speed of this type of digital-to-analog converter is determined by the time constant of the combined resistance of the resistor strings, the resistance of the switch, and the input capacitance of the switch and the buffer amplifier.
In a digital-to-analog converter having a conversion speed of 00 KHZ, the unit resistance constituting the resistor strings needs to be several tens of ohms. Further, it is necessary to a resistor and a switch of the quantities digital input number of bits you increase 1 bit even the unit resistor for twice (1/2).

On the other hand, since the parasitic resistance value r of the folded return electrode 3A shown in FIG. 7 cannot be reduced unless the interval between the resistance networks 1 is reduced, the parasitic resistance caused by the folded return electrode 3A increases as the number of bits increases in the conventional example. There is a disadvantage that the influence of r is remarkably exhibited. As means for solving such a drawback, there is a method of designing the value of the unit resistance connected to the return electrode 3A to be smaller by the value of the parasitic resistance r.
Alternatively, as shown in FIG. 8, there is a method in which the unit resistances 1A are connected by wirings 3B, and the wirings 3B have the same parasitic resistance value as the return electrode 3A.

The former has a drawback that resistance matching cannot be obtained between an electrode and an impurity diffusion layer or each crystalline silicon film in a semiconductor substrate constituting a unit resistance, and the latter has a drawback that a resistance region is significantly increased. Was.

[0008]

A digital-to-analog converter according to the present invention comprises a decoder for decoding digital input data, a resistor string comprising a series network of a plurality of unit resistors, and connection of any one of the resistor strings. and a switch for selecting the point by the output of the decoder, met digital-to-analog converter generates an analog voltage corresponding to the decoded data by the decoder
The resistor strings are arranged on a semiconductor substrate in a plane.
A data comprising a connecting part for connecting the unit resistance by a metal wiring.
A digital-to-analog converter, wherein the resistor string is
Connected in series to the
Correction resistor network composed of metal wiring and this correction resistor
A correction switch for selecting one of the connection points of the network, the common output of the correction switch, e Bei an adder for adding the common output of the switch connected to the resistor string, the correcting resistor Data generated at the connection of the network
Generates a voltage approximately equal to the digital-to-analog conversion error voltage
To correct the digital / analog conversion error voltage.
It is good .

The digital-to-analog converter of the present invention further comprises a first buffer circuit having a common output of the correction switch as a non-inverting input, and adding the common output of the switch connected to the resistor strings to the addition. A non-inverting input of the adder and an output of the first buffer circuit may be used as an inverting input of the adder.

The digital-to-analog converter of the present invention further comprises a first buffer circuit having a common output of the correction switch as a non-inverting input, and a non-inverting input of a common output of the switch connected to the resistor strings. Wherein the output of the second buffer circuit is used as the non-inverting input of the adder, and the output of the first buffer circuit is used as the inverting input of the adder. Can also. Still further, the digital-to-analog converter of the present invention can be configured by replacing the adder with a differential amplifier.

[0011]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of a resistor string type digital-to-analog converter according to a first embodiment of the present invention.

2 ⁿ resistors R connected in series between reference power supply VREF and ground, and 2 ⁿ switches S (1) to S (S) having one terminal connected to one end of these resistors R
(2 ⁿ ), correction resistors rk connected in series to the 2 ⁿ resistors R connected in series, and i correction switches SK each having one terminal connected to one end of these correction resistors rk.
One of the switches S (1) to S (2 ⁿ ) is made conductive by (1) to SK (i) and the digital input signal VIN to select an analog output corresponding to the digital input signal VIN, Switch S selected
Correction switches SK (1) to SK that output the same correction voltage as the error voltage included in the outputs of (1) to S (2 ⁿ )
A decoder circuit 10 for selecting (i), a buffer circuit 4 having the other terminals of the correction switches SK (1) to SK (i) in common and having a non-inverting input, and switches S (1) to S (1).
The other terminal of S (2n) is made common and used as a non-inverting input.
It comprises an adder 5 and a resistor Rf provided between the inverted input of the adder 5 and the output of the buffer circuit 4.

A resistor R and switches S (1) to S (S)
(2 ⁿ⁾ has become a well arrangement shown in Figure 7 as a conventional example, in the conventional example and cage return part of the resistor network 1 as well (Figure 7 S
The parasitic resistance r due to the electrode 3A (between (32) and S (33)) is included in the circuit diagram in FIG. The output voltage V0 of the digital-to-analog converter according to the present invention can be expressed by the following equation.

[0015]

Here, S: the number of the switch selected by the digital input signal m: the number of the folded return portions included in the resistor strings when the S-th switch is turned on r: the parasitic resistance value of the folded return portion rk: correction resistance Value K: Number of the correction switch that is turned on at the same time when the S-th switch is turned on A: Number of rk r: Current flowing through the resistor strings (1) The term (m · r) i in equation (1) This value changes depending on the ON state of the switches S (1) to S ( 2 ⁿ ), which is the error voltage due to the parasitic resistance, and thus appears as linear distortion in the output. In the present invention, (k · r) in the second term is used.
k) i is designed to be the same as the term (m · r) i, so that the error voltage can be eliminated. That is

[0017]

As a result, (m · r) in the equation (1)
The term of i is deleted and the following equation is obtained.

[0019]

Next, a specific example will be described (Rf / R
i) = 1 When equation (2) indicates that K = 2 m, that is, when the correction resistance rk is twice the value of the parasitic resistance r for each flip-back section, the equation (3) is satisfied. This is because the correction resistance rk is designed as a pattern having a value twice as large as the parasitic resistance r as shown in FIG. 2, or the correction switches SK (1) to SK are alternately provided with the correction resistance rk being the same as the parasitic resistance r. This can be easily realized by selecting (i).

If the correction resistor rk shown in FIG. 2 is formed with the same structure (for example, an aluminum electrode) as the return electrode 3A in FIG. 7, the two can be matched with each other, and the equation (3) is satisfied. The effect can be obtained even if is changed.

Similarly, when (Rf / Ri) = 0.5, k = 3 m from equation (2), that is, the correction resistance rk is three times the parasitic resistance r for each flip-back portion. Should be designed. Further, when K is not a positive multiple of m (Rf / Ri), the value of the correction resistor rk may be designed to a necessary magnification.

Next, a resistor string type digital-to-analog converter according to a second embodiment of the present invention will be described with reference to the drawings.

Referring to FIG. 5 which shows a circuit diagram of a resistor string type digital-to-analog converter according to a second embodiment of the present invention, the digital-to-analog converter of this embodiment is the adder of the first embodiment. 5 is replaced with a differential amplifier 6,
The buffer circuit 4A which has the other terminals of the correction switches SK (1) to SK (i) in common and has a non-inverting input, and the buffer circuits 4 (1) to S (2 ⁿ ) has the other terminals in common and has a non-inverting input. And a resistor Ri provided between the output of the buffer circuit 4B and the non-inverting input of the differential amplifier 6.
A resistor Ri provided between the output of the buffer circuit 4A and the inverting input of the differential amplifier 6, a resistor Rf provided between the non-inverting input of the differential amplifier 6 and the ground, It is composed of a resistor Rf provided between the input and the inverted input.

The analog output voltage V0 of the digital-to-analog converter according to this embodiment is given by the following equation.

[0026]

However, S, m, r, rk, K, A, and i are the same as in equation (1). In this embodiment, if rk = r, K = m (5), the output voltage V0 is included in the output voltage V0. Error voltage can be eliminated and

[0028]

From the condition of equation (5), in this embodiment, K = m,
That is, by setting the correction resistance rk to the same value as the parasitic resistance r for each return operation, the expression (6) is established, and the ratio of the resistance Ri to the resistance Rf is not affected. Therefore, the correction resistance r
There is an effect that the number of k may be prepared as many as the number of the folded back portions of the resistor strings.

Next, a resistor string type digital-to-analog converter according to a third embodiment of the present invention will be described with reference to the drawings.

FIG. 4 is a plan view showing a part of the resistor strings, and is a further reduced and improved version of the resistor strings shown in FIG. 7 described in the above conventional example. That is, the contact 2A and the electrode 3 are arranged at equal intervals (11 in the figure) on the side surface of the resistance network 1.
Are provided, and the potential is divided, thereby removing the contact on the resistance ladder and reducing the area corresponding to the contact. Also, the connection with the neighboring resistance network at the turn-back portion of the resistance network 1 is via a contact and is connected with the return electrode 3A in the same manner as that shown in FIG.

In the case of employing such a pattern, in the conventional example, not only the parasitic resistance of the flip-back part electrode 3A but also the resistance of the contact 2 of the flip-back part is added as a parasitic resistance. And the linearity of the digital-to-analog converter deteriorates.

In this embodiment, the effect described in each of the first and second embodiments can be easily obtained by forming the shape of the correction resistor shown in FIG. 3 in such a pattern. That is, the wiring 2B having the same resistance as the return electrode 3A in FIG.
Distance l from the center line of contact 2A provided on the side of net 1
The correction resistance rk may be constituted by a unit resistance r 'having an interval 1 obtained by subtracting the interval 11 of the center line of the contact 2A that is formed from the sum of 2 and 13 together.

[0034]

Effect of the Invention] above, the present invention as described, a correction resistor network connected to the resistor string series, and the correction switch for selecting one of the compensation resistor network <br/>, the output of the resistor string By adding the output of the correction switch with an adder or a differential amplifier, it is possible to easily remove the error voltage due to the parasitic resistance generated at the flip-back portion when the resistance strings are flipped and arranged. This has the effect of improving the linearity of the digital-to-analog converter and increasing the accuracy of the conversion.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a digital-to-analog converter according to a first embodiment of the present invention.

FIG. 2 is a plan view of a correction resistor of the digital-to-analog converter shown in FIG.

FIG. 3 is a plan view of a correction resistor of a digital-to-analog converter according to a third embodiment of the present invention.

FIG. 4 is a plan view of a resistor string of a digital-to-analog converter according to a third embodiment of the present invention.

FIG. 5 is a circuit diagram of a digital-to-analog converter according to a second embodiment of the present invention.

FIG. 6 is a circuit diagram of a conventional digital / analog converter.

FIG. 7 is a plan view of a resistor string of the conventional digital-to-analog converter shown in FIG. 6;

FIG. 8 is a plan view of another resistor string of the conventional digital-to-analog converter shown in FIG.

[Explanation of symbols]

R Resistance string unit resistance rk Correction resistance S (1) to S (2 ⁿ ) Resistance string switch SK (1) to SK (i) Correction switch 4, 4A, 4B Buffer circuit 5 Adder 6 Differential amplifier 10 Decoder

Claims (4)

(57) [Claims] A decoder for decoding digital input data, a resistor string comprising a series network of a plurality of unit resistors, and a switch for selecting any connection point of the resistor strings by an output of the decoder; met digital-to-analog converter for generating an analog voltage corresponding to the decoded data by the decoder
The resistor strings are arranged on a semiconductor substrate in a plane.
A data comprising a connecting part for connecting the unit resistance by a metal wiring.
A digital-to-analog converter, wherein the resistor string is
Connected in series to the
Correction resistor network composed of metal wiring and this correction resistor
A correction switch for selecting one of the connection points of the network, the common output of the correction switch, e Bei an adder for adding the common output of the switch connected to the resistor string, the correcting resistor Data generated at the connection of the network
Generates a voltage approximately equal to the digital-to-analog conversion error voltage
To correct the digital-to-analog conversion error voltage.
Digital-to-analog converter and said and. 2. A first buffer circuit having a common output of the correction switch as a non-inverting input, wherein a common output of the switch connected to the resistor strings is used as a non-inverting input of the adder. inverting input 請 Motomeko 1 digital-to-analog converter according you of the output of the buffer circuit and the adder. 3. A first buffer circuit having a common output of the correction switch as a non-inverting input, and a second buffer circuit having a common output of the switch connected to the resistor strings as a non-inverting input. , an output of said second buffer circuit and the non-inverting input of said adder, an inverting input and 請 Motomeko 1 digital-to-analog converter according you of the adder output of the first buffer circuit. 4. 請 Motomeko 3 digital-to-analog converter according you configure <br/> replaced with differential increase width vessel the adder.