JP4330232B2 - Current mode D / A converter - Google Patents

Description

この式は、Ｇm1＝４Ｇm2＝３２Ｇm3という関係により、
【数２】

という形に簡略化することが出来る。これは、１２ビットの電流モードＤＡＣについての厳密な式である。
【００２５】
このような関係についてさらに考えると、３個の４ビットの抵抗型ＤＡＣ回路は、入力の組み替えが可能であるので、７ビットの抵抗型ＤＡＣ回路の異なる部分を利用しているのと同じことになる。すなわち、上記のようにＧ_m1＝３２Ｇ_m3で、最大最小のトランスコンダクタンスの比が、３２（＝２5）対１であるので、抵抗型ＤＡＣ回路の抵抗アレイの大きさは、４０９６個から１２８（＝２⁷）個までに減らすことができる。これは、７ビット抵抗型ＤＡＣ回路の１２８個の出力うち、抵抗列の中の中央の１６の隣り合う出力（タップ５６〜７２）をＧ_m3のために用い、Ｇ_m2のために第６４番目までの４個毎の抵抗列の中央部分の出力（タップ３２〜９６）を用い、補助的ペアであるＧ_m1のためには１６個の８個毎の出力（タップ１〜１２８）を用いることにより実現することができる。このようにして抵抗型ＤＡＣをスケールして接続することができる。図３に示した３個の抵抗型ＤＡＣ２４，２５，２６は、図４に示すように１個の抵抗型ＤＡＣ回路２７により置き換えることができる。
【００２６】
この４０９６個の抵抗アレイというのは、実際に用いられる回路としては、ほとんど実現不可能な大きさであるが、このような大きな抵抗アレイに比べて、１２８個の抵抗アレイで済むのであれば、線形性とマッチングも相当に改善される。スイッチやその他の論理回路についても同様なことがいえる。
【００２７】
より正確に言うと、以下に説明するように二つの電圧（以下に説明する実施形態においては電圧比が２であるもの）がトランスコンダクタにおいて使用されるので、上記の７ビットは、トランスコンダクタにある補助ペアが必要とするより大きな電圧（図５のＶ_B ⁺とＶ_B ^-）のための１ビットを加えて８ビットであるべきであるが、トランスコンダクタンスがもっとも小さいトランスコンダクタについては、入力電圧を差動的に行うことを省略しても（作動ペアの一方のみの電圧をすべてのステップにおいて変動させても）支障がないことが分かっているので、１ビットを省略して７ビット、１２８個の抵抗を用いることができる。
【００２８】
図４の実施例においては、１２８個の抵抗器と（２×２×１６）×３＝１９２個のスイッチとを含む単一の抵抗型ＤＡＣ回路２７と、３個のトランスコンダクタ２１，２２，２３とがある。
【００２９】
スイッチの数は、次のようにして計算することができる。以下に述べる本発明のトランスコンダクタにおいて、２個のトランスコンダクタ回路（線形性の余り高くないものでよい）を組み合わせて高い線形性を得ている。この２個のトランスコンダクタ回路は、主トランスコンダクタ回路と補助トランスコンダクタ回路と呼ばれる。差動的構成故にそれぞれのトランスコンダクタ回路用に２個のスイッチが必要であり、結合した線形トランスコンダクタ回路の一つ一つに２個のトランスコンダクタがあり、各トランスコンダクタの片側毎に１６個の状態がある（各トランスコンダクタへと抵抗型ＤＡＣから１６（２⁴）個の電圧端末が接続している）。したがって、各トランスコンダクタに６４個のスイッチが必要であり、これが３個のトランスコンダクタのそれぞれについて必要であるので、３倍して、１９２個のスイッチとなる。
【００３０】
したがって、本発明のＤＡＣによれば、ハードウエアの量を劇的に減少させることが出来、線形性が高められ、必要とされる電力は小さくなり、応答速度も向上する。トランスコンダクタが完全にオフになることは決してないので、信号に対して迅速に応答することが出来る。
【００３１】
上述のＧ_mの比や、抵抗の数、スイッチの数などは、色々な条件のもと当業者が自由に選択でき、またするべきものであり、上記の例示に限定されるものでは全くない。ある入力ビット数が与えられたとき、それに対応するトランスコンダクタの数、トランスコンダクタ比、その他の回路のパラメータは、種々の要素を考慮に入れて設計者が回路の目的に合わせて任意に選択すべきものである。
【００３２】
次に、本発明による線形性の高いトランスコンダクタについて説明する。
従来の方法により線形のＣＭＯＳトランスコンダクタを作り出すことは困難であり、複雑である。また、そのようなトランスコンダクタはフィードバックを用いるので、応答が遅くなりがちである。
【００３３】
これに対し、本発明のトランスコンダクタは線形の動作をするべく単純な数学的概念に基づいて設計されている。これは、抵抗器回路を用いて実施することが出来る。例えば、第１のペア（主ペアあるいは主トランスコンダクタ回路）に△Ｖ_inが入力されるとき、第２のペア（補助ペアあるいは補助トランスコンダクタ回路）には２△Ｖ_inの差動電圧が入力されるようにすることができる。この丁度２という比は、上述の抵抗型ＤＡＣ回路に僅かな改変を加えて公知の方式で簡単に生み出すことが出来る。すなわち、これは、デジタルデコーダからの出力を二組の異なるスイッチに、つまり一つのスイッチの組は抵抗型ＤＡＣ回路の隣り合う抵抗のタップに接続されており、別の組は抵抗型ＤＡＣ回路の一つおきのタップに接続されているようにし、それらの二組にデジタルデコーダからの出力を加えることにより容易に達成することができる。このような抵抗型ＤＡＣ回路は、２×２ⁿ個の抵抗を必要とする点に留意されたい。この比率は任意であり、３，４などの整数値を採用することもできるが、もっとも単純な２という数は、入力電圧を分割する抵抗回路の回路構成を単純化する上で効果があり、好ましい。
【００３４】
本発明のトランスコンダクタの構成例を図５に示す。この図においては、上述のように２つのトランスコンダクタ回路に加えられる電圧の比は２になっており、常に２（Ｖ_A ⁺−Ｖ_A ^-）＝Ｖ_B ⁺−Ｖ_B ^-である（ここで、Ｖ_A ⁺とＶ_A ^-は主トランスコンダクタ回路用であり、Ｖ_B ⁺とＶ_B ^-は補助トランスコンダクタ回路用である）。図５においてまず注目すべきであるのは、２個の差動ペア３１、３２が逆極性に接続されていることである。例えば、第１の差動ペア３１において、Ｖ_A ^-が入力している側のトランジスタ３５のドレインは、Ｖ_B ⁺という極性が反対の電圧が加えられているトランジスタ３６のドレインに接続されている。トランジスタ３７と３８の間でも同様である。
【００３５】
また、トランスコンダクタ回路３１と３２との間でのトランスコンダクタンスの比は、８（Ｗ／Ｌ）とＷ／Ｌまたは８：１である。ここで、Ｗはトランジスターのチャンネル幅、Ｌはチャンネル長であり、しきい電圧Ｖｔとゲート面積あたりのキャパシタンスＣ_ox、荷電移動度ｕが一定であるとき、Ｇ_m＝（１／２）ｕＣ_ox（Ｗ／Ｌ）となるものである。これに対応して、第１差動ペアに接続されている電流源の大きさは第２作動ペアに接続されている電流源の大きさに対する比で、トランスコンダクタンスの比と同様に、８：１になっている。ＭＯＳ回路技術を用いて実際の回路を作成する際には、主トランスコンダクタ回路３１は、Ｗ／Ｌの大きさの８個のトランスコンダクタ回路を並列に接続して実現することが好ましい。このトランスコンダクタンス比の選定は、次のようにすることができる。
【００３６】
一般に、大信号用の差動トランスコンダクタンスを△Ｖについて多項式展開すると、本発明のトランスコンダクタ回路は△Ｖについて差動的に作動するので、△Ｖの奇数乗の項は必要がない。
【００３７】
したがって、
Ｇ_m＝ｇ_m0（１＋ａ₃△Ｖ²＋ａ₅△Ｖ⁴＋・・・）
となる。ｇ_m0は定数であり小信号時のトランスコンダクタンスを示す。ここで、あるトランスコンダクタについて、
△Ｉ_out ^total＝Ｇ_m ^p△Ｖ−２Ｇ_m ⁿ△Ｖ
である。これは、上述のように第１の差動ペアに△Ｖ_inの入力があったとき第２の差動ペアには２△Ｖ_inの電圧がかかるように抵抗器ＤＡＣが構成されており、図５に示すように、第１の差動ペアと第２の差動ペアは逆極性に接続されているので、各ペアを流れる電流の差が合計の電圧となる。
【００３８】
したがって、Ｇ_m ^totalは、
Ｇ_m ^total＝Ｇ_m ^p−２Ｇ_m ⁿ
となる。ここで第１の差動ペアのトランスコンダクタンスをＧ_m ^pで表し、第２の差動ペアのトランスコンダクタンスをＧ_m ⁿで表した。言い換えれば、上付のｐは第１差動ペア、上付のｎは第２差動ペアを表す。
【００３９】
ここで、さらに、
ｇ_m0 ^p＝８ｇ_m0 ⁿ
あるいは、
ｇ_m0 ⁿ＝ｇ_m0 ^p／８
とすると、
【数３】

および
【数４】

となる。ΔＶから独立しており定数である項に到達した。ａ₃を含む項は互いにキャンセルし、ａ₅は通常非常に小さいので、ａ₅，ａ₇などを含む項は無視することができる。したがって、上式における近似はよいものである。全体としてのＧ_mはｇ_m0 ^pの３／４に減っているが、これは線形性を得るために効率が若干犠牲にされたことを意味する。ここで分かるのは、３次調波の影響は完全に打ち消されることである。そして、３次調波よりはるかに小さい５次調波は実用的に無視することができる。したがって、Ｇ_m ^p／Ｇ_m ⁿ＝８という単純な比から、入力信号が大きいときであっても非常に線形性の高いトランスコンダクタとして働く回路を作ることができる。もし、５次調波についても打ち消し合うようにする必要があるときには、ここでは２に固定した第１差動ペアの入力電圧と第２差動ペアの入力電圧の比と、８に設定したｇ_m ^pとｇ_m ⁿの比とを、それぞれ変数として５次調波の項がうち消されるような条件の下で方程式を解くと、これらの変数の値が求まる。そのような値を用いれば、５次調波も消すことができ、さらに線形性が高まるが、回路構成はより複雑になる。
【００４０】
本発明の一つの実施形態においては、これらのトランスコンダクタを差動ペアのユニット回路を用いて構成することができる。これは、回路設計をより容易にし、Ｇ_mの比のマッチングを正確にするための工夫である。第２のトランスコンダクタ（Ｇ_m2）のために８個（主トランスコンダクタ回路用）と１個（補助トランスコンダクタ回路用）のユニット回路を用い、第１のトランスコンダクタ（Ｇ_m1）のために、３２個（主トランスコンダクタ回路用）と８個（補助トランスコンダクタ回路用）のユニット回路を用い、そして、最も小さく、ＬＳＢ（ここでは４ビット）に対応する第３のトランスコンダクタ（Ｇ_m3）については、１個（主トランスコンダクタ回路用）と１／８個（補助トランスコンダクタ回路用）のユニット回路を用いる。むろん、１／８個のユニット回路は製造が単位ユニット回路より困難で、精度が低くなりがちであるが、ＬＳＢに対応するものであるので、実際上は特に問題とならない。しかし、これは、単に回路の設計・製造上の工夫であるので、より高い精度を求める場合や、その他の条件が整えば、どのような数のユニット回路を用いても、またユニット回路を用いなくても、所定のトランスコンダクタンス比さえ達成できればよいことはいうまでもない。
【００４１】
【実施例】
０．６μｍのデジタルＣＭＯＳ技術を用いて、上述の本発明の実施形態にかかる回路を実際に作成した。入力ビット数は１２、この入力ビットを３つに分けて、それぞれ３個の抵抗型ＤＡＣ回路とトランスコンダクタを用いた。本発明の回路に必要な面積は０．７２ｍｍ²であり、駆動電圧は５Ｖ、消費電力は３５０ｍＷ、積分非線形性（ＩＮＬ）は±２ＬＳＢ、微分非線形性（ＤＮＬ）は±１ＬＳＢであった。クロックレート４００ＭＨｚでもデータスルーモードで作動した。最高２．９ナノ秒の立上がり立下がり時間をもつ８チャンネルのテクトロニクス２０３０パターンジェネレータを使用し、４ビットのＬＳＢをグランドして測定した結果、ＴＨＤは−５４ｄＢであり、８ビットのＤＡＣとしては理想に近い結果であった。クロックは２チャンネルのテクトロニクス２０４０パターンジェネレータを使用した。
【００４２】
【発明の効果】
本発明によれば、高解像度で高速の電流モードＤ／Ａ変換器が得られる。グリッチが小さく、精度の高い電流モードＤ／Ａ変換器が得られる。
【図面の簡単な説明】
【図１】本発明の一実施形態による、電流モードＤ／Ａ変換器を模式的に示す。
【図２】本発明の別の実施形態による、ｋ個の抵抗型ＤＡＣとトランスコンダクタを組み合わせた電流モードＤ／Ａ変換器の回路構成を示す。
【図３】本発明の一実施形態による、３個の抵抗型ＤＡＣ回路とトランスコンダクタを組み合わせた電流モードＤ／Ａ変換器のブロックダイヤグラムである。
【図４】本発明の別の実施形態による１個の抵抗型ＤＡＣ回路と３個のトランスコンダクタを組み合わせ電流モードＤ／Ａ変換器のブロックダイヤグラムである。
【図５】本発明のトランスコンダクタの一実施形態を示す回路図である。
【図６】従来のバイナリ型Ｄ／Ａ変換器の原理を示す回路図である。
【図７】従来のセグメント型Ｄ／Ａ変換器の一ユニットセルを示す回路図である。
【符号の説明】
１ 電流モードＤ／Ａ変換器（電流モードＤＡＣ）
２ 抵抗型ＤＡＣ回路
３ デジタルデコーダ
４ トランスコンバータ
５ 抵抗
６ ｎビット入力データ信号[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a high-resolution, high-speed current mode D / A converter (DAC) that converts a digital signal into an analog signal.
[0002]
[Prior art]
Existing current mode high-speed D / A converters (DACs) are known to be binary switch type, segment type, and a combination of binary switch type and segment type. The binary switch type DAC includes many unit current cells. These unit current cells, each functioning as an individual current source, are for processing n-bit digital signals, 1, 2, 4, 8,. . . It is divided into 2n-1 groups, and each group is simultaneously turned on and off. The output current is fed into a small resistor, typically 50 or 75 ohms, to produce a corresponding output voltage. FIG. 6 is a simplified diagram of such a digital-to-analog converter.
[0003]
In FIG. 6, the first group 101 includes one current cell, the second group 102 includes two, the third group 103 includes four, and the number of current cells in each group increases to a power of two. Go. Switches S1, S2, S3,. . . Flows current from the corresponding group of current cells to the output. Switches S1 ', S2', S3 ',. . . Each connects the same group to ground so that it does not take a long time to return to normal operation. The switches are also divided into groups 111, 112, 113 including switch pairs corresponding to the current cell groups. If S1 is on, the LSB (least significant bit) is 1. If S2 is on, the second LSB is 1. If S3 is on, the third LSB is 1. Similarly, if Sn is on, the MSB (maximum significant bit) is 1. If Sn-1 is on, the second MSB is 1.
[0004]
Such a current mode DAC has a drawback that matching is difficult. Considering a 10-bit DAC, 1023 unit current cells are required. In practice, each group can be viewed as a differential pair called current “steering” cells.
[0005]
The advantage of such a DAC is that the configuration of the logic circuit is very simple. However, a disadvantage is that a glitch that is a noise signal at the time of switching becomes large, and nonlinearity due to mismatch of current cells is large. Such a scheme is called a “binary switched” current mode DAC.
[0006]
In addition, a circuit called “segmented” current mode DAC is known. The advantage of this scheme is that the glitch output is considerably reduced and the linearity is considerably improved. This circuit is also composed of many unit current cells, and these unit current cells 121 are formed by combining a current source and two switches. One circuit shown in FIG. 7 corresponds to one digital signal, and the illustrated circuit can be considered as a circuit for LSB that directly corresponds to one digital signal. In such a segmented current mode DAC, the unit current cells 121 are turned on and off one by one, not as a group. The input n-bit data signal is converted to 2 by a logic circuit.ⁿ-Converts to one digital signal. The unit current cell is turned on / off by an individual digital signal generated as a result of this conversion. This n-bit signal is 2ⁿA decoder logic circuit that converts to −1 signal must occupy a very large hardware area and consumes a large amount of power.
[0007]
[Problems to be solved by the invention]
Therefore, a high resolution DAC having a large value of n usually uses a combination of the binary switch type and segment type circuits to reduce the required hardware. However, as a result, especially in a high-speed and high-resolution DAC, signal glitches and nonlinearity increase. Furthermore, since the number of unit current cells is large, the circuit layout becomes complicated and there is a problem that a large area is required.
[0008]
It can be said that the cause of such a problem of the prior art is mainly that the current cells are turned on and off discontinuously. In other words, the conventional current mode DAC has a problem in that the current of the current cell flows to 100% output or 100% ground. Therefore, the current cell or the differential pair in the current cell receives a very large signal at its input and is exposed to large current fluctuations at the “common source” point of the differential pair, which causes nonlinearity and glitches. It was a reason to grow.
[0009]
An object of the present invention is to provide a new circuit configuration for solving the above problems.
[0010]
[Means for Solving the Problems]
The present invention provides a high-speed current mode DAC configured by combining a resistive DAC circuit including a digital decoder circuit and a highly linear transconductor.
[0011]
In the current mode DAC of the present invention, the differential pair or transconductor is not completely turned on or off. In other words, the present invention positively utilizes an intermediate state between on and off in the transconductor. Each differential pair will transition in steps from the most on state to the most off state over the entire input range. In this sense, the current mode DAC of the present invention adopts an analog approach. Moreover, the fluctuation of the voltage input to each switch is relatively low. Therefore, the glitch that becomes a problem can be reduced.
The present invention also provides a highly linear transconductor. This transconductor obtains high linearity by using two differential pairs that are not necessarily high in linearity.
[0012]
More specifically, the present invention includes (1) a digital decoder circuit that receives a digital input signal, a plurality of switches that are turned on or off in response to an output from the digital decoder circuit, and a plurality of resistors connected in series. A resistance type D / A conversion circuit including a resistor whose respective nodes are connected to the output of the resistance type D / A conversion circuit via the switch, and the resistance type D / A conversion circuit A current-mode D / A converter including a highly linear transconductor that receives a voltage output from the power supply and provides a current output; and (2) coupled at the output node, and the polarity of the input voltage is between the following pairs: The first MOS transistor operating pair, the second MOS transistor operating pair, and the first and second transistor operating pairs having different transconductance values, respectively. A coupled MOS transformer in which the signal voltage applied to the first and second pairs is proportional to the signal voltage input to the transconductor but has a different value. A conductor and (3) a current mode D / A converter according to (1) using such a transconductor are provided.
[0013]
Such a transconductor can be manufactured using bipolar or CMOS technology, but in practice, a MOS transistor can be preferably used. The first operating transistor pair can be formed by combining a plurality of operating pairs having the same characteristic value as the second operating pair. When the first operating pair is formed by using a plurality of operating pairs having the same characteristic values as the second operating pair and these pairs are connected in parallel, the matching of the circuit is improved and the error is small.
[0014]
The current mode D / A converter of the present invention may include one resistance type D / A conversion circuit and a plurality of transconductors. Preferably, a single resistance type D / A conversion circuit smaller than the actual number of input digital bits can be used. This can be achieved, for example, by using different parts of a single 7-bit resistive D / A converter circuit for a 12-bit digital signal.
[0015]
Furthermore, the current mode D / A converter of the present invention can include a plurality of resistance type D / A conversion circuits and a plurality of transconductors. These resistance type D / A conversion circuits and transconductors form a plurality of pairs, and each of these pairs performs D / A conversion on a plurality of bits included in an n-bit digital signal input. For example, a 10-bit input can be split in two so that 5 bits are processed by each pair, and a 12-bit input is split in three so that 4 bits are processed by each pair Various combinations are conceivable, such as a 15-bit input divided into three and 5 bits processed by each pair.
[0016]
In the above-described transconductor, the ratio of the conductance of the first transistor differential pair to the conductance of the second transistor differential pair is substantially 8: 1, and is input to the first transistor differential pair and the second transistor differential pair. The ratio of the signal voltages to be performed can be substantially 1: 2. At this time, the current source connected to the first differential pair can be eight times the current source connected to the second differential pair. Preferably, the first pair of current sources is the second pair, just as the first pair of transistors in the transconductor can be configured with transistors having the same characteristics as the transistors used in the second pair. Eight current sources having the same characteristics as the current sources of the transistor operating pair and connected in parallel to each other can be used. Again, matching is facilitated by forming current sources of different capacitances using the same unit transistor.
[0017]
BEST MODE FOR CARRYING OUT THE INVENTION
As shown in FIG. 1, the basic embodiment of the current mode DAC 1 of the present invention includes a resistive DAC circuit 2 including a digital decoder circuit 3 and a transconductor 4 having a very high linearity. is there. When an n-bit digital signal is input from the left, the n-bit digital decoder circuit 3 outputs 2ⁿOne of the switches is selected corresponding to the input signal. Since the digital decoder circuit 3 used here is generally well known, description thereof is omitted here. 2ⁿIf any of the switches are on, 2ⁿBy the resistors 5 having the same resistance value connected in series, V_ref ⁺-V_ref ^-To V_ref ^--V_ref ⁺2 of the rangeⁿAn output voltage corresponding to any one of the voltage values is output from the resistive DAC circuit 2. This is converted into a current output by a transconductor 4 having a very high linearity, which will be described later. In FIG. 1, only four switches and four resistors are shown, but it goes without saying that the above-mentioned number of switches and resistors are originally included.
[0018]
FIG. 2 shows an embodiment of the present invention that is preferable for a high-accuracy DAC having a relatively large number of input bits. This DAC has k transconductors 11 having very high linearity. The configuration of the transconductor 11 will be described in detail later. Each transconductor 11 is capable of converting an analog input voltage into a differential current with high linearity. This differential current (Im + −Im−) (m = 1,..., K) is proportional to the value of the corresponding input bit. The output of the resistor DAC circuit 13 including the digital decoder circuit 12 to which a digital signal is input is connected to the input of the transconductor via a switch.
[0019]
If only one transconductor is used, in an n-bit DAC, the digital decoder is 2 × 2ⁿ2 to control one switchⁿOutputs are required. If n is 10, 1024 signals and 2048 switches are required. This is not realistic in terms of hardware amount. A bigger problem is the size of the resistor array. For example, when n = 10, 1024 resistors are required. Thus, when the number of resistors in the resistor array is increased, the linearity is critically deteriorated, apart from the problem of hardware amount.
[0020]
Therefore, n bits are appropriately divided into a plurality of groups, and an appropriate combination of transconductor and resistor DAC circuit is used for each group. In FIG. 2, n = n for an input n-bit signal.₁+ N₂+. . . + N_kIt is.
[0021]
According to the present invention, a plurality of transconductors can be used, for example, for a 12-bit DAC. In the example shown in FIG. 3, three (k = 3) transconductors 21, 22, and 23 are used. In this case, each transconductor converts a 4-bit data signal into one differential signal. As shown in FIG. 3, a 12-bit input data signal is converted into a 4-bit maximum significant bit (MSB) signal, a 4-bit intermediate significant bit (MidB) signal, and a 4-bit least significant bit (LSB) signal. The 4-bit signal is converted by one transconductor. Therefore, the number of resistors in the resistor array in each of the three resistive DAC circuits 24, 25, and 26 is only 16, and the number of switches can be reduced to 16.
[0022]
Therefore, the above-described output differential current ΔI₁= I₁ ⁺-I₁ ^-Is proportional to the value of the four most significant bits, and the next 4-bit differential output voltage is ΔI₂= I₂ ⁺-I₂ ^-It becomes. The same applies to the third 4 bits. As will be described below, since this transconductor has high linearity, matching every 4 bits using the same transconductor is guaranteed. In practice, resistance matching is the limit of linearity. Therefore, the linearity is improved by increasing the number of bits of the upper transconductor.
[0023]
Here, if all transconductors have the same transconductance (G_m1= G_m2= G_m3) 2¹²Requires one resistive DAC circuit (digital decoder circuit), or the reference voltage of each resistive DAC circuit is V_ref ⁺And V_ref ^-Will be different and with the required accuracy V_ref ⁺And V_ref ^-Cannot be generated.
[0024]
For example 2^Four= 2 even when several relatively large resistive DAC circuits comprising 16 resistors are used.¹²= The number of resistors in each circuit is extremely small compared to using a resistive DAC circuit composed of 4096 resistors. Therefore, a different Gm value is used. Here, for example, G_m1= 4G_m2= 32G_m3And Of course, the number of transconductors, the ratio of transconductance, the size of the digital decoder circuit, etc. can all be selected by the designer as needed. It can be seen that the selection is preferable. When the total differential output current is ΔI, ΔI is expressed as follows.
[Expression 1]

This equation is based on the relationship Gm1 = 4Gm2 = 32Gm3.
[Expression 2]

Can be simplified. This is an exact equation for a 12-bit current mode DAC.
[0025]
Considering this relationship further, the three 4-bit resistive DAC circuits can be rearranged, so that it is the same as using different parts of the 7-bit resistive DAC circuit. Become. That is, G_m1= 32G_m3Since the ratio of the maximum and minimum transconductance is 32 (= 25) to 1, the size of the resistance array of the resistive DAC circuit is 4096 to 128 (= 2).⁷) It can be reduced to pieces. This is because the center 16 adjacent outputs (tap 56 to 72) in the resistor string among the 128 outputs of the 7-bit resistor type DAC circuit are G_m3Used for G_m2For each of the four resistor strings up to the 64th (for example, taps 32 to 96),_m1Can be realized by using 16 outputs (tap 1 to 128). In this way, the resistive DAC can be scaled and connected. The three resistive DACs 24, 25, and 26 shown in FIG. 3 can be replaced by a single resistive DAC circuit 27 as shown in FIG.
[0026]
The 4096 resistor array is almost impossible to realize as a practical circuit, but if only 128 resistor arrays are required compared to such a large resistor array, Linearity and matching are also significantly improved. The same is true for switches and other logic circuits.
[0027]
More precisely, as described below, since two voltages are used in the transconductor (in the embodiment described below, the voltage ratio is 2), the above 7 bits are applied to the transconductor. The larger voltage required by an auxiliary pair (V in FIG. 5)_B ⁺And V_B ^-) Should be 8 bits, but for transconductors with the lowest transconductance, the differential input voltage may be omitted (the voltage of only one of the working pairs) Since it is known that there is no problem (even if it is changed in all steps), 7 bits and 128 resistors can be used by omitting 1 bit.
[0028]
In the embodiment of FIG. 4, a single resistive DAC circuit 27 including 128 resistors and (2 × 2 × 16) × 3 = 192 switches, three transconductors 21, 22, There are 23.
[0029]
The number of switches can be calculated as follows. In the transconductor of the present invention described below, high linearity is obtained by combining two transconductor circuits (which may not be so high in linearity). These two transconductor circuits are called a main transconductor circuit and an auxiliary transconductor circuit. Because of the differential configuration, two switches are required for each transconductor circuit, each of the coupled linear transconductor circuits has two transconductors, 16 on each side of each transconductor. (From each resistive conductor to a resistive DAC 16 (2^Four) Voltage terminals are connected). Therefore, 64 switches are required for each transconductor, and this is necessary for each of the 3 transconductors. Therefore, the number of switches is tripled to 192 switches.
[0030]
Therefore, according to the DAC of the present invention, the amount of hardware can be drastically reduced, the linearity is enhanced, the required power is reduced, and the response speed is also improved. Since the transconductor is never completely turned off, it can respond quickly to the signal.
[0031]
G mentioned above_mThe ratio, the number of resistors, the number of switches, and the like can be freely selected by those skilled in the art under various conditions, and should not be limited to the above examples. Given a certain number of input bits, the corresponding number of transconductors, transconductor ratio, and other circuit parameters should be arbitrarily selected by the designer to suit the purpose of the circuit, taking into account various factors. Kimono.
[0032]
Next, a highly linear transconductor according to the present invention will be described.
Creating a linear CMOS transconductor by conventional methods is difficult and complex. Also, such transconductors use feedback and tend to be slow in response.
[0033]
On the other hand, the transconductor of the present invention is designed based on a simple mathematical concept for linear operation. This can be done using a resistor circuit. For example, ΔV is applied to the first pair (main pair or main transconductor circuit)._inIs input to the second pair (auxiliary pair or auxiliary transconductor circuit)._inCan be input. This ratio of just 2 can be easily generated in a known manner with a slight modification to the above resistive DAC circuit. That is, this is because the output from the digital decoder is connected to two different sets of switches, that is, one set of switches is connected to the adjacent resistor tap of the resistive DAC circuit and the other set is connected to the resistive DAC circuit. This can be easily accomplished by connecting to every other tap and adding the output from the digital decoder to the two sets. Such a resistive DAC circuit is 2 × 2ⁿNote that one resistor is required. This ratio is arbitrary, and an integer value such as 3 or 4 can be adopted. However, the simplest number 2 is effective in simplifying the circuit configuration of the resistance circuit that divides the input voltage. preferable.
[0034]
A configuration example of the transconductor of the present invention is shown in FIG. In this figure, as described above, the ratio of the voltages applied to the two transconductor circuits is 2, and is always 2 (V_A ⁺-V_A ^-) = V_B ⁺-V_B ^-(Where V_A ⁺And V_A ^-Is for the main transconductor circuit, V_B ⁺And V_B ^-Is for auxiliary transconductor circuits). It should be noted first in FIG. 5 that the two differential pairs 31, 32 are connected in reverse polarity. For example, in the first differential pair 31, V_A ^-The drain of the transistor 35 on the input side of_B ⁺Is connected to the drain of the transistor 36 to which a voltage of opposite polarity is applied. The same applies between the transistors 37 and 38.
[0035]
The transconductance ratio between the transconductor circuits 31 and 32 is 8 (W / L) and W / L or 8: 1. Where W is the channel width of the transistor, L is the channel length, threshold voltage Vt and capacitance C per gate area._oxWhen the charge mobility u is constant, G_m= (1/2) uC_ox(W / L). Correspondingly, the magnitude of the current source connected to the first differential pair is a ratio to the magnitude of the current source connected to the second working pair, as with the transconductance ratio, 8: It is 1. When an actual circuit is created using MOS circuit technology, the main transconductor circuit 31 is preferably realized by connecting eight transconductor circuits of W / L in parallel. This transconductance ratio can be selected as follows.
[0036]
In general, when the differential transconductance for large signals is expanded in terms of ΔV, the transconductor circuit of the present invention operates differentially with respect to ΔV, so that an odd power term of ΔV is not necessary.
[0037]
Therefore,
G_m= G_m0(1 + a_Three△ V²+ A_Five△ V^Four+ ...)
It becomes. g_m0Is a constant and indicates the transconductance at the time of a small signal. Here, for a certain transconductor,
△ I_out ^total= G_m ^p△ V-2G_m ⁿ△ V
It is. This is because ΔV is applied to the first differential pair as described above._in2ΔV for the second differential pair when_inAs shown in FIG. 5, the first and second differential pairs are connected in opposite polarities, so that the current flowing through each pair is configured. The difference is the total voltage.
[0038]
Therefore, G_m ^totalIs
G_m ^total= G_m ^p-2G_m ⁿ
It becomes. Where the transconductance of the first differential pair is G_m ^pAnd the transconductance of the second differential pair is G_m ⁿExpressed in In other words, the superscript p represents the first differential pair, and the superscript n represents the second differential pair.
[0039]
Where
g_m0 ^p= 8g_m0 ⁿ
Or
g_m0 ⁿ= G_m0 ^p/ 8
Then,
[Equation 3]

and
[Expression 4]

It becomes. A term which is independent of ΔV and is a constant has been reached. a_ThreeTerms that contain cancel each other and a_FiveIs usually very small, so a_Five, A₇Terms that contain etc. can be ignored. Therefore, the approximation in the above equation is good. G as a whole_mIs g_m0 ^pThis means that some efficiency has been sacrificed to achieve linearity. It can be seen that the effect of the third harmonic is completely cancelled. A fifth harmonic much smaller than the third harmonic can be practically ignored. Therefore, G_m ^p/ G_m ⁿFrom a simple ratio of = 8, it is possible to create a circuit that works as a highly linear transconductor even when the input signal is large. If it is necessary to cancel out the fifth harmonic, here, the ratio of the input voltage of the first differential pair fixed to 2 to the input voltage of the second differential pair, and g set to 8_m ^pAnd g_m ⁿWhen the equation is solved under the condition that the fifth-order harmonic term is eliminated by using the ratio of each as a variable, the values of these variables are obtained. If such a value is used, the fifth harmonic can be eliminated and the linearity is further improved, but the circuit configuration becomes more complicated.
[0040]
In one embodiment of the present invention, these transconductors can be configured using differential pair unit circuits. This makes circuit design easier and G_mThis is a device for making the ratio matching of the above accurate. Second transconductor (G_m28) (for the main transconductor circuit) and one (for the auxiliary transconductor circuit) unit circuit for the first transconductor (G_m1A third transconductor that uses 32 (for the main transconductor circuit) and 8 (for the auxiliary transconductor circuit) unit circuit and is the smallest and corresponds to the LSB (here 4 bits) (G_m3), One (for main transconductor circuit) and 1/8 (for auxiliary transconductor circuit) unit circuits are used. Of course, the 1/8 unit circuit is more difficult to manufacture than the unit unit circuit and tends to be less accurate. However, since it corresponds to LSB, there is no particular problem in practice. However, this is just a device design / manufacturing device, so if more accuracy is required or other conditions are met, any number of unit circuits can be used. Needless to say, it is only necessary to achieve a predetermined transconductance ratio.
[0041]
【Example】
A circuit according to the above-described embodiment of the present invention was actually created using a 0.6 μm digital CMOS technology. The number of input bits was 12, and this input bit was divided into three, and three resistive DAC circuits and transconductors were used. The area required for the circuit of the present invention is 0.72 mm.²The drive voltage was 5 V, the power consumption was 350 mW, the integral nonlinearity (INL) was ± 2 LSB, and the differential nonlinearity (DNL) was ± 1 LSB. It operated in data through mode even at a clock rate of 400 MHz. Using an 8-channel Tektronix 2030 pattern generator with a rise / fall time of up to 2.9 nanoseconds and measuring with 4-bit LSB grounded, the THD is -54 dB, ideal as an 8-bit DAC. The result was close to. The clock used was a 2-channel Tektronix 2040 pattern generator.
[0042]
【The invention's effect】
According to the present invention, a high-resolution and high-speed current mode D / A converter can be obtained. A current mode D / A converter with a small glitch and high accuracy can be obtained.
[Brief description of the drawings]
FIG. 1 schematically illustrates a current mode D / A converter according to an embodiment of the present invention.
FIG. 2 shows a circuit configuration of a current mode D / A converter combining k resistive DACs and a transconductor according to another embodiment of the present invention.
FIG. 3 is a block diagram of a current mode D / A converter combining three resistive DAC circuits and a transconductor according to an embodiment of the present invention.
FIG. 4 is a block diagram of a current mode D / A converter combining one resistive DAC circuit and three transconductors according to another embodiment of the present invention.
FIG. 5 is a circuit diagram showing an embodiment of a transconductor of the present invention.
FIG. 6 is a circuit diagram showing the principle of a conventional binary D / A converter.
FIG. 7 is a circuit diagram showing one unit cell of a conventional segment type D / A converter.
[Explanation of symbols]
1 Current mode D / A converter (current mode DAC)
2 Resistive DAC circuit
3 Digital decoder
4 Transformer converter
5 resistance
6 n-bit input data signal

Claims (3)

  A first MOS transistor differential pair and a second MOS transistor differential pair coupled with each other at the output node, the input voltages having opposite polarities, and having different transconductance values; A different current source connected to each of the MOS transistor differential pairs, and the signal voltages applied to the first and second pairs are proportional to but different from the signal voltage input to the transconductor A coupled MOS transconductor having a value.   The ratio of the conductance of the first transistor differential pair to the conductance of the second transistor differential pair is 8: 1, and the ratio of the signal voltages input to the first transistor differential pair and the second transistor differential pair is 1: The transconductor according to claim 1, which is 2. The second MOS transistor differential pair has a device size of W / L, a current source value of I and a certain signal input voltage, and the first MOS transistor differential pair has a second Each device has the same device size and current source value as the MOS transistor differential pair, and the input signal voltage is half the input value of the second MOS transistor differential pair, and is connected in parallel at the output terminals of each other. And the polarity of the input signal voltage is inverted between the first MOS transistor differential pair and the second MOS transistor differential pair. The current signal of the MOS transistor differential pair and the current signal of the second MOS transistor differential pair have opposite directions and are in a relationship of subtracting each other. Coupled MOS transconductor according to.

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