KR100727885B1 - 10 bit digital/analog converter with new deglitch circuit and new 2-dimensionally hierarchical symmetric centroid switching order - Google Patents

Abstract

The present invention relates to a D / A converter using CMOS. In particular, the complexity of the thermometer decoder in order to satisfy the dynamic specification that fluctuates depending on the frequency characteristics in the D / A converter for image processing while the structure does not change significantly. The lower 6 bits are the centered current cell matrix structure, the lower 4 bits are the weighted current array structure, and 10-bit for image processing using a new switching method that extends hierarchical symmetric switching in two dimensions, and designing a glitch suppression circuit with symmetrical outputs to satisfy both static and dynamic characteristics Providing a D / A converter also improves frequency performance and eliminates the need for additional compensation circuit design within the current cell matrix. Try to maintain 10 bits of linearity.

Glitching Circuit, Current Cell, Glitch Suppression

Description

10-bit DIGITAL / ANALOG CONVERTER WITH NEW DEGLITCH CIRCUIT AND NEW 2-DIMENSIONALLY HIERARCHICAL SYMMETRIC CENTROID SWITCHING ORDER}             

1 is an overall circuit diagram of a 10-bit D / A converter designed in accordance with the present invention.

2 is a proposed glitch energy suppression circuit diagram according to the present invention.

3 is an exemplary input / output waveform of a glitch glitch energy suppression circuit proposed according to the present invention.

4 is an exemplary D & D_bar waveform and a U & U_bar waveform of the proposed glitch glitch energy suppression circuit according to the present invention.

5 is a characteristic curve of the proposed glitch suppression circuit according to the present invention.

6 illustrates a new two-dimensional current cell switching sequence proposed in accordance with the present invention.

7 is a circuit diagram of a current source bias circuit according to the present invention.

8 is an upper bit (1MSB) switch current source circuit diagram.

9 is a lower bit (1, 2, 4, 8 MSB) switch current source circuit diagram.

The present invention relates to a D / A converter using CMOS, and more particularly, to a 10-bit D / A converter.

Recent developments in wireless communication, voice, image signal processing (Voice, Image Signal Processing), asymmetric digital subscriber line (ADSL), measurement equipment (Measurement Equipment), etc. In addition to the static resolution of resolution and speed, which are important in D / A converters for audio and audio signal processing, dynamic specifications are also important.

In general, the dynamic specification is a frequency characteristic, and is expressed in bandwidth and signal to noise (spurious free dynamic range).

Therefore, CMOS current-driven D / A converters have the advantages of low voltage and low power consumption while enabling high-speed operation, but high resolution applications are limited due to process variable mismatch and current source mismatch. The disadvantage is that energy is limited in frequency performance.

In particular, D / A converters designed for image processing have excellent speed and resolution, but have a disadvantage in that signal-to-noise ratio performance decreases rapidly with higher frequencies. October IEEE J. Solid-State Circuits, vol. 35, pp.1841-1852, AR Bugeja, BS Song, "A Self-Trimming 14b 100MS / s CMOS DAC" is recommended to use a calibration circuit, but this is due to the additional circuitry This has the disadvantage of increasing design complexity and time.

See also S. Chin, and C. Wu, "A 10-b 125-MHz CMOS Digital-to-Analog Converter with Threshold-Voltage Compensated Current source," IEEE J. Solid-State Circuits , vol. 29, pp. 1374-1380, Nov. 1994. and Reference 2 (T. Wu, C. Jih, J. Chen, and C. Wu, "A low glitch 10-bit 75-MHz CMOS Video D / A converter ". When designing a glitch suppression circuit referred to in IEEE J. Solid-State circuits , pp. 68-72 Jan. 1995. There was also a problem of causing a current source error due to the use.

Many switching methods have been proposed to reduce random and graded and symmetrical errors caused by process and structural problems.

However, the research results show that the proposed switching method is not effective in the matrix structure due to the one-dimensional, two-dimensional, non-row and column errors, and structural limitations of the row and column decoders. Many have been announced.

 An object of the present invention for solving the above problems is directed to a D / A converter using CMOS, in particular, the structure of the D / A converter for image processing changes in the structure while satisfying the dynamic specification that fluctuates depending on the frequency characteristics In order to reduce the complexity of the thermometer decoder, a mixed structure scheme that reduces linearity and guarantees linearity, the upper 6 bits are the central current cell matrix structure, and the lower 4 bits are the weighted current. The present invention provides a 10-bit D / A converter for image processing having an array structure.

In addition, another object of the present invention to solve the above problems is to use a new switching method that extends the two-dimensional hierarchical symmetric switching (Dimension) hierarchical structure in the current cell matrix A 10-bit D / A converter for image processing to maintain 10-bit linearity without additional correction circuit design.

In addition, another object of the present invention to solve the above problems is to improve the frequency performance, 10-bit D / A for image processing that employs a glitch suppression circuit with a symmetrical output to satisfy both static and dynamic characteristics To provide a converter.

A feature of the 10-bit D / A converter for image processing according to the present invention for achieving the above object is to divide the input digital binary data into upper bits and lower bits, but to reduce the glitch energy and increase monotonism by receiving the upper bits of data. An upper bit thermometer decoder that converts the thermometer code into a 64-bit form to increase the sex; A delay element for receiving a lower bit and delaying the upper bit during an operation time of the upper bit thermometer decoder; A first glitch energy suppression circuit that receives the output signal of the higher-bit thermometer decoder and delays the signal when converting the logic state to convert the signal so that glitches are not generated and output the converted signal; A second glitch energy suppression circuit which receives the output signal of the delay element and converts the signal to delay the signal during conversion of the logic state so that the glitch does not occur; A binary weighted current source of a lower bit that converts the signal received from the second glitch energy suppression circuit into a current and outputs the converted digital value to an analog value; And a higher-order thermometer code current source matrix for converting the signal received from the first glitch energy suppression circuit into a current and outputting the converted digital value to an analog value, wherein the current source matrix includes a two-dimensional hierarchical structure and It has a symmetrical switching order.

An additional feature of the 10-bit D / A converter for image processing according to the present invention for achieving the above object is that the output signal of the higher-bit thermometer decoder receives the first glitch energy suppression circuit in synchronization with an arbitrary drive clock A first latch delivered to; And a second latch configured to receive the output signal of the delay element in synchronization with the driving clock of the first latch and to deliver the output signal to the second glitchy energy suppression circuit.

An additional feature of the 10-bit D / A converter for image processing according to the present invention for achieving the above object is that the higher-bit thermometer decoder uses a 6-bit thermometer decoder.

An additional feature of the 10-bit D / A converter for image processing according to the present invention for achieving the above object is that the upper bit thermometer code current source matrix has the same current magnitude of the binary bit current source of the lower bit. It consists of connecting four matrix of current sources.

An additional feature of the 10-bit D / A converter for image processing according to the present invention for achieving the above object is that the binary weighted current source of the lower bit is driven directly by an input binary bit without a decoder, The present invention is to use the current mirror (Current Mirror) for the implementation.

The above object and various advantages of the present invention will become more apparent from the preferred embodiments of the present invention described below with reference to the accompanying drawings by those skilled in the art.

The overall configuration of the proposed 10-bit D / A converter according to the present invention is shown in the accompanying Figure 1, the proposed circuit is designed in a mixed structure of the upper 6 bits, lower 4 bits, the circuit is 6 The bit thermometer decoder 110, the delay circuit 140, the first latch circuit 120, the second latch circuit 150, the first glitch energy suppression circuit 130, and the first glitch energy suppression circuit Deglitch Circuit 160, the LSB current source 170 and the MSB current source 180 circuit.

The input digital binary code is divided into upper 6 bits and lower 4 bits, and the upper 6 bits are converted into thermometer codes through the 6-bit thermometer decoder 110 to reduce the glitch energy and increase monotonic growth. Form is transmitted to the first latch circuit 120, and the lower 4 bits are transmitted to the second latch circuit 150 through the delay element 140 to match the time when the upper 6 bits are converted into a thermometer code. .

The first and second latch circuits 120 and 150 convert the values of the upper and lower bits, which are converted into thermometer codes in accordance with a clock, to the first and second glitch energy suppression circuits 130 and 160. The first and second glitch energy suppression circuits (Deglitch Circuit 130, 160) delays the signal to convert the signal so that the glitch does not occur, and delivers it to the current source (170, 180).

The current sources convert the signal received from the glitch energy suppression circuit into current and output the digital value by converting it into an analog value.

In this case, the proposed D / A converter is composed of the upper 6 bit thermometer code current source and the lower 4 bit binary weighted current source.

The thermometer code current source consists of a 6-bit thermometer decoder 110, a first latch 120, a first glitch energy suppression circuit 130, and a current source matrix 180, the current source matrix 180 having the same current magnitude of 4LSB. Four 63 current source matrices with are connected.

The binary weighted current source consists of four current sources, four differential current switches, a delay stage, and a glitch energy suppression circuit, which is directly driven by the input binary bits without a decoder, and is a current mirror for the implementation of binary weighted current sources. Was used.

The input bits are divided into 6 bits for the Most Significant Bit (MSB) block and 4 bits for the Least Significant Bit (LSB) block.The upper end is decoded into 64 thermometer codes by the thermometer decoder 110. One thermometer cord that is extra connects into a stack.

In addition, the output thermometer code is differentially input to the first glitch energy suppression circuit 130 together with the inverted signal, and the first glitch energy suppression circuit 130 synchronizes the input signal and is referred to by reference numeral 180a. The differential current source switch inside each cell is driven.

On the other hand, at the lower stage, the second current suppression circuit 160 directly drives the differential current source switch inside the lower current source referred to by reference numeral 170.

At this time, the output current Iout and the output voltage Vout generated by driving the upper and lower stages are represented by Equations 1 and 2, and as shown in Equation 3, the current magnitude of one MSB current source is a binary weighted current source. Has a current magnitude that is four times greater than the least significant bit of the current source.

In Equation 1, bx represents an input digital bit.

In Equation 2, R _LOAD represents the magnitude of the external resistor.

Also, the current magnitude of one MSB current source

(3.3)

(3.3)

In Equation 3, I _MSB represents a current of one current cell, and I _LSB represents a current magnitude of a current source corresponding to the least significant bit in a binary weighted current source.

FIG. 2 is a glitch energy suppression circuit diagram proposed according to the present invention, FIG. 3 is an exemplary input and output waveform diagram of a glitch energy suppression circuit proposed according to the present invention, and FIG. 4 is proposed according to the present invention. D & D_bar and U & U_bar waveforms are shown for the glitch glitch energy suppression circuit.

The basic principle is to move the crossing point of the input signal to VDD for N-type transistors and to ground for P-type transistors, so that either of them is always in conduction during switching to prevent them from turning off at the same time. can do.

In the previous papers, there are two ways to change the intersection point by using asymmetry output with different rise and fall times and a slight delay just before rise or fall. In the former case, the latter method is preferred because of the asymmetry of the current source output due to the asymmetry of the input signal.

The basic structure and operation of the circuit are as follows. The design of the circuit allows the output of the circuit to be symmetrical, so the path of the signal is also symmetrical. With two inverters facing each other, each was latched and an additional biased delay element was added.

At this time, the (W / L) ratio of the biased delay elements M5 and M6 should be determined by the relationship of Equation 9 to be described later.

If the rise time and fall time of the signal through the device is defined by the equation, respectively, the rise time is defined by equation (4), the fall time is defined by equation (5).

는 수학식 6과 같이 정의된다.Variables in Equations 4 and 5

Is defined as in Equation 6.

의 관계는 수학식 7과 같이 정의된다.In addition, the variables in Equations 4 and 5

Is defined as in Equation 7.

(3.7)

(3.7)

는 아래의 수학식 8에 의해서 계산되어진다. Therefore, average delay time of MOS gate

Is calculated by Equation 8 below.

In Equation 8, a relationship as shown in Equation 9 below may be confirmed.

하고

and

와

로 입력된다.Therefore, the input signals of the thermometer code and the binary code pass through the inverter and are converted into differential signals.

Wow

Is entered.

에 논리상태 High(Low),

에 논리상태 Low(High)가 입력되면

,

의 값은 논리상태 High(Low)가 되며,

,

는 논리상태 Low(High)의 값을 출력한다.

Logic state at High (Low),

When logic state Low (High) is input to

,

The value of becomes the logic state High (Low),

,

Outputs the value of the logic state Low (High).

The biased transistors M5 and M6 are a kind of delay element that cause a delay of the output signal when the output is switched from the logic state "High" to the logic state "Low". In addition, the upper and lower latch stages serve to reduce the effect of charge leakage to the switch transistor, thereby stabilizing the input value to the current source switch.

,

에서의 출력은 상승신호부분에서 지연이 일어나 출력신호의 교차점이 하강하게 된다. 다만 출력 전압 스윙 폭이 작아져 전류원 스위치 구동속도 가 감소될 수 있으나, 스위치 전하누설도 감소되어 출력의 오차가 적어질 수 있다. 따라서 제안된 글리치 에너지 억제 회로를 이용하면, 전류원 스위치 트랜지스터의 종류에 상관없이 원하는 입력 신호를 선택해 사용할 수 있다. Meanwhile

,

The output at is delayed in the rising signal part, and the intersection of the output signal falls. However, the output voltage swing width may be reduced to reduce the current source switch driving speed, but the switch charge leakage may also be reduced to reduce the error of the output. Therefore, using the proposed glitch energy suppression circuit, the desired input signal can be selected and used regardless of the type of the current source switch transistor.

Figure 5 shows the characteristic curve of the proposed glitch suppression circuit according to the present invention, the maximum glitch occurred at the intermediate value of the most switching, the input code was generated when the transition from 0111111111-> 1000000000, and simulated The result of the experiment was 10.5 pVsec.

FIG. 6 is a diagram illustrating a new two-dimensional current cell switching sequence proposed according to the present invention, and illustrates a two-dimensional hierarchical symmetric centroid switching sequencing current source matrix.

Each block is laid out in a centroid manner in which a matrix of current sources symmetrical with the reference block is positioned with respect to the center point.When an input is input to the MSB block, current sources in the same order of the reference block and the symmetric block are simultaneously turned on. Each switch sequence will output 4LSB × 4 blocks = 16LSB of current.

Conventional hierarchical symmetrical switching method is a one-dimensional method, it was difficult to apply to the current source matrix structure, but the method proposed in the present invention can be applied to the matrix structure because the switching order is determined in two dimensions hierarchical, symmetrical In order to determine the switching order, the following method is used.

First, the columns are fixed based on the hierarchical structure of the column and the symmetrical sequence arrangement, and then the cells facing each other are ordered while changing the sequencing order of the column structure and the symmetrical switching order. If this is explained in detail. The number in the cell of FIG. 6 represents the order in which the current source is turned on. If you look at the order in which the cells are turned on, you can see that 1,2,3,4,5,6,7,8 turns on diagonally with each other. Then you can see that 9, 10, 11, 12, 13, 14, 15 and 16 are turned on. At this time, 1 and 9 are located on the same line in the horizontal direction, and also 2 and 10, 3 and 11, 4 and 12, 5 and 13, 6 and 14, 7 and 15 You can see that times, 8 and 16 are on the same line. That is, the current cells are turned on in the same order as described above, and the switching order does not change when only the vertical axis is viewed.

By applying this order, the slope and symmetry errors are reduced in both rows and columns within the 8 * 8 local matrix. Since the current sources in the symmetric matrix are turned on at the same time, the slope error systematically in the entire current source matrix is canceled with each other. In other words, the new switching method and the central layout method can be used to achieve the double error correction effect.

The amount of current in the current source is adjusted at the bias stage. To display 2 ¹⁰ (= 1024) steps at a low voltage of 3.3V, a bias circuit with a low minimum output voltage is needed, so an improved cascode bias circuit is used.

7 is a circuit diagram of a current source bias circuit according to the present invention, which generates a minimum saturated output voltage by adjusting a bias voltage of VB1 at M1.

As the aspect ratio of M1 is k times smaller than the aspect ratios of M2 and M3, the bias voltage VB1 can be obtained as shown in Equation 10 below.

At this time, since the bias voltage (VGS-VT) of the current source transistor used to determine the device ratio of the cascode current source is equal to the value of VB1, 1.2V is substituted.

Here, VT is a threshold voltage, and ΔV is a saturation voltage applied to the sources and drains of M2 and M3, which is represented by Equation 11 below.

Ideally, when k is 4, VB1 becomes VT + 2ΔV, so the cascode current source will cause all transistors to operate at the edge of the saturation region with a minimum operating saturation output voltage of 2ΔV, but due to the bulk effect or process variable error It can escape from the saturation region.

Therefore, the value of k of M1 is set to 5 so that the cascode current source operates in a stable saturation region. This improved cascode bias circuit reduces the saturation voltage of the current source by about VT compared to the conventional cascode bias circuit, operating the entire D / A converter at a supply voltage of 3.3V.

After setting the external output resistance of the D / A converter to 50Ω and adding the total current to 16mA, the device ratio (W / L) and the unit current can be determined using Equation 12 below.

는 총 전류의 크기와 같다. 그러므로 계산된 소자비의 값은 약 0.3이며, 단위 전류의 크기는 15.64 uA이다.N is the resolution of the D / A converter, ILSB is the unit current magnitude,

Is equal to the magnitude of the total current. Therefore, the calculated device ratio is about 0.3, and the unit current is 15.64 uA.

Therefore, in consideration of the minimum area, device ratio, and unit current, the device ratio of the unit current source transistor is set to 3/9, and the voltage swing value corresponding to the total current is 0.8V.

8 is an upper bit (1MSB) switch current source circuit diagram, in which the current source transistor M1 generates unit current by the bias voltage VB1, and the switching transistors M3 and M4 adjust the direction of the current according to the input from the glitch suppression circuit. .

Since the relationship between the output impedance and INL is represented by Equation 13 below, the cascode transistor M2 is connected to improve the INL characteristics and reduce the nonlinearity due to the finite output resistance.

I _unit is the LSB current source, RL is the external resistance, N is the total number of current sources, and Z _imp is the output impedance. As the M2 transistor was cascoded, the output resistance increased from g _m3 r _o3 r _o1 to g _m3 g _m2 r _o2 r _o3 r _o1 .

In addition, Figure 9 is a lower bit (1, 2, 4, 8 MSB) switch current source circuit diagram, the current size of the upper current source is four times larger than the current size of the lower current source, and receives the same input signal to the four current source matrix Four MSB current sources are turned on simultaneously, resulting in a total size of 16LSB. The upper bit current source can be realized by four times (×) the device ratios of the transistors M1 _MSB and M2 _{MSB to} the device ratios of the M1 _LSB and M2 _LSB .

In order to improve the matching characteristics by increasing the channel length, the current source transistor is composed of four 1LSB-sized current sources. M3MSB and M4MSB are composed of differential pairs to control the current direction by differentially inputting the signal from the glitch suppression circuit.

While the invention has been shown and described in connection with specific embodiments thereof, it is well known in the art that various modifications and changes can be made without departing from the spirit and scope of the invention as indicated by the claims. Anyone who owns it can easily find out.

As described above, according to the present invention, when using the glitch energy suppression circuit (Deglitch Circuit) according to the present invention can solve the disadvantage that the frequency performance is limited due to the glitch energy in the output during high speed operation.

In addition, by suppressing the glitch energy effectively, high speed and high resolution D / A converter designs are possible.

In addition, the proposed new two-dimensional current cell switching order can maintain high linearity by minimizing slope and hierarchical errors caused by process and structural problems.

In addition, by using the glitch suppression circuit and the new two-dimensional current cell switching sequence according to the present invention, both linear and dynamic frequency characteristics, which are static characteristics, can be improved.

Claims (6)

An upper bit thermometer decoder that divides the input digital binary data into upper bits and lower bits but converts the thermometer data into a 64-bit form in order to reduce glitch energy and increase monotonous increase by receiving upper bits of data; A delay element for receiving a lower bit and delaying the upper bit during an operation time of the upper bit thermometer decoder; A first glitch energy suppression circuit that receives the output signal of the higher-bit thermometer decoder and delays the signal when converting the logic state to convert the signal so that glitches are not generated and output the converted signal; A second glitch energy suppression circuit which receives the output signal of the delay element and converts the signal to delay the signal during conversion of the logic state so that the glitch does not occur; A binary weighted current source of a lower bit that converts the signal received from the second glitch energy suppression circuit into a current and outputs the converted digital value to an analog value; And Including a higher-order thermometer code current source matrix for converting the signal received from the first glitch energy suppression circuit into a current to output a digital value is converted to an analog value, Wherein said current source matrix has a two dimensional hierarchical structure and a symmetrical switching order. The method of claim 1, A first latch receiving an output signal of the higher bit thermometer decoder and synchronizing with an arbitrary drive clock to deliver the first signal to the first glitch energy suppression circuit; And a second latch configured to receive the output signal of the delay element in synchronization with the driving clock of the first latch and to transfer the output signal to the second glitchy energy suppression circuit. The method according to claim 1 or 2, And the higher bit thermometer decoder uses a 6 bit thermometer decoder. The method of claim 1, And the upper bit thermometer code current source matrix is formed by connecting four 63 current source matrices having the same current magnitude of the lower bit binary weighted current source. The method of claim 1, Wherein the lower bit binary weighted current source is directly driven by the input binary bit without a decoder, and uses a current mirror to implement a binary weighted current source. In the two-dimensional current cell switching method of the D / A converter, Fixing based on a hierarchical, symmetric sequence of columns; And ordering cells facing each other horizontally and vertically while changing the sequencing order of the columnar hierarchy and the symmetrical switching order in all cases.

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