JP2002246911A - Resistance ladder-type digital/analog converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a resistance ladder-type digital/analog converter which is simple in structure and is high in accuracy. SOLUTION: This resistance ladder-type digital/analog converter is equipped with a resistance ladder composed of unit resistors 10 connected in series, and switches 14, which correspond to the unit resistors 10 and select one of divided voltages which are obtained by dividing a reference voltage by the resistance ladder as an analog output voltage by digital input signals. When a resistance ladder-type digital/analog converter is laid out on a semiconductor integrated circuit chip, the unit resistors 10 and the switched 14 are arranged alternately on the same line, and the unit resistors 10 are connected together with metal wirings 13 to form a resistance ladder. The total resistance value of the unit resistors 10 and the metal wirings 13 is set identical through the overall length of the resistance ladder, including a folding metal wiring 15.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a resistance ladder type digital-to-analog converter, and
The present invention relates to a layout structure of a resistance ladder type digital / analog converter using S (Metal Oxide Silicon) transistors.

[0002]

2. Description of the Related Art As is well known, a resistance ladder type digital / analog converter (hereinafter referred to as a "D / A converter") has 2 ⁿ resistors (referred to as unit resistance) between two reference voltages. the pressure in series connection min, switching the 2 ⁿ pieces of resistive partial pressure in the 2 ⁿ switch, refers to a signal converter which they were taken out as an analog output voltage. Here, n is the number of bits of the digital input signal to be input to the switch. Such D / A converters have been known for a long time, but in recent years, demands for integrated circuits with mixed analog signals have been increasing. Video and CCD (Charge Coupl
In applications related to (ed Device), the number of bits n of the digital input signal is significantly increased.

An analog output voltage corresponding to a digital input signal is generated by dividing a voltage applied to a resistor ladder by resistance. Therefore, in order to improve the accuracy of a D / A converter, a relative error of each unit resistor is suppressed to be low. There is a need. Therefore, when the D / A converter is implemented by a semiconductor integrated circuit, when arranging the unit resistors on the integrated circuit chip, some measures are taken such as making the shapes and arrangement intervals of the unit resistors the same. However, when the number n of bits of the digital input signal increases, it is difficult to arrange the unit resistors in one column due to the layout, and the efficiency becomes poor.

Therefore, conventionally, as shown in a schematic diagram of the element arrangement shown in FIG. 8, the unit resistors 40 are folded back in the middle of the resistor ladder to form a two-dimensional array. Since the row of the resistor ladder and the row of the switches 44 are formed on different lines, the same contact 42 is provided between adjacent unit resistors 40.
, But the folding is performed by the metal wiring 43. A resistor 41 having a resistance value R / 2 that is half of the unit resistance 40 is arranged at both ends of the metal wiring 43 to make the resistance ladder uniform.

As described above, since the metal wiring 43 made of a material different from that of the unit resistance 40 is used for folding the resistance ladder,
The resistance arrangement of the resistance ladder is as shown in FIG. In FIG. 9, R is the resistance value of the unit resistor 40, and R / 2 is the resistor 41.
, R is the wiring resistance value of the metal wiring 43, r ′ is the wiring resistance value of another folded portion (not shown), and SW indicates the switch 44. The wiring resistances r and r ′ are parasitic resistances that are not considered in the circuit design, and the wiring resistance r or r ′ is added to the resistance value R of the unit resistance 40 at the folded portion. Also, in the simple folding method, as shown in FIG.
The wiring resistance is r at the position where the size of the switch SW is turned back, and r ′ at the position where the switch SW is simply turned back.

As a result, the expected resistance value R cannot be obtained in the folded portion. As a countermeasure, even if the resistance value of the folded portion is adjusted to the resistance value of the other portion in consideration of the resistance values of the wiring resistances r and r ′, the constituent materials are different between the unit resistance 40 and the metal wiring 43. Manufacturing variations do not match. After all, not all the resistance values can be equalized, so that the irregularity of the resistance value is D /
This is output as an error of the analog output voltage of the A converter.

When this kind of conventional technique is searched for in a patent publication, Japanese Patent Laid-Open Publication No. Hei 7-86949 was detected. The "digital / analog converter" described in this publication includes a switch for selecting any connection point of the resistor strings by a digital input signal, a correction resistor network connected in series to the resistor strings, and any one of the correction resistor networks. A correction switch for selecting the connection point, and an adder for adding a common output of the switch connected to the resistor strings and a common output of the correction switch. This eliminates the error due to the parasitic resistance generated at the folded portion of the resistor string by the correction resistor network, virtually eliminates the digital-to-analog conversion error voltage, improves its linearity, and performs D / A conversion with high accuracy. Is going to be transformed.

[0008] Another search result, Japanese Patent Laid-Open Publication No.
In the "D / A converter" described in Japanese Patent No. 5423 (Prior Art 2), all switches connected to the unit resistance are configured by a parallel connection of a P-channel MOSFET and an N-channel MOSFET, and the switch element is not used. This prevents the non-uniformity of the stress with respect to the diffusion resistance, which is generated when the IC chip of the D / A converter is incorporated into the mold package where the stress is strong due to the uniform arrangement.
The primary purpose is to prevent the relative accuracy of the unit resistance from deteriorating due to the ezoelectric effect).

FIG. 10 is a layout pattern diagram on a semiconductor integrated circuit for a 6-bit resolution D / A converter described in Japanese Patent Application Laid-Open No. 3-235423. 6
3 bits in the digital input signal bits next are decoded digital input signals X1 to X8, it is used to select one of 2 ^three switches. The remaining 3 bits of the digital input signal is used to select one from among the 2 ^three analog output voltage 01 to 08 connected to the selected switch. Also in FIG.
As shown in FIGS. 8 and 9, metal wiring is recognized at the folded portion. Further, it can be seen that the strings of the unit resistors and the switch rows are arranged on different lines as shown in FIG. Unlike the resistor strings shown in FIG. 9, the VDD terminal and the ground terminal at both ends of the resistor string reciprocate so that they are adjacent to each other. Are made to be the same.

[0010]

However, in the above-mentioned prior art 1, the error due to the parasitic resistance generated at the folded portion is eliminated by installing the correction resistor network.
There is a first problem that elements that are not originally required, such as a correction resistor network and a correction switch, are required, which is a negative factor in cost and mounting.

The time constant of the switch related to the D / A conversion speed is determined by the combined resistance of the resistor strings and the resistance of the switch, and the input capacitance of the switch and the adder. There is a second problem that it becomes larger.

Further, in the above-described prior art 2, regarding the folded portion, only the folded portion is equalized, an error due to a parasitic resistance generated in the folded portion is eliminated, and an attempt is made to make the resistance value uniform over the entire length of the resistor string. Since this is not the case, the error output of the analog output voltage of the D / A converter is accepted.

A first object of the present invention is to provide a highly accurate resistor ladder type D / A converter with a simple configuration.

A second object of the present invention is to provide a resistance ladder type D / A converter for lowering the wiring resistance in accordance with the unit resistance required to reduce the resistance as the number of bits of the D / A converter increases. Is to do.

[0015]

According to a first aspect of the present invention, there is provided a resistor ladder type D / A converter in which a unit resistance (10 in FIG. 1) is connected in series, and a reference voltage is divided by the resistor ladder. A resistor ladder-type digital / analog converter for extracting one of the resistive voltage divisions as an analog output voltage in response to a digital input signal. In laying out a ladder type digital / analog converter on a semiconductor integrated circuit chip, unit resistors and switches are alternately arranged on the same line, and the unit resistors are connected by metal wiring (13 in FIG. 1). The resistance ladder is constituted, and the total resistance value of the unit resistance and the metal wiring is equalized over the entire length of the resistance ladder.

According to the present invention, as described above, the unit resistors and the switches are alternately arranged on the same line and the unit resistors are connected by metal wiring. The total resistance value of the resistor and the metal wiring can be easily equalized over the entire length of the resistor ladder including the folded portion.

The resistor ladder type D / A converter according to the second aspect of the present invention includes a resistor ladder in which unit resistors (R11 and the like in FIG. 6) are connected in series, and a reference voltage (REF in FIG. 6).
1, REF2) and switches (such as SW11 in FIG. 6) corresponding to unit resistances of a plurality of channels (two channels in FIG. 6) for independently selecting the divided resistors. Ladder type digital / analog converter for extracting one of the resistive voltage divisions as an analog output voltage (such as 01-1 in FIG. 6) from a digital input signal (such as X1-1 in FIG. 6). When laying out a digital / analog converter on a semiconductor integrated circuit chip, unit resistors and switches are alternately arranged on the same line, sandwiching the unit resistors shared by the switches of each channel, and the unit resistors are connected. A special feature is that the resistance ladder is configured by connecting with metal wiring, and the total resistance value of the unit resistance and the metal wiring is equalized over the entire length of the resistance ladder. To.

In this configuration, since one resistor ladder is shared by a plurality of channels, the chip area of the integrated circuit can be reduced as compared with a case where a plurality of layout patterns for one channel are not shared. Further, since the unit resistors and the switches are alternately arranged on the same line so as to sandwich the unit resistor shared by the switches of each channel, the switches and the unit resistors of each channel are arranged rather than arranging the elements as shown in the circuit diagram. Can be made as short as possible and have the same length.

Further, the metal wiring is a layer different from the switch,
For example, if the wiring is formed above the switch layer, the space for the metal wiring can be widened, so that the wiring resistance of the metal wiring can be reduced. Specifically, an N-type well layer (3 in FIG. 4)
The P-type diffusion layer (31, 32 in FIG. 4) formed in 9) serves as a source electrode and a drain electrode, and has a gate electrode (30 in FIG. 4) formed on an N-type well layer, and functions as a switch. P-channel MOSFET and unit resistance region formed in the same layer as the gate electrode layer (38 in FIG. 4)
A first-layer metal wiring (35 in FIG. 4) formed between the source electrode and the first terminal of the unit resistance region, and the drain electrode and the analog output signal, and formed on the upper layer of the unit resistance region;
A first terminal and a second terminal of a unit resistance region are connected to a second terminal, a first terminal and a gate electrode of an adjacent unit resistance to a digital input signal, and a second layer metal formed on the first layer metal wiring And wiring (36 in FIG. 4).

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment
The A-converter includes a resistor ladder in which unit resistors are connected in series, and a switch corresponding to a unit resistor that selects a resistor divider in which a reference voltage is divided by the resistor ladder. Ladder-type digital-to-analog converter for extracting the analog output voltage as an analog output voltage, the unit resistors and switches are alternately arranged on the same line when the resistor ladder-type digital-to-analog converter is laid out on a semiconductor integrated circuit chip. In addition, the resistance ladder is formed by connecting the unit resistors by metal wiring, and the total resistance value of the unit resistance and the metal wiring is equalized over the entire length of the resistance ladder.

According to a second aspect of the present invention, there is provided a resistor ladder type D / A converter comprising a resistor ladder in which unit resistors are connected in series, and a plurality of channels for independently selecting a resistor voltage having a reference voltage divided by the resistor ladder. With a switch for unit resistance,
A resistor ladder type digital / analog converter for extracting one of the resistive voltage divisions as an analog output voltage by a digital input signal from one switch of each channel,
In laying out the resistor ladder type digital / analog converter on a semiconductor integrated circuit chip, unit resistors and switches are alternately arranged on the same line so as to sandwich a unit resistor shared by switches of respective channels, and Are connected by a metal wiring to form a resistance ladder, and the total resistance value of the unit resistance and the metal wiring is equalized over the entire length of the resistance ladder.

[0022]

Next, embodiments of the present invention will be described with reference to the drawings.

Before entering into specific contents, the basic concept of the present invention will be described with reference to FIGS. FIG. 1 is a schematic view of an element arrangement according to the present invention, which is shown in a form that can be compared with FIG. 8 showing the prior art. In the present invention, as shown in FIG. 1, unit resistors 10 and switches 14 are alternately arranged on the same line. Between adjacent unit resistors 10,
It is connected by a contact 12 to a metal wiring 13 extending over the switch 14. The metal wiring 13 can easily have the same resistance value as the metal wiring 15 in the folded portion. Further, since the metal wiring 13 and the metal wiring 15 are arranged in the upper wiring layer, their area can be increased, and therefore, the resistance value can be reduced.

FIG. 2 shows the arrangement of resistors with respect to the element arrangement of FIG. 1, and is shown in a form that can be compared with FIG. As described above, since the unit resistances 10 and the switches 14 are alternately arranged on the same line, the total resistance value of the unit resistance 10 and the wiring resistance value of the metal wiring 13 is set to “new”. It can be regarded as the resistance value R of the unit resistance Rxx (xx is 11, 12, etc.). Further, for the same reason, it is possible to minimize the difference between the wiring resistances r and r 'shown in FIG.

FIG. 3 shows a resolution 4 according to an embodiment of the present invention.
FIG. 2 shows a circuit diagram of a bit D / A converter. In FIG.
Sixteen unit resistors R11-R14, R21-R that are connected in series between the reference voltage REF1 and the reference voltage REF2 and divide the potential difference between the reference voltage REF1 and the reference voltage REF2.
24, R31 to R34 and R41 to R44 are arranged in a matrix configuration of 4 rows and 4 columns. The horizontal axis of the matrix is the decoded digital input signals X1 to X4,
The vertical axis indicates the analog output voltages 01 to 04. Switches SW11 to SW14, SE21 to SW24, and SW31, which are P-channel MOSFETs, correspond to each unit resistor on a one-to-one basis.
To SW34 and SW41 to SW44. P-channel MOSFET constituting each switch SW
The source terminal S is connected to a resistance ladder, the drain terminal D is connected to the analog output voltage 01 to 04 on the vertical axis, and the gate terminal G is connected to the digital input signal X on the horizontal axis.

The features of the present invention are represented on the circuit diagram by unit resistors R24, R31 and R44 arranged at the folded portion of the resistor ladder. The resistance at this position is shown in FIG.
As shown in FIG. 8 and FIG. 8, the unit resistance is conventionally divided into two parts. In the present invention, the accuracy of the D / A converter is improved by setting the total resistance on the resistance ladder to the unit resistance Rxx having the same resistance value. Details of this will be described later with reference to the layout pattern diagram shown in FIG.

Two bits of the 4-bit digital input signal are decoded by a decoder (not shown) to become digital input signals X1 to X4, and the remaining two bits of the digital input signal are decoded by the decoder to be analog. It is used to select any one of the output voltages 01 to 04. In other words, the four switches SW derive the divided voltage on the resistance ladder from the source terminal S to the drain terminal D by the digital input signal X of which one is activated, and the four analog outputs to which these drain terminals D are connected. One of the voltages 01 to 04 is selected by the switch SW. Although FIG. 3 shows a D / A converter having a resolution of 4 bits in order to avoid complication of the drawing, the present invention assumes a D / A converter having a resolution of more bits. The switch is an n-channel MOSFET, or a C-channel in which n-channel and p-channel MOSFETs are connected in parallel.
A MOS configuration may be used.

FIG. 4 is a layout pattern diagram corresponding to the circuit diagram of FIG. In this layout pattern diagram, a multilayer structure is formed from bottom to top in the order of a white background, a dotted portion, a horizontal line portion, and a hatched portion. In FIG. 4, reference numeral 30 denotes a gate electrode of a switch SW to which digital input signals X1 to X4 are supplied, 31 denotes a P-type diffusion electrode corresponding to a drain terminal D of the switch SW, and 32 denotes a P-type diffusion electrode corresponding to a source terminal S of the switch SW. Reference numeral 33 denotes an N-type diffusion electrode for the back gate of the P-channel MOSFET forming the switch SW. The hatched portion 35 is the first layer metal wiring, the hatched portion 36 is the second layer metal wiring, and a small black square 37
Denotes a via hole connecting the first layer metal wiring and the second layer metal wiring, and 34 denotes a contact connecting the diffusion layer and the electrode or the first layer metal wiring. A region 39 surrounded by a dotted line including 30 to 34 is an N-type well layer.

The dotted region 38 is a unit resistance region, and is formed of a P-type high-concentration diffusion layer formed simultaneously with the formation of the source / drain regions of the P-channel MOSFET constituting the switch SW. As for the unit resistance, it is general to use N-type and P-type diffusion resistances having a high layer resistance when obtaining a high resistance value, and to use a polysilicon resistance having a low layer resistance when obtaining a low resistance value. .

Next, a method of arranging and wiring each element will be described. The switches SW and the unit resistance regions 38 are arranged vertically, and four of them are arranged vertically and four horizontally. The upper right unit resistor 38 is a unit resistor R11 connected to the reference voltage REF1, and the upper left unit resistor 38 is a unit resistor R41 connected to the reference voltage REF2. These connections are made via contacts 34 and via holes 37. The side of the unit resistor R11 opposite to the side connected to the reference voltage REF1 is:
The source electrode S of the switch SW11 disposed thereon,
That is, it is connected to the P-type diffusion electrode 32 via the first-layer metal wiring 35. In addition, it is taken out to the second layer metal wiring 36 through the via hole 37 and connected to the next unit resistance R12.

The gate electrodes G of the four switches SW in the vertical direction, that is, the gate electrodes 30 are guided to the second-layer metal wiring 36 via the via holes 37, and the digital input signal X is supplied therefrom. Four back gates B in the vertical direction
Similarly, the N-type diffusion layer 33 for G is guided to the second-layer metal wiring 36 via the via hole 37. The drain electrodes D of the four lateral switches SW, that is, the P-type diffusion electrodes 3
1 is guided to the first layer metal wiring 35, from which analog output voltages 01 to 04 are taken out. In FIG. 4, the portion where the digital input signal X and the analog output voltages 01 to 04 are actually conductors, but for convenience, the names of the signals and voltages on the conductors are used as they are.

Even when wiring is performed according to this layout method,
As shown in FIG. 4, the folded part 1 and the folded part 2 exist. The folded part 1 has a unit resistance R14 and a unit resistance R.
24, or when connecting the unit resistor R34 and the unit resistor R44, the first
The upper layer metal wiring 35 is connected by a second layer metal wiring 36. On the other hand, when connecting the unit resistor R34 and the unit resistor R44, the folded section 2 switches the switch SW2 between the unit resistor R21 and the via hole 37 above the unit resistor R31.
1 and the switch SW31 are connected by a second layer metal wiring 36. However, the folded portions 1 and 2 have different wiring lengths, and this difference can be eliminated by changing the wiring width.
Since the folded portion also uses the second layer metal wiring 36 made of the same material as the connection between the unit resistors, it is possible to design the resistance values of the total resistance including the wiring resistance of the folded portion as required. It is possible. As a result, an analog output voltage with desired accuracy can be obtained.

FIG. 5 is a layout pattern diagram for clarifying the arrangement and wiring method of each element described above. FIG.
FIG. 5A is an extracted layout pattern diagram of one of the blocks repeated four times in FIG.
5B is a layout pattern diagram when the second metal wiring 36 is deleted from FIG. 5A, and FIG.
The layout pattern diagram when the first metal wiring 35 and the via hole 37 are deleted from FIG.

Referring to FIG. 5C, the N-type well layer 3
9, P-type diffusion electrodes 31 and 32 having contacts 34 and N-type diffusion electrodes 33 are formed.
The gate electrode 30 is arranged on the upper layer of the second. Further, a unit resistance region 38 is formed in the same layer as the gate electrode 30.

In FIG. 5B, the gate electrode 30, the P-type diffusion electrodes 31, 32, the N-type diffusion electrode 33 and the contact 34
The first layer metal wiring 35 is provided. As a result, the P-type diffusion electrode 31 (the drain terminal D of the switch SW), the analog output voltage 01, and the P-type diffusion electrode 32
(Source terminal S of switch SW) is connected to contact 34 below unit resistance region 38, respectively.

In FIG. 5A, the digital input signals X0 to X4 are connected to the gate electrode 30 by the second-layer metal wiring 36. In addition, the first with respect to the unit resistance region 38
The connection of the reference voltage REF1 and the second reference voltage REF2, the connection to the next unit resistance region 38, the connection of the folded portion of the resistance ladder, and the connection between the N-type diffusion electrode 33 and the back gate BG are made by the second layer metal wiring 36. Have been.

FIG. 6 shows a resolution 4 according to another embodiment of the present invention.
FIG. 7 shows a circuit diagram of a bit D / A converter, and FIG. 7 shows a layout pattern diagram thereof. This embodiment provides two sets of 4-bit D / A converters having the same resolution as the above-described embodiment, but is characterized in that a resistance ladder is shared. 6 and 7, the same reference numerals are given to portions common to FIGS. 3 and 4. In this D / A converter, two types operate independently, that is, operate on two channels. In the digital input signal X and the analog output voltages 01 to 04, -1 and -2 are added after each symbol to distinguish channels.

In FIG. 7, switches SW of channel 1 and channel 2 are arranged so as to sandwich one unit resistor.
These are combined as a set and connected repeatedly as in FIG. As a result, the wiring connecting the switch SW of each channel and the unit resistor can be made the shortest and the same length, as compared with the case where the elements are arranged as shown in the circuit diagram of FIG. When arranged as shown in the circuit diagram of FIG. 6, for example, there is a clear difference between the wiring length from the switch SW14 of the channel 1 to the unit resistance R14 and the wiring length from the switch SW14 of the channel 2 to the unit resistance R14. The wiring length from the switch SW11 of the channel 1 to the unit resistance R11 and the wiring length from the switch SW14 of the channel 1 to the unit resistance R1
The same applies to the wiring length to No. 4. Referring to FIG. 7, it can be seen that such a difference has disappeared.

However, the length of the second layer metal wiring 36 connecting the unit resistors is such that the switch SW for one channel is 4
It becomes longer by the increase. Therefore, in order to reduce the wiring resistance of this portion, the wiring width is increased, and the wiring width of the folded portion 1 is reduced, thereby making the wiring resistance the same. As a result, the analog output voltages of channel 1 and channel 2 become completely the same, and variations between channels can be minimized.

[0040]

The first effect of the present invention is that the unit resistors and the switches are alternately arranged on the same line, and the unit resistors are connected by metal wiring. Can easily realize the same total resistance value of the unit resistance and the metal wiring, including the folded part, over the entire length of the resistance ladder. Therefore, a highly accurate resistance ladder type D / A converter with a simple configuration can be realized. It can be provided.

The second effect of the present invention is that the metal wiring connecting the unit resistance and the switch is formed in a layer different from the switch,
For example, since it can be formed above the switch layer, the space for the metal wiring can be widened, and the wiring resistance of the metal wiring can be reduced. Therefore, a reduction in resistance is required as the number of bits of the D / A converter increases. An object of the present invention is to provide a resistance ladder type D / A converter that lowers wiring resistance according to unit resistance.

Further, a third effect of the present invention is that a resistance ladder type D / A in which one resistance ladder is shared by a plurality of channels.
In the converter, the unit resistance and the switch can be alternately arranged on the same line so as to sandwich the unit resistance shared by the switch of each channel. This means that the wiring connecting to the unit resistance can be made the shortest and the same length.

[Brief description of the drawings]

FIG. 1 is a schematic view of an arrangement of elements in a D / A converter for explaining a basic configuration of the present invention.

FIG. 2 is a layout diagram of resistors with respect to the device layout of FIG. 1;

FIG. 3 shows a D / D with a resolution of 4 bits according to an embodiment of the present invention.
Circuit diagram of A converter

FIG. 4 is a layout pattern diagram corresponding to the circuit diagram of FIG. 3;

FIG. 5 is a detailed view of the layout pattern diagram of FIG. 4;

FIG. 6 shows another embodiment of the present invention, which has a resolution of 4 bits and 2 bits.
Circuit diagram of channel D / A converter

FIG. 7 is a layout pattern diagram corresponding to the circuit diagram of FIG. 6;

FIG. 8 is a schematic view of an arrangement of elements in a conventional D / A converter.

9 is a layout diagram of resistors with respect to the device layout of FIG. 8;

FIG. 10 is a layout pattern diagram of a conventional D / A converter.

[Explanation of symbols]

 01 to 04 Analog output voltage 10 Unit resistance 11, 13 Metal wiring 12, 34 Contact 14 Switch 30 Gate electrode 31, 32 P type diffusion electrode 33 N type diffusion layer 35 First layer metal wiring 36 Second layer metal wiring 37 Via hole 38 Unit resistance area 39 N-type well layer 01-1 to 04-1 Analog output voltage 01-2 to 04-2 Analog output voltage R Unit resistance REF1, REF2 Reference voltage SW switch X1 to X4 Digital input signal X1-1 to X4- 1 Digital input signal X1-2 to X4-2 Digital input signal

Claims (6)

[Claims] A resistor ladder in which unit resistors are connected in series;
A resistor ladder-type digital / analog converter for selecting a resistor divided by dividing a reference voltage by the resistor ladder, the switch corresponding to the unit resistor, and extracting one of the resistor divided as an analog output voltage by a digital input signal In laying out the resistor ladder type digital / analog converter on a semiconductor integrated circuit chip, the unit resistors and the switches are alternately arranged on the same line, and the unit resistors are connected by metal wiring. A resistance ladder type digital / analog converter, wherein a total resistance value of the unit resistance and the metal wiring is equalized over the entire length of the resistance ladder. 2. A resistance ladder in which unit resistances are connected in series,
A plurality of switches corresponding to the unit resistance, each of which independently selects a resistance voltage divided from a reference voltage by the resistance ladder, wherein one of the resistance voltage divisions is digitally input from one switch of each channel. What is claimed is: 1. A resistance ladder type digital / analog converter for extracting as an analog output voltage, comprising: The unit resistors and the switches are alternately arranged on the same line, and the unit resistors are connected by metal wiring to form the resistance ladder, and the total resistance of the unit resistance and the metal wiring A resistor ladder type digital / analog characterized in that values are equalized over the entire length of the resistor ladder. Log converter. 3. When the resistance ladder is folded back,
3. The resistance ladder type digital / analog converter according to claim 1, wherein a total resistance value of the unit resistance and the metal wiring is equalized over the entire length of the resistance ladder including the folded portion. 4. 4. The resistance ladder type digital / analog converter according to claim 1, wherein said metal wiring is formed in a layer different from said switch. 5. The resistance ladder type digital / analog converter according to claim 4, wherein said metal wiring is formed on an upper layer of said switch. 6. A gate electrode formed on a first polarity well layer using a second polarity diffusion layer formed on a first polarity well layer as a source electrode and a drain electrode, wherein the switch is used as the switch. Functional second polarity MOSFE
T, connecting a unit resistance region formed in the same layer as the layer of the gate electrode, connecting the source electrode and the first terminal of the unit resistance region, and connecting the drain electrode to the analog output signal;
A first layer metal wiring formed in an upper layer of the unit resistance region; a second terminal of the unit resistance adjacent to the first terminal and the second terminal of the unit resistance region; 6. The resistance ladder type digital / analog converter according to claim 5, further comprising a second layer metal wiring formed on the first layer metal wiring and connected to a signal.