JPS62254523A - Pcm signal encoder - Google Patents

Abstract

PURPOSE:To minimize the transmission delay and to make the titled encoder suitable for large scale integration by providing a means holding an input analog signal to a sample and holding circuit and deciding a polarity bit at the same time. CONSTITUTION:The titled encoder consists of a sample and holding circuit for an input analog signal, a digital/analog conversion circuit, a voltage comparator and a sequential comparison register. Then a non-inverting input terminal of the voltage comparator is connected to a common terminal of switches S1, S2 switching the analog input signal and ground. The analog input voltage is held and the polarity is decided to convert a PCM 8-bit data in 8 time slots (t1-t8), the transmission delay of the encoder is minimized and it is easily realized by having only to change the circuit connection without requiring any additional circuit and the this circuitry is suitable for large scale circuit integration.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a PCM signal encoder that converts an analog signal such as a telephone voice into a PCM digital signal, and particularly relates to a PCM signal encoder suitable for LSI implementation.

[Conventional technology]

Conventionally, this type of PCM signal encoder includes a sampling and holding circuit;
It consists of a digital-to-analog conversion circuit, a voltage comparator, and a successive approximation register. FIG. 3 shows the connection of the sampling and holding circuit and the voltage comparator section, and the operation of this encoder will be explained.

Analog signal input terminal MIN + Positive and negative reference voltage input terminals +VREF and -vREF Step voltage input terminals to selectively input the voltage obtained by dividing the positive or negative reference 'α juice into 16 equal parts according to the signal from the successive approximation register. Vstep
and a capacitor string e, 2C that samples and holds the input analog signal.
, 4C, ---, 128C and switches 81 to 82B controlled by successive approximation registers.

The encoder with this configuration operates according to the timing shown in FIG. 2(a). First, during the 11th period, the switches S1 and Ss are switched on.

S8. S11. S14,817,820,823゜S2
6.828 is closed, and the input signal from the analog signal input terminal VIN is connected to the capacitor series e, 2C, ---.

Charge to 128C. Next, during the t2 period, the switches 81 and 828 are opened, S2 is closed, the voltage comparator determines the polarity of the input analog signal, and outputs it to the successive approximation register from the output terminal OUT of the voltage comparator. If the determination result is a high level, the successive approximation register determines that the polarity is positive, closes the switch S3, and connects the positive reference voltage +VREF.

Also, if the level is low, the polarity is determined to be negative and the switch S
4 and is connected to the negative reference voltage -VREF. When the polarity is positive, in the 13th period, the switch 85°88, S11
．． 814 and switch 86. S'9゜812.815
is closed, the second bit is determined, and the result is output to the successive approximation register. In the period t4, if the judgment result of the second bit of the successive approximation register is high level, the switch 817. S20
Open switches 818 and 821, and if the level is low, open switches 812 and 815, close switches 811 and 814, and determine the third bit. Similarly, during the 1 s period, the 4th bit is determined by a successive approximation operation to determine which segment (1 to 8) it is in. If the third segment is determined, during the t6 period, only the capacitor 4C is connected to the switch 813 connected to the step voltage input terminal V8tep.
is closed, and the capacitors c and 2c below the third segment are connected to the reference voltage source, and the switch 86 and S9 are closed.
Capacity 80~128C of the third segment and above is grounded,
Switches 814.817.820.823 and S26 are closed. Further, a voltage of half the positive reference voltage +VREF/2 is applied to the step voltage input terminal Vstep, and the 5th and 5th bits are determined and output to the successive approximation register. In the t7 period, the successive approximation register applies a voltage of +3 VREF / 4 to the step voltage input terminal vsstep if the judgment result of the 5th bit is high level, and if the judgment result of the 5th bit is low level, a voltage of + REF / 4 is applied to the step voltage input terminal vsstep. It is controlled so that it is applied, and the 6th bit is determined. Similarly, the 7th and 8th bits are determined during the tl+'9 period by successive approximation.

By the operation described above, the input analog signal can be converted into an 8-bit PCM code. Therefore, this type of encoder requires nine time slots as shown in FIG. 2(a) to convert into an analog signal.

[Problem that the invention seeks to solve]

Now, the transmission delay between holding the analog input in this encoder and outputting the 8-bit PCM code is determined by these 9 time slots. In order to shorten the time of these 9 time slots, first, the capacitance value of the unit capacitor C is made small, and the total capacitance is made small. Second, the determination speed of the voltage comparator is increased. Third, it is possible to reduce the on-resistance of the switch, but when implementing LSI, reducing the capacitance value of the unit capacitor C means reducing the area of the capacitor, and the relative accuracy between each capacitor. is degraded, and the characteristics of the encoder are degraded. In addition, increasing the speed of the voltage comparator increases power consumption, and high gain is required to prevent deterioration of the encoder characteristics.
It is very difficult to implement a high-speed, high-gain voltage comparator. Further, in order to lower the on-resistance of the switch, the demechanism of the transistor of each switch must be made very large, which has the disadvantage of increasing the chip area of the LSI.

An object of the present invention is to provide an i-'CM encoder that minimizes transmission delay and is suitable for LSI implementation.

[Means for solving problems]

The PCM signal encoder of the present invention includes an input analog signal sampling and holding circuit, a digital-to-analog conversion circuit, a voltage comparator, and a successive approximation register. It is characterized by comprising means for holding the polarity bit and determining the polarity bit at the same time.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 shows an embodiment of the present invention. The same parts as in FIG. 3 are given the same numbers. The only difference in FIG. 1 from FIG. 3 is that the normal input terminal of the voltage comparator is connected to the common point of the switch sl, 82 that switches between the analog input signal and the ground, and the other components are are the same. FIG. 2(b) shows the operation timing of this encoder.

The operation of this encoder will be explained using FIG. 1
In one period, the same switches as in the first construction period in Fig. 2(a) are opened and closed, and the analog input voltage is
It is charged to C and holds the input voltage. In the present invention, during the t1 period, the input analog voltage is also applied to the normal input terminal of the voltage comparator, and the inverting input terminal is grounded via the switch 828, so that the polarity of the analog input voltage is determined at the same time. At this time, since the analog input signal is connected to the normal input terminal of the voltage comparator, the logic of the judgment result is inverted from that in the configuration shown in Figure 3, but this can be easily converted into logic using a successive approximation register. It is possible to convert .

Next 1. During the period, switch S1 is open and switch S2 is open.
is closed, the normal input terminal of the voltage comparator is connected to switch S2.
The structure is the same as that shown in FIG. 3. The other switch operations are similar to those in period t3 in FIG. 2(a), and the second bit is determined. Thereafter, the operation during the period t3 to t8 is the second
Similar to the operation in periods 14 to 19 in FIG. 3A, bits 3 to 8 are successively compared.

〔Effect of the invention〕

As explained above, the present invention can convert a 1'cM 8-bit data in 8 time slots from t'1 to t8 by holding the analog input voltage and determining the polarity at the same time, thereby reducing the transmission delay of the encoder. In addition, it does not require any additional circuits and can be easily realized by simply changing circuit connections, making it suitable for LSI integration.

Further, the present invention can be used not only for PCM encoders but also for determining the polarity bit or the most significant bit of a successive approximation type analog-to-digital converter having a normal sampling and holding circuit. This has the effect that it is possible to shorten the conversion time.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention, and FIG. 2(a). (b) is a timing diagram showing the operation timing of the encoder, and FIG. 3 is a circuit diagram of a conventional PCM signal encoder. VIN・−・・・Analog signal input terminal, +”REF
+V REF...Positive and negative reference voltage input terminal, Vstep...Step voltage input terminal, C
,2C,4C,-1--s128c...capacity,
81.82, ---. 828...Switch,
OUT...Output terminal.

Claims (1)

[Claims] In a PCM signal encoder comprising an input analog signal sampling and holding circuit, a digital-to-analog conversion circuit, a voltage comparator, and a successive approximation register, the polarity bit is determined at the same time as holding the input analog signal to the sampling and holding circuit. A PCM signal encoder comprising: means.