JPS63299616A - D/a converter - Google Patents

Abstract

PURPOSE:To reduce a chip size, to lower a power consumption and to execute low noise by being composed of an AM (amplitude modulation) type first D/A converting circuit, a PWM (pulse width modulation) type second D/A converting circuit and a third D/A converting circuit by a level shifting circuit. CONSTITUTION:Out of the digital data of an N bit, the data of a low-order J bit are supplied to a third converting circuit 3, the potential loaded to both edges of a partial pressure circuit at a first D/A converting circuit 1 is changed in accordance with the data of a J bit while the potential difference is constant and the potential partially pressured and removed from the partial pressure circuit. From the first D/A converting circuit 1, two approximate potentials removed from the partial pressure circuit are selected and outputted in accordance with the data of the high order M bit, further, from a second D/A converting circuit 2, either of two approximate potentials is selected and synthesized in accordance with the data of a middle order K bit and an analog signal to the digital data of the N bit is outputted. Further, the second D/A converting circuit 2 is equipped with a means to form the period to the output edge of a synthesizing means into the high impedance condition.

Description

DETAILED DESCRIPTION OF THE INVENTION (A) Industrial Application Field The present invention relates to a high-precision, high-bit D/A (digital/analog) converter, and includes devices equipped with various D/A converters, For example, it is used in speech synthesizers, CD (compact disc) players, and the like.

(B) Prior Art Conventionally, various types of D/A converters have been put into practical use. In Japanese Patent Application Laid-Open No. 57-23321, amplitude modulation (AM
A D/A converter that combines the advantages of the ) type and the pulse width modulation (PWM) type, does not require high-precision resistors, and has a high conversion speed is disclosed. However, the PWM type D/A converter has a drawback in that it has large harmonic distortion.

Patent application 14032/1986 was made to solve this problem.
This is the number. Unlike conventional PWM type D/A converters, which change the pulse width within one conversion period according to the content of digital data, this converter changes the pulse width within one conversion period by 2'M. Since the analog signal is output in a widely distributed manner according to the input digital data, the D/A
The harmonic spectrum of the analog signal that is the output of the converter is large in the high range and small in the low range, and band limitation is used to reduce harmonic distortion in the low range.

Recently, equipment that requires D/A converters, such as those used in the digital audio field, is required to be lower in price, lower in power consumption, and smaller in size, and the same requirements apply to D/A converters. has been done.

In order to reduce the size and cost of the D/A converter that combines the AM type and PWM type described in the above-mentioned Japanese Patent Application No. 14032/1980, it is sufficient to reduce the chip size. It is effective to downsize the voltage divider circuit in the AM type D/A converter, which occupies most of the parts. That is, it is sufficient if the number of bits processed by the AM type D/A converter can be reduced. However, if the number of bits processed by the AM type D/A converter is reduced, the number of bits processed by the PWM type D/A converter increases.
The base number of the counting circuit that counts the clock pulses in the conversion section becomes larger, and the conversion speed becomes slower accordingly. To avoid this, it is possible to increase the frequency of the clock pulse, but this increases power consumption, which is not preferable for battery operation. In addition, if the frequency of the clock pulse is high, switching noise will increase and unnecessary radiation will occur during mounting.
The performance as an A converter will deteriorate.

On the other hand, it is known that ordinary D/A converters generate glitch noise during data conversion due to mismatch in delay times in decoding circuits. Although it is effective to provide a sample/hold circuit after the D/A converter and perform sampling when the output of the D/A converter becomes stable, it is effective to deal with such glitch noise. If the converter is highly accurate, the sample-and-hold circuit itself must also be highly accurate and must be constructed from expensive, high-precision elements.

(8) Problems to be Solved by the Invention As mentioned above, there are various difficulties in reducing the chip size of a D/A converter that combines an AM type and a PWM type. This is an attempt to solve the problems that have made it difficult to realize a D/A converter. and,
Furthermore, it is an object of the present invention to avoid the influence of the glitch noise without using a sample-and-hold circuit using expensive high-precision elements.

(d) Means for solving the problem The present invention is a D/A converter that outputs an analog signal corresponding to N (=M+K+J) bits of digital data. a first decoder for decoding upper M bits of digital data of bits;
a voltage dividing circuit that divides the voltage between the reference potential of the decoder and the second reference potential using 2M resistors; a D/A conversion circuit, a clock generating means for generating clock pulses provided for the middle bits of the N bits of digital data, and a 2'-base counting unit for counting the clock pulses from the clock generating means. A circuit, a pulse forming circuit which inputs digital data of a middle bit among the N bits and a counting output of the counting circuit, and outputs a pulse signal corresponding to the content of the digital data of the middle bit, the pulse forming circuit; means for selecting and synthesizing one of two adjacent potentials output from the first D/A conversion circuit in accordance with a pulse signal that is an output;
a second D/A conversion circuit comprising means for forming a period in which the synthesizing means does not select either of the adjacent potentials and puts the output end of the synthesizing means in a high impedance state; Among them, the circuit is provided for the lower J bits and is connected between the first reference potential and one end of the voltage divider circuit, and between the second reference potential and the other end of the voltage divider circuit. According to the contents of the digital data of the lower J bits among the N bits,
A third D comprising means for changing the resistance values of the first and second resistance networks while keeping the sum of the resistance values of the first resistance network and the second resistance network constant. /A conversion circuit.

(*) The lower J bit data of the N bit digital data is given to the third conversion circuit, and the voltage is applied to both ends of the voltage dividing circuit in the first D/A conversion circuit according to the J bit data. The potential is changed while the potential difference is constant, and the potential divided and taken out from this voltage dividing circuit is changed.

Then, the first D/A converter circuit selects and outputs the 21st adjacent one taken out from this voltage divider circuit according to the data of the upper M bits, and further, the second D/A converter circuit selects and outputs, One of these two adjacent potentials is selected and combined according to the middle bit data, and an analog signal corresponding to N bits of digital data is output. And furthermore,
The second D/A conversion circuit includes means for forming a period in which the output end of the combining means is in a high impedance state, so that data can be converted during the period.

(F) Embodiment FIG. 1 is a schematic diagram of a D/A converter according to the present invention. (1) is the first D/A conversion circuit, and the input N (=
A decoder (11) that decodes the upper M bits of digital data of M+K+J) bits, and a voltage divider circuit (12) that is composed of 21 resistors R and divides the potential difference between the potentials applied to both ends thereof. The decoder (
11) from the voltage dividing circuit (12) in accordance with the output of the adjacent 2
It consists of a switching circuit (13) that selects and extracts the potentials Vt and V*.

(2) is a second D/A conversion circuit, which includes a clock pulse generator (21) that generates clock pulses, and a clock pulse generator (21) that counts clock pulses from the clock pulse generator (21).
It inputs a decimal counting circuit (2M), the middle bit data of the N bits, and the output from the counting circuit (2M), and outputs a pulse signal with a pulse width corresponding to the N bit data. A pulse forming circuit (23) and a gate circuit (2) for gating the pulse output of the pulse forming circuit (23).
4) and two switching transistors (25a) and (25b) that perform complementary switching operations, and the first D/A conversion is performed in response to the pulse signal that has passed through the gate circuit (24). A selective synthesis circuit (25) that selects and synthesizes one of the two adjacent potentials VI+V output from the circuit (1), and RC integration circuits (26).

) and a low-pass filter (26). (3
) is a level shift circuit serving as a third D/A conversion circuit, and is connected to the first reference potential Vref 1 and the voltage dividing circuit (12
), and between the second reference potential Vref 2 and the other end of the voltage dividing circuit (12). This level shift circuit (3) is inputted with the data of the lower J bits among the N bits, and according to this data, the potential applied to both ends of the voltage dividing circuit (12) is changed while maintaining the potential difference. change.

Below, it is referred to as N-16, and its human power data ala + a, 4.
..., a, the 8 bits (M-
8) Intermediate a tra to the second D/A conversion circuit (2)
8+ a m + a, 4 bits (K=4), lower as, ago at, a to the third D/A conversion circuit (3)
A case will be described in which the configuration is such that 4 bits of s (J=4) are provided.

FIG. 2 is a circuit configuration diagram of a level shift circuit (3) which is a third D/A conversion circuit. This level shift circuit (
3) is the voltage divider circuit (12) of the first D/A converter circuit (1)
and the first reference potential Vref 1, and the second reference potential Vre
The data a of the lower J bits is provided between f2 and
ss azt a++ aa is given. Voltage divider circuit (
12) A resistor RI+R1 is connected between one end and Vref 1.
eRs and R4 are connected in series in this order, and a resistor R1 is connected between the other end of the voltage dividing circuit (12) and Vref 2.
°R=, Rt, and Rs are connected in series in this order.

A series circuit of a resistor R9 and a switching transistor T is connected between both ends of the resistor R so as to be on the voltage dividing circuit (12) side. Similarly, resistors R2, R3, R
4, R, , R1, R, , R, each with a resistor RIB@
R11* Rtte RI3* R1at Rts, R
ta, respectively, and the switching transistor T*,
Ts, T4 + Tg l 'rl l Ty l
The series circuit with each of Ta is a voltage divider circuit (12)
They are connected side by side. Moshite J (-4)
The bit data a 6 +al+ am and as are connected to switching transistors T, , T*, T-, and Ta, respectively.
directly to the gates of each of the switching transistors T5, Ts*T? +T8 via an inverter (40).

Assuming that the resistance values of the resistor R14Rl@ and the resistor R of the voltage dividing circuit (12) are as indicated by the symbols, the respective resistance values are determined so as to satisfy the following relational expression.

Rl v~, R, =R R9fegR1j snow 255X Rko (2°'-1) XR
R+a-R+a=127X R-(2"'-' 1)
X RR++-R+s= 63xR=(2”'-'-
1) xRR+1-Rts-31XR=(2"'-"
1) If the resistance value between one end A and Vref 1 of the XR voltage divider circuit (12) is RA%, and the resistance value between the other end B and Vref 2 is Ri, switching transistor T or T5 is turned on. In this case, RA or R8 is R-255R
It becomes smaller by XR/(255R+R)-R/256.

Similarly, when T or T is turned on, RA or R is R
/12B When T or T is turned on, RA or R8 is R/T4
Or, when T is turned on, RA or R3 becomes smaller across Ri3.

Due to the presence of the inverter (40), the switching transistors T, ~T, and T, ~T are turned on and off in a complementary manner, so that regardless of the direction of a0~a, the difference between vrefl and Vref2 is The resistance value Rj between is Rj=(2”+8
-15/256) maintained at R. That is, while the potential difference between point A and point B is kept constant, RAIR8 is set to 0, R/256, 2R/256, etc. according to the values of a0 to a. ..., 15R/25
6, the level of the divided voltage output terminal of the voltage dividing circuit (12), that is, V, can be shifted by 16 gradations (4 pits).

Here, a case will be described in which one pit of the minimum resolution (ILSB) among N (=16) bits of data changes.

J-4 bit data a @+ a l+ a fin
When a s is a, = a-4, 1F-〇, RA-4R RR-4R15R/ 256 and the potential Vs(o) at point B is Va(0) = (Vrefl - Vref2) X
(4R-15Ri256)/Rj.

Then a,=1. al-a, core a, electric O, RA-4R
-Ri256 R1=4R-14R/256, and the potential vm(t) at point B is Va(1)= (Vrefl -Vref2) X
(4R-14Ri256)/Rj. The potential difference Etsa between vll(0) and vll(1) is E Lss-i (Vrefl'/ref2)
X R/ Rj) /. The voltage step eM between the divided voltage output terminals of the voltage dividing circuit (12) is: e M= (Vref 1 - Vref2) X R/
Rj, ELSll indicates that the potential divided by the voltage dividing circuit (12) is further divided into 1/256 (-1/2").

That is, in the level shift circuit (3), which is the third D/A conversion circuit, the input J-4 bit data a, ~
The potential that is divided and output from the voltage dividing circuit (12) is shifted in accordance with a.

In the first D/A conversion circuit (1), the input M=8-bit data ass~a is decoded by the decoder (11), and the level-shifted voltage dividing circuit (12) outputs a divided voltage. Among them, two adjacent potentials V t and V t are selectively outputted by a switching circuit (13) based on the dehood result.

Now, in the second D/A conversion circuit (2), while the 2K counting circuit (2M) counts 2K clock pulses output from the clock generator (21) (1 conversion period)
Then, a pulse signal corresponding to the input bit data a, to a4 is outputted from the pulse forming circuit (23). Third
The figure shows a schematic circuit diagram of a pulse forming circuit (23) corresponding to 14 pits.

The pulse forming circuit (23) includes the counting outputs Q, , Q, , Q, , Q of the counting circuit (2M) and the clock generating section (21).
The first, second, and third circuits receive the clock pulse CLK at their clock input terminals, and input the counting outputs Q, , Q, , Q, respectively at their D input terminals.
D flip-flop (27), <28), (2
9), a first AND gate (30) whose inputs are the back bit data a of the K-bit data, and the count output Q;
A second AND gate (to which the bit data a, the count output Q, and the output of the first D flip-flop (27) are input);
31), a third AND gate (32) into which the bit data a, the counting output Q, and the ζ output of the second D flip-flop (28) are input, and the bit data a4 and the counting output Q4.
and the ζ output of the third D flip-flop (29) as inputs, and a fourth AND gate (33) which receives these first, second,
3rd and 4th AND gates (30), (31),
Each output ClICff1lC of (32) and (33),
, C, and an OR gate (34) for inputting ,C,.
The output C6 of the OR gate (34) is output to the gate circuit (24).

In other words, the height of the digit of the input digital data and the counting circuit (2
M) Combined so that the high and low outputs are in reverse order,
AND GATE (3G>, (31), (32)
, (33), and the counting circuit (2M)
Q, , Q, , Q, other than the least significant digit of the output are also given to D flip-flops (27), (28), (29) driven by the clock pulse CLK to be counted, respectively, and these blip The output of the flop is also Q,,Q,,Q
, as well as and gates (31), (32),
(33) is given.

In order to explain the typical operation of this pulse forming circuit (23), FIG.
2nd and 3rd periods (TI) (Data '12 as -4 bit data for each period ('rs))
” (am ” 01 a s -01 a m 5lI
I Ha, = 1), data' 8 J (@ 4-Q
, B, gourd 0゜@ , -Q , @ , =l), and data 'IJ (aa-1, as=O, as-0, a, -
0) are respectively input to the second D/A conversion circuit (2). In the first period (TcI), significant information "1" is assigned to the bit data &@eat, so the first and second AND gates (30), (31
), the AND gate outputs CWt and C□ appear, respectively. -Brother 3, 4th And Gate (32), (33)
Since there is no significant information, the OR gate (34) output C0
C...

The logical sum C and I of C□ appears. This C61 is a pulse signal that represents "12" as the sum of the pulse widths, that is, the sum of the periods in which it is "1", and is approximately equally distributed over the entire first period ('re,). The pulse width and pulse period are distributed with 0゛.

In the second period ('rct), bit data a.

Only significant information '1' is input, so OR gate (3
4), the first AND gate (30) outputs CI! The pulse signal C, , which matches , can be outputted. This C0, is a pulse signal that represents "8" as the sum of pulse widths,
"1" approximately evenly throughout the second period ('rct),
These are the pulse width and pulse period in which each “0” is distributed.

Furthermore, a third period ('
rc, ), significant information '1' is input only to bit data a4, so the OR gate (34) outputs a pulse signal Cos that matches the output C48 of the fourth AND gate (33).

FIG. 5 summarizes the relationship between the pulse signal C0 output from the reject pulse forming circuit (23) and the input 4-pit digital data for one conversion period ('rc).

In this way, regardless of the input 4-bit digital data, the pulse width and pulse period change according to the input data so that the pulses are almost evenly distributed within one conversion period (Tc), °Also, the total pulse width is determined. This is the same even if the number of bits K of the input digital data is larger or smaller than 4.

The pulse signal C6 output in this way is input to the gate circuit (24). In the gate circuit (24), the pulse signal C, due to the presence of the inverter (24a),
A fifth AND gate (24b) and a sixth AND gate (24C) are input complementary to one input terminal of each, and the other input terminal of the fifth and sixth AND gates (24b>, (24c)) It is composed of a gate control circuit (24d) that outputs a gate control signal during one conversion period (' At the end of the clock generator (21), the gate control circuit (24d)
), for example, during the period (Tni-z), both the fifth and sixth AND gates (24b) and (24c) are closed. The pulse signals C* and C- that have passed through the rejection gate circuit (24) are each connected to a switching transistor (25b).
and <25a), which perform complementary switching operations, and both transistors (25a) and (25b)
The connection mode of is connected to a low-pass filter (26) to obtain an analog signal V out.

That is, while the output pulse signal C0 of the pulse forming circuit (23) is '1', the transistor (25a) is turned on,
The first potential V output from the first D/A conversion circuit (1) is selected, and while the pulse signal is 0'', the transistor (25b) is turned on and the second potential V is selected. These potentials are synthesized in time series, harmonic components are removed by a low-pass filter (26), and output.

vI output from the first D/A conversion circuit (1).

(2) can be expressed as follows from the above explanation.

V, = ((Vrefl −Vref2)/Rj)
X (4R-15R/2560(a IAX 2'
+ a l 4 X 2" + ・" + a a X
2°) R+(a.

X 2" + amX2" + aIX2' + a,
, X2°) X R/256)=Vconst+(a,
,X2'+a,,X2'+...10a,X2°)Xe
M+ (a, X2"+a, X2"+a, X2'+a, X
2°)
The output V out of the D/A converter with X (4R-15R/256 >/Rj is e M (-V + V
(7) Since the potential is divided into 16 (=2K) and combined and output, Vout = right + (at X 2" + a, X 2
” + as X 'l' + a4X 2°)Xe“
716. Therefore, Vout=Vconst+ (a,,X2'+a,4X
2'+ ...+a8×2") X ev + (a
y X 2"+as X 2"+as X 2'
+ a ay2°) Xeu/ 16 + (a, X
2" + am X 2" + a 1 X 2'+
a, X2°)eM/256 = (a+sX 27 + al 4 X 2' + ”
・+ a@X 2°+a, X2'+aiX2"+as
X2'+aaX2°+ as X 2"+a,X2"
+a, X2'+a, X2゜) X aM/256 +c
onst, that is, in FIG. 1, it is a 16-bit D/A converter with eM/256 as the LSB.

Like the conventional one, the first D/A conversion circuit and the second D/A conversion circuit
In the D/A converter of the present invention, the number of bits input to each D/A converter circuit is reduced compared to a D/A converter circuit that is a combination of only /A converter circuits. When the number of input bits in the second D/A conversion circuit (PWM type) is 8 bits, the clock frequency of the counting circuit needs to be 11.29 MHz or more, which is 2a times the sampling period of 44 degrees 1 KHz, but this is 4 If it is a bit, the clock period is 2
' 705.6KHz or higher is sufficient. This enables a high-performance D/A converter that consumes less power and has less switching noise and unnecessary radiation due to high-frequency clock pulses.

Furthermore, if the number of bits input to the first D/A conversion circuit (AM type) is reduced, the number of high-precision resistors can be reduced accordingly, and thus the chip size can be reduced. In particular, since the number of resistors is 2M, the effect is very large.

Note that the resistors used in the level shift circuit, which is the third D/A conversion circuit, are those with low resistance values of R0 to R, and R, to RI.
Since the high resistance values of M are connected in parallel and the overall resistance value is converted digitally, R9~
High precision is not required for high resistance RIMs.

For example, the minimum resolution (LSB) of 16 bits is expressed by resistors RIIR8#R,,R,, but R,
, R, and Rj+R0 (range within LSB of ±) is 1:170 to 511, and Rn, R
,.

The resistors used in the voltage divider circuit do not require high accuracy. Therefore, the amount of increase in chip size due to the addition of the third D/A conversion circuit is small.

On the other hand, the gate circuit (24) includes a gate control circuit (24d
) at the end of one conversion period (Tc) by the gate control signal of
That is, immediately before the next conversion period, the fifth and sixth AND gates (24b) and (24c) are closed for a period (Tni-2). Therefore, both AND gates (24b), (
When the chamber 24c) is closed, the switching transistors (25a) and (25b) at the subsequent stage are turned off, and the impedance becomes infinite. Then, the low-pass filter (2
6) and the operational amplifier (260F) in
The RC integration circuit (26*c
) with one end grounded (26c)
is the switching transistor (25a) in the previous stage,
(25b), the transistor (25a)
, (25b) are both in a high impedance state, they hold the potential immediately before entering the high impedance state, thus acting as a pseudo sample-and-hold circuit. Here, it is preferable that the potential immediately before being held by the capacitor (26c) is the potential (Vlo%#) at the end of discharging of the capacitor (26c), that is, by sampling and holding Vlo, glitch noise can be reduced. influence can be suppressed reliably. Such V lo
In order to hold the potential of w, as mentioned above, the charge accumulated in the capacitor (26c) is transferred to the capacitor (26c). All you have to do is choose. In this way, the RC integrating circuit (26*c), which constitutes a part of the low-pass filter (26), and the operational amplifier (2
6o,) is a switch at the end of the conversion period ('rc).
Since the chip transistors (25a) and (25b) are in a high impedance state and the capacitor (26c) has finished discharging, it operates as a sampling and holding circuit effective against glitch noise.

FIG. 6 shows another example of the third D/A conversion circuit.゛In Figure 6, the J-bit data decoder (
41), and the resistors connected in series to the voltage dividing circuit (12) are one on each side of R2° and R3°, and the resistors R1° and R1° are
One or more high resistances are connected in parallel.

That is, the resistor R2 has resistors R□, R,,,R,.

..., a series circuit of Rn and a switching transistor Tn is connected in parallel, and the transistor Tn and the resistor R8° are connected to the signal line and each resistor R11, R*x*R0.
,..., switching transistor T! between the connection mode of Rn! I* Tag e Tax *..., can be read directly. Similarly, there is a resistance RsIe on the resistance R1 side.
Rsx*Rss+...+Rm and switching transistor T3. .

TS! l Tss e..., Tm are connected.

J-bit data is input to a decoder (41). The decoder uses one of the switching transistors T□, Tag + Tag t...Tn and the switching transistors T, , T, , "l" according to the input data.
831..., one or more high resistance Rx+ + Rlt + -r Rs+ * which is determined by the turned-on transistor and emits a signal to turn on one of Tm.
Rsx * ”” etc. as R2゜lRj. are connected in parallel with each of the voltage dividing circuits (12) to level shift the divided voltage output of the voltage dividing circuit (12).

(G) Effects of the Invention As is clear from the above description, the present invention comprises a first AM-type D/A conversion circuit, a PWM-type second D/A conversion circuit, and a third D/A conversion circuit using a level shift circuit. With the D/A conversion circuit, 1
Since it consists of two D/A converters, the number of bits of data input to each conversion circuit can be reduced, reducing the chip size of the D/A converter, lowering power consumption, and reducing noise. can be achieved. Furthermore, the second D/A conversion circuit includes means for forming a period in which the output end of the combining means is in a high impedance state, so that data can be converted during the period, so that glitch noise is prevented during conversion. Even if glitch noise occurs, it is not output from the output end of the synthesizing means, and the D/A conversion output is not affected by glitch noise.

[Brief explanation of drawings]

FIG. 1 is a schematic configuration diagram of an embodiment of the present invention, FIG. 2 is a circuit configuration diagram of the conversion circuit in FIG. 3, FIG. 3 is a schematic circuit diagram of the second conversion circuit, and FIG. 4 is a pulse forming circuit. Operation explanation tie 1
1 chart, FIG. 5 is a waveform diagram showing the relationship between the input signal and output signal of the pulse forming circuit, and FIG. 6 is a circuit configuration diagram of another embodiment of the third D/A conversion circuit. (1)...First D/A conversion circuit, (2)...Second D/A conversion circuit, (3)...Third D/A conversion circuit, (11)...・Decoder, (12)... Voltage divider circuit, (13)... Switching circuit, (21)
... Clock generation section, (2M) ... Counting circuit,
(23)...Pulse forming circuit, (24)...Gate circuit, (25)...Selective synthesis circuit,' (26
)...Low pass filter.

Claims (2)

[Claims] (1) In a D/A converter that outputs an analog signal corresponding to N (=M+K+J) bits of digital data, there is a decoder that decodes the upper M bits of the N bits of digital data, a first reference potential and a second reference potential. A first D/A comprising: a voltage dividing circuit that divides the voltage between the voltage and the reference potential of the decoder using 2^M resistors; and means for selectively extracting two adjacent potentials from the voltage dividing circuit according to the output of the decoder. a conversion circuit; a clock generation means for generating clock pulses provided for the middle K bits of the N bits of digital data; a 2^K counting circuit for counting the clock pulses from the clock generation means; A pulse forming circuit receives digital data of the middle K bits among the bits and the count output of the counting circuit and outputs a pulse signal according to the contents of the digital data of the middle K bits, and the output of the pulse forming circuit is means for selecting and combining one of the two adjacent potentials output from the first D/A conversion circuit in response to a pulse signal, the combining means selecting neither of the two adjacent potentials; a second D/A conversion circuit comprising means for forming a period in which the output terminal is in a high impedance state; first and second resistor networks connected respectively between one end of the voltage divider circuit and between the second reference potential and the other end of the voltage divider circuit; lower J bits among N bits; Depending on the content of the digital data,
A third D comprising means for changing the resistance values of the first and second resistance networks while keeping the sum of the resistance values of the first resistance network and the second resistance network constant. /A conversion circuit. (2) The pulse forming circuit generates a pulse signal whose pulse width and pulse period change according to the contents of digital data of middle K bits, and whose pulse width in 2^K clock periods is determined in total. The D/A converter according to claim 1, wherein the D/A converter outputs an output.