KR0182183B1 - Mode-changeable audio data output circuit - Google Patents

Abstract

The present invention relates to an audio data output circuit capable of mode switching, comprising: counting means for latching n-bit audio data input in serial data form in synchronization with a clock signal by one bit, and the n-bit A first selecting means for receiving audio data of one as an input and receiving final output data of the counting means as another input and selecting one input data according to a selection signal and outputting it to the first input terminal of the counting means; A control signal for generating the selection signal for controlling the first selection means and a clock signal for controlling the counting means and controlling the output format of the audio data according to a mode selection signal input from the outside, that is, the audio data Bit signal to control by bit unit, word unit unit Mode conversion means for outputting a word clock signal for control and a left / right clock signal for control for each left / right channel, and second selection means for selecting audio data latched in the counting means in accordance with the mode selection signal. The present invention relates to an audio data output circuit for allowing a user to listen to audio data of a desired sound quality according to a mode selected by a user.

Description

Audio data output circuit which can change mode

The present invention relates to an audio data output circuit capable of mode conversion. More specifically, the present invention relates to a mode in which a user can listen to audio data of a desired sound quality by changing an output format of audio data for each mode selected by the user. The present invention relates to an audio data output circuit that can be converted.

In general, referring to a process of outputting audio data, an analog audio signal is converted into a digital signal by an analog-to-digital converter (ADC) and input to a signal processor (DSP). The signal processor performs sound-field processing and sound quality adjustment, and each digital signal outputted through the left and right / right channels after the processing is completed is a digital-to-analog converter (DAC). After conversion, it is converted into an analog signal and can be heard by the user.

However, in the audio data output method as described above, the format of the data output through the left and right channels is fixed to only one of 20 bits or 16 bits, respectively.

Therefore, such a conventional data output method has a problem in that the user has a poor selectivity to select a sound quality according to his or her taste.

Accordingly, an object of the present invention is to solve the above-mentioned problems, and the user can directly select various output modes of the audio data, and by varying the output format of the audio data for each selected mode, the user can select the sound quality data. It is to provide an audio data output circuit capable of one mode conversion so that it can be heard.

1 is a block diagram of an audio data output circuit capable of mode conversion according to an embodiment of the present invention.

2 is a detailed circuit diagram of a mode conversion circuit according to an embodiment of the present invention;

3 is a timing diagram illustrating an output format of audio data in mode 0 according to an embodiment of the present invention.

4 is a timing diagram illustrating an output format of audio data in case of Mode 1 according to an embodiment of the present invention.

5 is a timing diagram showing an output format of audio data in case of Mode 2 according to an embodiment of the present invention.

6 is a timing diagram illustrating an output format of audio data in mode 3 according to an embodiment of the present invention.

The present invention for achieving the above object is a counting means for latching the n-bit audio data input in the form of serial data in synchronization with a clock signal by one bit, and the n-bit audio data First selecting means for receiving one input, receiving the final output data of the counting means as another input, selecting one input data according to a selection signal, and outputting the selected input data to the first input terminal of the counting means; 1 generating a selection signal for controlling the selection means and a clock signal for controlling the counting means, the control signal for controlling the output format of the audio data according to a mode selection signal input from the outside; Bit clock signal to control in bit unit, word clock signal to control in word unit And mode switching means for outputting left / right clock signals for controlling for each left / right channel, and second selecting means for selecting audio data latched in the counting means in accordance with the mode selection signal.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art can easily implement the present invention in detail.

1 is a block diagram of an audio data output circuit capable of mode conversion according to an embodiment of the present invention, and FIG. 2 is a detailed circuit diagram of a mode conversion circuit according to an embodiment of the present invention.

As shown in FIG. 1, in an audio data output circuit capable of mode switching according to an embodiment of the present invention, first, a ring counter 10 is input in serial form in synchronization with an input mode clock signal MODCLK. The 40-bit audio data D39: 0 is latched by 1 bit.

The multiplexer 20 receives the audio data D39: 0 through one input terminal D0, and receives the final output terminal data S0 of the ring counter 10 as another input terminal D1. Selects the input data and outputs it to the first input terminal D39 of the ring counter 10. First, the audio data D39: 0 is selected according to the load control signal LOADL used as the selection signal. After latching bit by bit (10) and the process is completed, the final output terminal data SO of the ring counter 10 is selected to circulate the latched audio data.

The mode conversion circuit 30 generates a load control signal LOADL for controlling the multiplexer 20 and a mode clock signal MODCLK for controlling the ring counter 10, and selects a mode input from the outside. According to signals MODE0 and MODE1, various control signals BCLK, WCLK, and LRCLK for controlling the output format of the audio data are output.

Next, the de-flip-flop 40 delays the output data S39 of the ring counter 10 by one bit in synchronization with the mode clock signal MODCLK generated from the mode conversion circuit 30 (S40). Output

Finally, the multiplexer 50 is configured to output the audio data S35 and S39 latched to the ring counter 10 and the output signal S40 of the de flip-flop 40 according to the mode selection signals MODE0 and MODE1. Select one to output (SDAT).

The mode converting circuit 30 has a 16-bit mode (MODE0 = 1, MODE1 =) in accordance with the de-flop 31 for dividing the clock frequency CLK of 2.8224 MHz into two and the mode selection signals MODE0 and MODE1. 0) and the mode discrimination unit 32 for discriminating the 20-bit mode, and the output signal of the flip-flop 31 is selected in the case of the 16-bit mode according to the output signal of the mode determination unit 32. In the bit mode, the multiplexer 33 selects the clock frequency CLK and outputs it as a bit clock signal BCLK, and a 6-bit counter that counts the output signal of the multiplexer 33 as a clock input. 34 and a write 12-bit removing unit 35 for receiving the output signals Q4, Q3, and Q2 of the 6-bit counter 34 to remove the right 12 bits of the word clock signal WCLK. In response to the output signals Q4, Q3, and Q2 of the 6-bit counter 34, left of the word clock signal WCLK Le ft) A left 12-bit remover 36 for removing 12 bits and an output signal of the write 12-bit remover 35 are received as a data input D2 and an output signal of the left 12-bit remover 36 is received. Receives the data inputs D0 and D3 and receives the mode selection signals MODE0 and MODE1 as the selection inputs S0 and S1, respectively, the multiplexer 37 for selecting one data according to the selection input, and a high level voltage. Receive (+) as the data input D1 and receive the output signal Q5 of the 6-bit counter 34 as the other data input D0, one data according to the output signal of the mode discriminating unit 32. In the case of 20-bit mode, the multiplexer 38 for selecting the < RTI ID = 0.0 > and the output signals Q4-Q0 < / RTI > of the 6-bit counter 34 and the output signal of the multiplexer 38 are logically combined. Load control signal (LOADL) stays 'high' while counting 32 / 64-bit selector 39 for outputting a load control signal LOADL that maintains a high state while the 32-bit clock signal is counted in the 16-bit mode and the multiplexers 33 and 37. ) And the inverted signal of the output signal of the multiplexer 37 and the mode clock signal generator 3A for generating the mode clock signal MODCLK by combining the output signal of the 32 / 64-bit selector 39. Receives the output signal Q3 of the 6-bit counter 34 to the other data input D0 by receiving the data input D1 and selects one data according to the output signal of the mode determining unit 32. The multiplexer 3B for generating the word clock signal WCLK and the output signals Q4 and Q5 of the 6-bit counter 34 are respectively received as data inputs D1 and D0 of the mode discriminating unit 32. The left / right clock is selected by selecting one data according to the output signal. And a multiplexer 3C for generating the clock signal LRCLK.

Here, the mode determining unit 32 includes an inverter 1 for inverting the mode selection signal MODE0, and a NOR gate 2 for negating and ORing the output signal of the inverter 1 and the mode selection signal MODE1. It consists of).

The write 12-bit remover 35 includes an OR gate 3 for ORing the output signals Q3 and Q2 of the 6-bit counter 34, an output signal of the OR gate 3, and the 6 bits. It consists of an AND gate 4 for ANDing the output signal Q4 of the counter 34.

The left 12-bit remover 36 includes an AND gate 5 for ANDing the output signals Q3 and Q2 of the 6-bit counter 34, an output signal of the AND gate 5, and the 6 bits. It consists of the NOR gate 6 for carrying out the negative OR of the output signal Q4 of the counter 34. As shown in FIG.

The 32 / 64-bit selector 39 includes an AND gate 7 for ANDing the output signals Q2, Q1, and Q0 of the 6-bit counter 34 and the output signal of the 6-bit counter 34. And an AND gate 8 for ANDing the output signals of the multiplexer 38 with (Q4, Q3), and a NAND gate 9 for negative ANDing the output signals of the AND gates 7 and 8. .

The mode clock signal generator 3A includes an OR gate A for ORing the output signals of the multiplexers 33 and 37, an output signal of the multiplexer 33, and the 32 / 64-bit selector 39. OR gates B for ORing the output signals of ") and AND gates C for ANDing the output signals of the OR gates A and B.

Operation of the audio data output circuit capable of mode switching according to the embodiment of the present invention configured as described above is as follows.

The present invention is to change the output format of the audio data for each mode (Mode) selected by the user, as shown in Figure 1 ring counter 10, multiplexer (20, 50), mode conversion circuit 30 And a de-flop flop 40 or the like.

First, the input signal of the multiplexer 20 is divided into 40 bits of audio data D39: 0, left 20 bits, and right 20 bits. The multiplexer 20 receives new audio data when the load control signal LOADL is 'low', and latches the input audio data in synchronization with the mode clock signal MODCLK in the ring counter 10 when the load control signal LOADL is 'low'. Be sure to

Some of the data latched to the ring counter 10 (S35, S39) are input to the multiplexer 50 together with the output data S40 of the de-flip-flop 40, and mode selection signals MODE1 and MODE0. According to this, one data is selected and output in units of 20 bits or 16 bits.

FIG. 2 is a detailed circuit diagram of the mode conversion circuit 30, in which the flip-flop 31 divides an input clock frequency CLK of 2.8224 MHz into two. The multiplexer 33 which receives the divided clock frequency and the undivided clock frequency CLK as data inputs D1 and D0 respectively selects one data according to the output signal of the mode discriminator 32. When the mode selection signal MODE1 is 'low' and MODE0 is 'high' (mode 1), the output signal of the mode determination unit 32 becomes 'high' so that the multiplexer 33 selects the clock frequency divided by two. As a result, the bit clock signal BCLK is doubled to 16-bit mode.

The word clock signal WCLK for controlling the audio data D39: 0 in word units is changed into four types (WCLK0 to WCLK3) according to each mode, and mode 0 (MODE1 = MODE0 = 0) And mode 3 (MODE1 = MODE0 = 1), the circuit for removing the left 12 bits from the word clock signal is the left 12-bit remover 36, and in the case of mode 2 (MODE1 = 1, MODE0 = 0), the word clock is The circuit for removing the write 12 bits from the signal is the write 12 bit remover 35.

3 to 6 are timing charts showing the output format of audio data in the mode 0 to mode 3 according to the embodiment of the present invention.

First, in the case of mode 0 (MODE1 = MODE0 = 0), the word clock signal WCLK0 is generated as shown in FIG. 3, and the mode clock signal MODCLK is input as the clock signal of the ring counter 10. The left 20 bits S40 to S21 and the right 20 bits S20 to S1 are sequentially output from the audio data S40.

Next, in the case of mode 1 (MODE1 = 0, MODE0 = 1), the word clock signal WCLK1 is generated as shown in FIG. 4 as a 16-bit mode, and the left 16 bits (S35) to audio data S35 are generated. S20 and the write 16 bits S19 to S4 are sequentially output.

In the case of mode 2 (MODE1 = 1, MODE0 = 0), the word clock signal WCLK2 is generated as shown in FIG. 5, and the left 20 bits (S39 to S20) and the right 20 bits from the audio data S39 are generated. (S19 to S0) are sequentially output.

In the case of mode 3 (MODE1 = MODE0 = 1), as shown in FIG. 6, the word clock signal WCLK3 is generated, from the audio data S39 to the left 20 bits (S39 to S20) and the right 20 bits (S19). S0) are output sequentially.

In this case, referring to the difference between the mode 2 and the mode 3, in the case of the mode 2, the audio data is first outputted and the write 12 bits of the word clock signal WCLK2 are removed, and in the case of the mode 3, the audio data Is output later and the left 12 bits of the word clock signal WCLK3 are removed.

Therefore, the effect of the mode data switchable audio data output circuit according to an embodiment of the present invention is that the user can listen to the audio data of the desired sound quality according to the mode selected by the user.

Claims (6)

Counting means for latching n-bit audio data input in the form of serial data in synchronization with a clock signal by one bit, and receiving the n-bit audio data as one input and receiving the last counting means. First selection means for receiving output terminal data as another input, selecting one input data according to a selection signal, and outputting the input data to a first input terminal of the counting means, a selection signal for controlling the first selection means, and A control signal for generating a clock signal for controlling a counting means and for controlling an output format of the audio data according to a mode selection signal input from an external device, that is, a bit clock for controlling the audio data in units of bits. Signal, word clock signal for word unit control and left / right channel control A left / light mode conversion means for outputting a clock signal and a second audio selection means data output circuit, which consists, including according to the mode selection signal for selecting the audio data latched in the counting means. The apparatus of claim 1, wherein the mode converting means comprises: a de-flop for dividing an input clock frequency into two, a mode discriminating unit for discriminating a 16-bit mode and a 20-bit mode according to a mode selection signal, and the mode discriminating unit. According to an output signal, a first multiplexer for selecting the output signal of the flip-flop in the 16-bit mode and the clock frequency in the 20-bit mode and outputting it as a bit clock signal and an output signal of the first multiplexer A counter for performing counting by receiving a clock input, a write 12-bit removing unit for removing write 12 bits of the word clock signal by receiving the output signal of the counter, and a left of the word clock signal receiving the output signal of the counter A left 12-bit remover for removing 12 bits, the write 12-bit remover and a left 12-bit remover A second multiplexer for receiving an output signal as a data input and a mode selection signal as a selection input, receiving a high level voltage as one data input, receiving a high level voltage as one data input, and receiving a different output signal from the counter. In the case of a 20-bit mode in which a third multiplexer for receiving one data input and selecting one data according to an output signal of the mode discriminator and a logic combination of an output signal of the counter and an output signal of the third multiplexer are logically combined. Outputs a load control signal that remains 'high' while the 64 bit clock signals are counted, and outputs a load control signal that remains 'high' while the 32 bit clock signals are counted in 16-bit mode. Mode by combining a 32 / 64-bit selector with output signals of the first and second multiplexers and a 32 / 64-bit selector A mode clock signal generator for generating a clock signal, an inverted signal of the second multiplexer output signal as one data input, and an output signal of the counter as another data input; A fourth multiplexer for generating a word clock signal by selecting one data and receiving the output signal of the counter as a data input, and selecting one data according to an output signal of the mode discriminator to generate a left / right clock signal. An audio data output circuit comprising a fifth multiplexer for generating. The audio data output circuit according to claim 2, wherein said clock frequency is 2.8224 MHz. The audio data output circuit as claimed in claim 2, wherein the counter is a 6 bit counter. The audio data output circuit as claimed in claim 1, wherein the counting means is a ring counter. 6. The audio data output circuit according to claim 5, wherein the output terminal of the ring counter further includes a de-flip for delaying the output data of the ring counter by one bit in synchronization with a mode clock signal.